EE213 Digital Integrated Circuits II. Lecture 10: Timing Clock & Power Distribution

Transcription

1 EE213 Digial Inegraed Circuis II Lecure 10: Timing Clock & Power Disribuion Prof. Pingqiang Zhou ShanghaiTech Universiy School of Informaion Science and Technology EE213-L10-Timing_Clock_Power.1 Pingqiang, ShanghaiTech, 2018

2 Maerials were parly aken from EE141: Digial Inegraed Circuis, Spring hp://bwrcs.eecs.berkeley.edu/classes/icdesign/ee141_s 10/index.hm Chaper 10 Chaper 9/12 EE213-L10-Timing_Clock_Power.2 Pingqiang, ShanghaiTech, 2018

3 Review: MIPS Processor crysal oscillaor 2-phase clock generaor ph1 ph2 rese MIPS processor memread memwrie wriedaa memdaa adr exernal memory EE213-L10-Timing_Clock_Power.3 Pingqiang, ShanghaiTech, 2018

4 Pipelining a REG a REG CLK log REG Ou CLK REG REG log REG Ou b REG CLK b REG CLK CLK CLK CLK Reference CLK Pipelined EE213-L10-Timing_Clock_Power.4 Pingqiang, ShanghaiTech, 2018

5 Ouline Timing basics Cycle ime and race margin Clock skew and jier Lach-based pipeline Clock Generaion Disribuion Power disribuion EE213-L10-Timing_Clock_Power.5 Pingqiang, ShanghaiTech, 2018

6 Review: Timing Parameers of Flip-Flop T EE213-L10-Timing_Clock_Power.6 Pingqiang, ShanghaiTech, 2018

7 Review: Timing Parameers of Lach EE213-L10-Timing_Clock_Power.7 Pingqiang, ShanghaiTech, 2018

8 Synchronous Timing clk-q clk-q,min su hd p,max p,min clk-q clk-q,min su hd R1 and R2 can be Laches or Flip-Flops EE213-L10-Timing_Clock_Power.8 Pingqiang, ShanghaiTech, 2018

9 Timing Consrains clk-q clk-q,min su hd p,max p,min clk-q clk-q,min su hd Cycle Time (max) T clk Q, R 1 p, max su, R 2 Race Margin (min) hd, R 2 clk Q, min p, min EE213-L10-Timing_Clock_Power.9 Pingqiang, ShanghaiTech, 2018

10 Review: Three Sequencing Mehods EE213-L10-Timing_Clock_Power.10 Pingqiang, ShanghaiTech, 2018

11 Max-Delay: Flip-Flops clk clk F1 Q1 Combinaional Logic D2 F2 T c clk pcq seup Q1 pd D2 EE213-L10-Timing_Clock_Power.11 Pingqiang, ShanghaiTech, 2018

12 Min-Delay: Flip-Flops clk F1 Q1 CL D2 clk F2 c d h o l d c c q clk Q1 ccq cd D2 hold EE213-L10-Timing_Clock_Power.12 Pingqiang, ShanghaiTech, 2018

13 Max-Delay: 2-Phase Laches D1 Q1 Combinaional D2 Q2 Combinaional D3 Logic 1 Logic 2 L1 L2 L3 Q3 1 2 T c D1 pdq1 Q1 pd1 D2 pdq2 Q2 pd2 D3 EE213-L10-Timing_Clock_Power.13 Pingqiang, ShanghaiTech, 2018

14 Min-Delay: 2-Phase Laches 1 L1 Q1 CL D2 1 2 L2 nonoverlap c d 1, c d 2 h o l d c c q n o n o v e r l a p Hold ime reduced by nonoverlap. 2 ccq Q1 cd D2 hold EE213-L10-Timing_Clock_Power.14 Pingqiang, ShanghaiTech, 2018

15 Max-Delay: Pulsed Laches p p D1 L1 Q1 Combinaional Logic D2 L2 Q2 T c D1 pdq (a) pw > seup Q1 pd D2 p (b) pw < seup Q1 D2 pcq T c pw pd seup EE213-L10-Timing_Clock_Power.15 Pingqiang, ShanghaiTech, 2018

16 Min-Delay: Pulsed Laches p L1 Q1 CL c d h o l d c c q p w p D2 L2 p pw hold Q1 ccq cd D2 EE213-L10-Timing_Clock_Power.16 Pingqiang, ShanghaiTech, 2018

17 Ouline Timing basics Cycle ime and race margin Clock skew and jier Lach-based pipeline Clock Generaion Disribuion Power disribuion EE213-L10-Timing_Clock_Power.17 Pingqiang, ShanghaiTech, 2018

18 Clock Nonidealiies Clock skew Spaial variaion in emporally equivalen clock edges; deerminisic + random Clock jier Temporal variaions in consecuive edges of he clock signal Variaion of he pulse widh Imporan for level sensiive clocking EE213-L10-Timing_Clock_Power.18 Pingqiang, ShanghaiTech, 2018

19 Sources of Clock Skew and Jier 4 power supply 1 clock generaion PLL 2 3 inerconnec clock drivers 6 capaciive load 7 capaciive coupling Skew manufacuring device variaions in clock drivers inerconnec variaions environmenal variaions (power supply and emperaure) 5 emperaure Jier clock generaion capaciive loading and coupling environmenal variaions (power supply and emperaure) EE213-L10-Timing_Clock_Power.19 Pingqiang, ShanghaiTech, 2018

20 Clock Skew # of regisers Earlies occurrence of Clk edge Nominal /2 Laes occurrence of Clk edge Nominal + /2 Nominal delay Max Clk skew Clk delay EE213-L10-Timing_Clock_Power.20 Pingqiang, ShanghaiTech, 2018

21 Clock Skew and Jier Clk SK Clk JS EE213-L10-Timing_Clock_Power.21 Pingqiang, ShanghaiTech, 2018

22 Posiive and Negaive Skew In R1 D Q Combinaional Logic R2 D Q Combinaional Logic R3 D Q??? CLK CLK1 CLK2 CLK3 delay delay (a) Posiive skew In R1 D Q Combinaional Logic R2 D Q Combinaional Logic R3 D Q??? CLK1 CLK2 CLK3 delay delay CLK (b) Negaive skew EE213-L10-Timing_Clock_Power.22 Pingqiang, ShanghaiTech, 2018

23 Posiive Clock Skew Clock and daa flow in he same direcion In clk D R1 1 > 0 Q clk1 2 Combinaional logic T T + delay 3 > 0 4 R2 D Q clk2 T : + hold T + c-q + plogic + su so T c-q + plogic + su - hold : hold + cdlogic + cdreg so hold cdlogic + cdreg - > 0: Improves performance, bu makes hold harder o mee. If hold is no me (race condiions), he circui malfuncions independen of he clock period! EE213-L10-Timing_Clock_Power.23 Pingqiang, ShanghaiTech, 2018

24 Negaive Clock Skew Clock and daa flow in opposie direcions In R1 D Q clk1 Combinaional logic T delay R2 D Q clk2 clk 1 T < 0 4 T : T + c-q + plogic + su so T c-q + plogic + su - hold : hold + cdlogic + cdreg so hold cdlogic + cdreg - < 0: Degrades performance, bu hold is easier o mee (eliminaing race condiions) EE213-L10-Timing_Clock_Power.24 Pingqiang, ShanghaiTech, 2018

25 Clock Jier - Longes Logic Pah Clk T Clk-Q T T LM T SU T JI + Laes poin of launching Earlies arrival of nex cycle EE213-L10-Timing_Clock_Power.25 Pingqiang, ShanghaiTech, 2018

26 Impac of Clock Jier on Cycle Time clk Q p, max su, R 2 T jier jier T 2 clk Q p, max su, R 2 jier Wors Case Scenario (Negaive Skew + Jier) T 2 clk Q p, max su, R 2 jier - EE213-L10-Timing_Clock_Power.26 Pingqiang, ShanghaiTech, 2018

27 Clock Jier - Shores Pah Earlies poin of launching Clk T Clk-Q T Lm Clk T H Nominal clock edge Daa mus no arrive before his ime EE213-L10-Timing_Clock_Power.27 Pingqiang, ShanghaiTech, 2018

28 Impac of Clock Jier on Race Margin clk Q, min p, min jier hd jier Wors Case Scenario (Posiive Skew + Jier) hd 2 jier + clk Q, min p, min EE213-L10-Timing_Clock_Power.28 Pingqiang, ShanghaiTech, 2018

29 Impac of Clock Skew and Jier Cycle Time - Posiive skew improves performance - Negaive skew reduces performance - Jier reduces performance T 2 clk Q p, max su, R 2 jier - Race Margin - Skew reduces race margin - Jier reduces accepable skew cu : clock uncerainy hd 2 jier + clk Q, min p, min cu : clock uncerainy EE213-L10-Timing_Clock_Power.29 Pingqiang, ShanghaiTech, 2018

30 Summary: Clock Skew and Jier Clock skew The deerminisic (knowable) difference in clock arrival imes a each flip-flop Caused mainly by imperfec balancing of clock ree/mesh Accouned for in STA by calculaing he clock arrival imes a each flip-flop Clock jier The random (unknowable, excep disribuion ) difference in clock arrival imes a each flip-flop Caused by on-die process, V DD, emperaure variaion, PLL jier, crossalk, Saic iming analysis (STA) accuracy, layou parameer exracion (LPE) accuracy Accouned for in STA by subracing (~3 ) from he cycle ime in long pah analysis, and adding o receiving clock arrival ime in race analysis Jier is always bad, skew can be helpful or harmful. Clock uncerainy skew jier Long pah analysis Race analysis FF skew Logic FF clk FF skew FF clk -jier +jier EE213-L10-Timing_Clock_Power.30 Pingqiang, ShanghaiTech, 2018

31 Ouline Timing basics Cycle ime and race margin Clock skew and jier Lach-based pipeline Clock Generaion Disribuion Power disribuion EE213-L10-Timing_Clock_Power.31 Pingqiang, ShanghaiTech, 2018

32 Lach-Based Pipeline EE213-L10-Timing_Clock_Power.32 Pingqiang, ShanghaiTech, 2018

33 Lach-Based Design Basic Analysis EE213-L10-Timing_Clock_Power.33 Pingqiang, ShanghaiTech, 2018

34 Slack-Borrowing EE213-L10-Timing_Clock_Power.34 Pingqiang, ShanghaiTech, 2018

35 Time Borrowing (a) Lach Combinaional Logic Lach Combinaional Logic Lach Borrowing ime across half-cycle boundary Borrowing ime across pipeline sage boundary 1 2 (b) Lach Combinaional Logic Lach Combinaional Logic Loops may borrow ime inernally bu mus complee wihin he cycle EE213-L10-Timing_Clock_Power.35 Pingqiang, ShanghaiTech, 2018

36 Summary: Lach vs. Flip-Flop In a Lach-Based sysem - Daa can pass hrough lach while i is ransparen - Long cycle of logic can borrow ime ino nex cycle as long as each loop finished in one cycle In a Flip-Flop-Based sysem - Daa launches on one rising edge and mus arrive before nex rising edge - If daa arrives lae, sysem fails - If daa arrives early, wasing ime - Flip-flops have hard edges Flip-Flop generally easier o use - Mos digial ASICs designed wih regiser-based iming Bu, Laches (pulsed and level-sensiive) allow more flexibiliy - And hence can poenially achieve higher performance - Laches can also be made more oleran of clock uncerainy EE213-L10-Timing_Clock_Power.36 Pingqiang, ShanghaiTech, 2018