Digital Microelectronic Circuits ( ) Dynamic Logic. Lecture 10: Presented by: Adam Teman

Transcription

1 Digial Microelecronic Circuis ( ) Presened by: Adam Teman Lecure 10: Dynamic Logic 1

2 Moivaion Las lecure, we learned abou Pass Transisor Logic. Using his echnique (i.e. passing a signal hrough a diffusion inpu in addiion o he gae inpu), we were able o reduce he number of ransisors needed o implemen several logic gaes. However, pass ransisors presened several disadvanages, such as V T drop, saic power dissipaion, loss of regeneraive propery, and in cerain siuaions, slow ransiions. In his lecure, we will discuss anoher concep dynamic logic and is implemenaion ino an efficien and very fas logic family. 2

3 Wha will we learn oday? 10.1 Dynamic CMOS 10.2 Charge Loss 10.3 Charge Sharing 10.4 Cascading Dynamic Gaes 10.5 Logical Effor of Domino 3

4 Dynamic CMOS 10.2 Charge Loss 10.3 Charge Sharing 10.4 Domino Logic 10.5 LE of Domino So now we d like o reduce some gaes and speed up our calculaions. I s ime for DYNAMIC LOGIC 4

5 Inroducion So far, we ve seen ha:» Sandard CMOS require 2N ransisors for N inpus.» Pseudo nmos requires only N+1 ransisors, bu has high saic power consumpion.» PTL is only efficien for cerain funcions An alernaive logic syle called Dynamic Logic provides:» N+2 Transisors for N Inpus» Low Saic Power Consumpion» High Operaion Speed Dynamic Logic provides a very differen approach o gae implemenaion, defining i as a compleely differen syle han he previously discussed Saic families. 5

6 Dynamic Logic Concep Dynamic Circuis operae in wo phases:» Precharge: se an iniial oupu sae» Evaluaion: change he precharged oupu o he legal sae. This is done wih a basic archiecure ha includes:» A sandard PDN nework» Complemenary precharge swiches This is an n-ype nework. The same can be accomplished using a p-ype Pull-Up nework. 6

7 Dynamic Logic Concep - Precharge Precharge occurs when he clock is low, blocking he discharge pah and enabling he pull up pah. The oupu capaciance is charged o 1 hrough he op pmos (he Precharge Transisor). The boom nmos eliminaes saic curren and raioed behavior. 7

8 Dynamic Logic Concep - Evaluaion Evaluaion occurs when he clock is high. The Precharge Transisor is urned off, blocking any addiional charge from flowing o he oupu capaciance. The boom nmos (he Evaluaion Transisor) is urned on, enabling a condiional pah o ground. The oupu is discharged, depending on he inpu values and he combinaional funcion of he PDN, similar o saic logic families. 8

9 Example Dynamic Inverer When he clock is low, he capaciance is charged. When he clock goes high, he oupu is discharged if he inpu is high. If he inpu is low, he oupu says high. clk precharge evaluae precharge evaluae P1 V DD 0 C ou A 1 0 A N2 V ou N1 9

10 Dynamic Logic Properies The operaion of Dynamic Logic brings abou a number of imporan properies:» N+2 Transisors are required for gae implemenaion.» The logic is Non-Raioed (i.e. sizing doesn affec funcionaliy).» Saic Power Consumpion is low, bu Dynamic Power Consumpion is significanly higher han Sandard CMOS.» The Swiching Speeds are higher han Sandard CMOS due o Reduced Load Capaciance, Zero Shor-Circui Curren and abiliy o Opimize Only One Swing ( phl ). 10

11 Dynamic Logic VTC An Ineresing (Bizarre) VTC» Remember assume DC» Unil V Tn, he oupu is V OH.» Once we pass V Tn, here is no parially open pmos combaing he PDN, so in a DC perspecive, oupu will fully discharge.» The VTC drops STRAIGHT down o V OL.» (If no DC, bu bounded wih ime, he VTC will be more gradual ) V DD V ou NM L =V Tn. This is very low! V Tn V DD V in 11

12 Logical Effor of Dynamic Logic A W 2W C ou phl: R R 2 n eq R 2 C A 2C C g d gmin 3C dmin inv p R gae d, gae LE R inv R C C d,min gae g, gae R inv C C g,min W : p 0, LE 0 plh Therefore, we ge a very fas gae! For a 2-inpu NAND, we ge: p NAND 4, LENAND

13 Dynamic Logic Problems The basic consideraion of using Dynamic vs. Saic Logic is Speed vs. Power. However, High Oupu Degradaion can occur in Dynamic Logic in he following cases:» Inpu Gliches» Leakage Currens» Charge Sharing» Cascading dynamic gaes 13

14 Dynamic CMOS 10.2 Charge Loss 10.3 Charge Sharing 10.4 Domino Logic 10.5 LE of Domino The Big Problem wih Dynamic gaes is heir CHARGE LOSS 14

15 Problem #1: Charge Loss Dynamic Logic only pulls up he oupu during he Precharge Phase. Therefore, any curren ha is discharged can only be replenished a he nex clock phase. If a low inpu (ha cus off he PDN, leaving a high oupu) gliches from 0 o 1, a pah o ground emporarily opens, discharging some of he oupu. In addiion, Saic Leakage Curren hrough he large nmos ransisors degrades he oupu level. 15

16 Inpu Glich Example clk P1 A A N2 C ou N1 V ou 16

17 Soluion: Bleed Devices To figh he Charge Loss in an oupu node, a Bleed Device can be added: A small Pseudo-nMOS syle pmos is he basic implemenaion» This causes V OLmin >0.» Saic Curren Dissipaion. 17

18 Example Bleed Device We have o carefully size he bleed device o rade off level compensaion and saic curren. To find he saic curren, assume he gae is in evaluaion wih A= 1. P1 PB PB C ou C ou A N2 N2 N1 N1 18

19 Example Bleed Device We now find he minimum oupu level. We can replace he wo nmos ransisors wih a single nmos wih L eq =L 1 +L 2 (assuming hey were sized wih an equivalen W) I lin I vel. sa PB Neq PB k Neq VDD VTn Vou Vou kpb VDD VTp VDsa, p 0.5V Dsa, p N2 N1 C ou PB N eq V ou 19

20 Feedback Bleed Device A beer way o aach a bleed device is using feedback. In his way he bleed device is cu off when V ou = 0 We ge: Bu:» Rail o Rail Swing» No Saic Curren» No gliching problem» We sill have o make sure he pull down nework is srong enough o flip he inverer.» We need an exra 3 ransisors* *In a few minues, we ll see ha his is almos free 20

21 Dynamic CMOS 10.2 Charge Loss 10.3 Charge Sharing 10.4 Domino Logic 10.5 LE of Domino A secondary problem of Dynamic Gaes is CHARGE SHARING 21

22 Problem #2: Charge Sharing Charge Sharing occurs when he PDN is closed, bu one or more sacked ransisors nex o he oupu are open.» The charge is shared beween he oupu capaciance and he diffusion capaciance of he conducing ransisor. One way o fix his is o Precharge hese capaciances. 22

23 Charge Sharing Example clk P1 A V final DD B B N3 V final 0 C ou A N2 C 2 V ou N1 C 1 23

24 Charge Sharing Example How much charge is los? We have o use Charge Conservaion Equaion: B P1 N3 C ou Q iniial Q final A N2 C 2 N1 C 1 Qiniial Cou VDD Q C V C2 V final ou final final Jus don forge o check if V final >V DD -V T 24

25 Dynamic CMOS 10.2 Charge Loss 10.3 Charge Sharing 10.4 Domino Logic 10.5 LE of Domino Bu he mos ineresing problem and soluion comes wih he need o hook up dynamic gaes in a logic nework, which brings us: DOMINO LOGIC 25

26 Problem #3: Cascading Dynamic Gaes The bigges drawback of Dynamic Logic is ha Dynamic Gaes canno be Cascaded:» During Precharge, he oupu of he Driving Gae is charged o V DD, urning on he PDN of he Cascaded Gae.» During he Evaluaion, i akes ime o discharge he oupu of he Driving Gae (considering i should be Low).» During his ime, he PDN of he Cascaded Gae is incorrecly conducing, discharging is oupu. 26

27 Cascading Gaes Example clk P1 V ou,1 P2 V ou,2 A N2 N4 N1 N3 A V ou,1 V ou,2 27

28 Soluion: Domino Logic One soluion o he cascading problem is using Domino Logic. Each Dynamic Gae is conneced o an Inverer, causing he inpu of he nex gae o be Low afer Precharge. This solves he cascading problem and buffering gaes provides several oher advanages. One major disadvanage occurs, hough. Can you guess wha i is? (Hin: Universaliy) 28

29 Domino Logic Example clk A A P1 N2 V ou,1 P2 0 0 V DD N4 V ou,2 V DD V ou,1 N1 N3 V ou,2 29

30 Solving he Res of Our Problems Now we can freely add our feedback bleed ransisor P1 PB V X V ou A N2 N1 30

31 Can we reduce he ransisor coun? Since he oupu of domino is always low during precharge, we don acually need he evaluaion ransisor! However, we beer be careful, because he precharge mus now propagae, creaing a consrain on he precharge ime! 31

32 Wha abou universaliy? Someimes, logic resrucuring works: ABC I I I I I I I I I I G H 32

33 Dual Rail Domino 33

34 np-cmos (NORA) Clk In 1 In 2 In 3 Clk M p PDN M e Ou1 Clk In 4 In 5 Clk M e PUN M p Ou2 (o PDN) Only 0 1 ransiions allowed a inpus of PDN Only 1 0 ransiions allowed a inpus of PUN 34

35 np-cmos Clk In 1 In 2 In 3 Clk M p PDN M e Ou1 Clk In 4 In 5 Clk M e PUN M p Ou2 (o PDN) o oher PDN s o oher PUN s 35

36 Dynamic CMOS 10.2 Charge Loss 10.3 Charge Sharing 10.4 Domino Logic 10.5 LE of Domino Finally, le s see how domino gaes behave in a logic nework: LOGICAL EFFORT OF DOMINO LOGIC 36

37 Domino Logic Logical Effor A B W 3W 3W 2W R phl eq (NAND): min C A, B 3C W g C d R 4C dmin gmin p LE NAND NAND LE NAND p NAND 3 3 3W phl p LE NOR (NOR): NOR 5 p NOR LE NOR

38 Domino Logic Logical Effor We can improve his by using a skewed inverer For a sandard Domino NAND, we go: p NAND LE 3 NAND LENAND pnand 3 Bu if we enlarge he pmos of he inverer, we ge: plh : p INV * LEINV * LE NAND* 1 p 6 6 NAND A B W 3W 3W 4W W The Average LE (~sage effor) is: 3W LE 5 NAND *