Sequential Circuit Background. Young Won Lim 11/6/15

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1 Sequential Circuit /6/5

2 Copyright (c) 2 25 Young W. Lim. Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free ocumentation License, Version.2 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license is included in the section entitled "GNU Free ocumentation License". Please send corrections (or suggestions) to youngwlim@hotmail.com. This document was produced by using OpenOffice and Octave. /6/5

3 Latches and FF's 3 /6/5

4 NOR-based SR Latch SET begins RST begins SET begins RST begins S R SET S= = S= R= S= R= S= R= S= R= S= R= S= S= R= R= S= R= R= = RESET S= = R= = HOL S= =old Hold begins Hold begins Hold begins Hold begins R= =old 4 /6/5

5 NOR-based SR Latch States HOL RESET SET NOR based SR Latch S R S= R= S= R= S= R= S= R= S= R= SET S= R= = = = = = = RESET S= R= = = S= R= HOL S= R= =old =old 5 /6/5

6 NAN-based SR Latch SET begins RST begins SET begins RST begins S R S= R= S= R= S= R= S= R= S= R= S= S= R= R= S= R= SET S= = R= = RESET S= = R= = Hold begins Hold begins Hold begins Hold begins HOL S= R= =old =old 6 /6/5

7 NAN-based SR Latch States HOL RESET SET NAN based SR Latch S R S= R= S= R= S= R= S= R= S= R= SET S= = R= = = = = = RESET S= = R= = S= R= HOL S= R= =old =old 7 /6/5

8 SR Latch Symbols HOL RESET SET NOR based SR Latch S R HOL RESET SET NAN based SR Latch S R 8 /6/5

9 Active High and Low Inputs Active High Active High Active High S S R R Active Low Active Low Active Low S S R R 9 /6/5

10 NOR-based Latch SET begins RST begins SET begins RST begins C C transparent opaque transparent opaque Hold begins Hold begins /6/5

11 NOR-based Latch HOL RESET SET NOR based Latch C C C= =X C= = C= = C= =X C= = = = C= = = = /6/5

12 Master-Slave FlipFlop Master Latch Y Y Slave Latch Y Master-Slave F/F the hold output of the master is transparently reaches the output of the slave this value is held for another half period 2 /6/5

13 Master-Slave FlipFlop Falling Edge Master Latch Y CK CK C CK C Y CK CK Slave Latch 3 /6/5

14 Master-Slave FlipFlop Rising Edge Master Latch Y CK CK CK C C Y CK CK Slave Latch 4 /6/5

15 Latch & FlipFlop Level Sensitive Latch CK= transparent CK= opaque CK C Edge Sensitive FlipFlop CK= transparent else opaque CK 5 /6/5

16 Advantages of Latches over FFs Flipflop designs are very easy to verify timing Each path between flip-flops must be less than the clock period Tools check for skew, setup, and hold time violations Short paths are padded (buffers are added to slow down the signals) Skew in flip-flop based systems affects the critical path Most designs in industry are based on flip-flops Latch designs are more flexible than a flip-flop design Need to CA tools to make sure it works Can borrow time to allow a path to be longer than clock period Can tolerate clock skew -- skew does not directly add to cycle time Less silicon area 6 /6/5

17 Latches at the output ports TRIS Latch WR TRIS C ATA Latch data bus WR port C 7 /6/5

18 Forbidden State 8 /6/5

19 NOR-based SR Latch SET begins RST begins SET begins RST begins S R S= R= S= R= S= R= S= R= S= R= S= S= R= R= S= R= Hold begins Hold begins Hold begins Hold begins 9 /6/5

20 Gated SR Latch (SR=) Forbidden state enters S R R S 2 /6/5

21 Gated SR Latch (SR= to ) RST begins S R R S R S RST 2 /6/5

22 Gated SR Latch (SR= to ) SET begins S R R S SET R S 22 /6/5

23 Gated SR Latch (SR= to ) S R R S R S 23 /6/5

24 24 /6/5 Gated SR Latch Oscillation State R S R S R S R S

25 Forbidden State Transition S R Forbidden St RESET, Hold S R Forbidden St SET, Hold S R Forbidden St Oscillation 25 /6/5

26 Classical SR Latch esign 26 /6/5

27 Master-Slave FF 27 * figures from wikipedia.org /6/5

28 Master-Slave FF opened closed Y closed Hold the last state for ½ cycle opened Y Hold the last state for another ½ cycle 28 /6/5

29 Master-Slave FF Y Y 29 /6/5

30 Master-Slave FF Y Master Latch Y Slave Latch Master- Slave F/F 3 /6/5

31 Classical Edge Triggered FF i o CLK i3 i2 o2 S o3 R Output Stage Latch Input Stage Latches =/ i4 o4 i o CLK i2 o2 CLK S i3 o3 R * figures from wikipedia.org i4 o4 3 /6/5

32 Classical Edge Triggered FF CLK= HOL op for the ouput latch CLK= SET, RESET op for the ouput latch Output Stage Latch = S= R= S S= R= S= R= = S= R= R 32 /6/5

33 Classical Edge Triggered FF reset hold set hold set hold reset hold set hold set S= S= S= S= S= S= S= S= S= S= S= R= R= R= R= R= R= R= R= R= R= R= 33 /6/5

34 Classical Edge Triggered FF CLK= HOL op for the ouput latch CLK= SET, RESET op for the ouput latch S= R= S= R= S= R= Output Stage Latch S R CLK= When = HOL RESET When = HOL SET CLK= RESET HOL SET HOL 34 /6/5

35 Output Latch Operation (Classical Edge Triggered FF) CLK= HOL op for the ouput latch CLK= SET, RESET op for the ouput latch S= R= S= R= S= R= S= R= Output Stage Latch S R CLK= When = HOL RESET When = HOL SET CLK= RESET HOL SET HOL 35 /6/5

36 Set Operation (Classical Edge Triggered FF) SET op for the ouput latch P= When CLK=, regardless of S= CLK R= CLK S= R= = P= X CLK= S= CLK= = P= P= S= CLK R= CLK P= = X CLK= S= CLK= = P= 36 /6/5

37 Reset Operation (Classical Edge Triggered FF) RESET op for the ouput latch P= When CLK=, regardless of S= CLK R= CLK P= S= R= CLK= R= CLK= = / X 37 /6/5

38 Hold Operation (Classical Edge Triggered FF) HOL op for the ouput latch P= When CLK=, regardless of S= CLK R= CLK S= R= P= CLK= R= X CLK= = P= P= S= CLK R= CLK P= CLK= S= X CLK= = P= 38 /6/5

39 Forbidden Operation (Classical Edge Triggered FF) Forbidden for the ouput latch P= Impossible to enter S= CLK R= CLK P= 39 /6/5

40 Clock Transition (Classical Edge Triggered FF) CLK= HOL op for the ouput latch CLK= SET, RESET op for the ouput latch S= R= S= R= S= R= S= R= Output Stage Latch S R CLK= When = HOL RESET When = HOL SET CLK= RESET HOL SET HOL 4 /6/5

41 Rising Edge Transition (Classical Edge Triggered FF) Rising edge CLK= P= HOL RESET / SET CLK= CLK= S= R= P= If = If = SR= SR= SR= SR= CLK= R= P= = P= CLK= CLK= S= R= P= CLK= S= = P= 4 /6/5

42 Falling Edge Transition () (Classical Edge Triggered FF) P= CLK= CLK= = S= R= P= Falling edge CLK= SET HOL SR= SR= CLK= S= = P= P= CLK= CLK= = S= R= P= CLK= S= = P= 42 /6/5

43 Falling Edge Transition (2) (Classical Edge Triggered FF) Falling edge CLK= P= RESET HOL CLK= CLK= S= R= P= SR= CLK= R= = SR= P= S= CLK= CLK= R= P= CLK= R= = 43 /6/5

44 Modern Latch esign 44 /6/5

45 Edge etector () CLK CLK EGE CLK EGE C CLK 45 /6/5

46 Edge etector (2) CLK CLK EGE CLK EGE C CLK 46 /6/5

47 Edge etector + Latch = FlipFlop CLK EGE CLK EGE CLK 47 /6/5

48 CMOS Latch esign Φ Φ Φ Φ 48 /6/5

49 CMOS FlipFlop esign Φ Φ Φ Φ Φ Φ Φ Φ Φ Φ Φ Φ 49 /6/5

50 Modern Latch esign 5 /6/5

51 Registers 5 /6/5

52 Toggling Input Shift Register Feedback Flip Flop JK Flip Flip T Flip Flop Toggling Flip Flop Pipeline Stage Register Feedback Register FSM State Register Counter Register 52 /6/5

53 Shift Register v.s. Pipeline Stage Register 3 CLK 53 /6/5

54 JKFF & TFF v.s. FSM J K inputs T A T B CLK Next State Current State S' S S' S T clk outputs CLK states : S : S : S2 : S3 S S L A L A L B L B 54 /6/5

55 Toggling FF v.s. Counter CLK Next State Current State S' S S' S clk 55 /6/5

56 FF and Register Timing 56 ecimal /6/5

57 Bus Notation 57 ecimal /6/5

58 Register I 3 I 2 I I CLK A 3 A 2 A A 58 ecimal /6/5

59 FF Timing input signal with a delay ignored (ideal case) input signal with a delay explicitly shown 59 /6/5

60 Register Timing input signal with a delay explicitly shown input signal with a delay explicitly shown 6 /6/5

61 Shift Register Timing Connected in serial, but parallel assignments 3 2 S 6 /6/5

62 Shift Register Timing Cycle SI 3 2 = SO Connected in serial, but parallel assignments CLK 3 2 S 62 /6/5

63 Shift Register Timing Cycle 2 SI 3 2 = SO Connected in serial, but parallel assignments CLK 3 2 S 63 /6/5

64 Shift Register Timing Cycle 3 SI 3 2 = SO Connected in serial, but parallel assignments CLK 3 2 S 64 /6/5

65 Shift Register Timing Cycle 4 SI 3 2 = SO Connected in serial, but parallel assignments CLK 3 2 S 65 /6/5

66 Rotate CLK SI 3 2 = SO 66 /6/5

67 ivide By 2 with a Sign Extension SI 3 2 = SO CLK 67 /6/5

68 Toggling Input CLK SI 3 2 = SO 68 /6/5

69 Register with Parallel Load EN EN I 3 I 2 I I I 4 L EN EN EN EN L CLK CLK 4 A 3 A 2 A A A 69 /6/5

70 Ripple Counter I 3 I 2 I I I 4 EN EN EN EN CLK CNT 4 A 3 A 2 A A A 7 /6/5

71 Synchronous Binary Counter I 3 I 2 I I I 4 L CLK EN EN EN EN EN CLK 4 A 3 A 2 A A A 7 /6/5

72 Counters 72 /6/5

73 Toggling Input Shift Register Feedback Flip Flop JK Flip Flip T Flip Flop Toggling Flip Flop Pipeline Stage Register Feedback Register FSM State Register Counter Register 73 /6/5

74 JKFF & TFF v.s. FSM J K inputs T A T B CLK Next State Current State S' S S' S T clk outputs CLK states : S : S : S2 : S3 S S L A L A L B L B 74 /6/5

75 Toggling FF v.s. Counter CLK Next State Current State S' S S' S clk 75 /6/5

76 Toggle Count own A 3 CK 3 A 2 CK 2 A CK A CK CLK 76 /6/5

77 Toggle Count Up A 3 CK 3 A 2 A CK A CK CK 2 CLK 77 /6/5

78 Ripple Counter multiple clocks I 3 = A 3 I 2 = A 2 I = A I = A I 3 I 2 I I I 4 EN EN EN EN CNT CLK 4 A A 3 A 2 A A 78 /6/5

79 79 /6/5 Toggle Conditions A A 2 A 3 CK A C = C = A C 2 = A A C 2 = A A A 2

80 Toggle Conditions A i A i A i x+ = x x+ = x A i C i C i I 3 = C 3 xor A 3 I 2 = C 2 xor A 2 I = C xor A I = C xor A C 3 = A 2 A A EN C 2 = A A EN C = A EN C = EN 8 /6/5

81 Synchronous Binary Counter a single clock toggle Ai toggling condition EN I 3 = C 3 xor A 3 I 2 = C 2 xor A 2 I = C xor A I = C xor A C 3 = A 2 A A EN C 2 = A A EN C = A EN C = EN I 3 I 2 I I I 4 CLK EN CLK 4 A 3 A 2 A A A 8 /6/5

82 82 /6/5 Toggle Conditions A A 2 A 3 CK A C = C = A C 2 = A A C 2 = A A A

83 Synchronous Upown Counter a single clock toggle Ai up counting condition down counting condition I 3 = C 3 xor A 3 I 2 = C 2 xor A 2 I = C xor A I = C xor A C 3 = A 2 A A EN C 2 = A A EN C = A EN C = EN C 3 = A 2 A A EN C 2 = A A EN C = A EN C = EN toggle Ai toggling condition I 3 = G 3 xor A 3 I 2 = G 2 xor A 2 I = G xor A I = G xor A G 3 = S A 2 A A + S A 2 A A EN G 2 = S A A + S A A EN G = S A + S A EN G = EN S= Up Counting S= own Counting 83 /6/5

84 References [] [2] M. M. Mano, C. R. Kime, Logic and Computer esign Fundamentals, 4 th ed. [3] J. Stephenson, Understanding Metastability in FPGAs. Altera Corporation white paper. July 29. /6/5

Capacitor in an AC circuit

Capacitor in an AC circuit Copyright (c) 2011 2017 Young W. Lim. Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.2