- DQ0 - NC DQ1 - NC - NC DQ0 - NC DQ2 DQ1 DQ CONFIGURATION. None SPEED GRADE

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1 SYNCHRONOUS DRAM 52Mb: x4, x8, x6 MT48LC28M4A2 32 MEG x 4 x 4 S MT48LC64M8A2 6 MEG x 8 x 4 S MT48LC32M6A2 8 MEG x 6 x 4 S For the latest data sheet, please refer to the Micron Web site: Features PC00 and PC33compliant Fully synchronous; all signals registered on positive edge of system clock Internal pipelined operation; column address can be changed every clock cycle Internal banks for hiding row access/precharge Programmable burst lengths:, 2, 4, 8, or full page Auto Precharge, includes CONCURRENT AUTO PRECHARGE, and Auto Refresh Modes Self Refresh Mode 64ms, 8,92cycle refresh LVTTLcompatible inputs and outputs Single +3.3V ±0.3V power supply Options Part Number Example: MT48LC32M6A2TG75:C Marking Configurations 28 Meg x 4 32 Meg x 4 x 4 banks 28M4 64 Meg x 8 6 Meg x 8 x 4 banks 64M8 32 Meg x 6 8 Meg x 6 x 4 banks 32M6 WRITE Recovery t WR t WR = 2 A2 Plastic Package OCPL 2 54pin TSOP II 400 mil TG 54pin TSOP II 400 mil LeadFree P Timing Cycle Time CL = 2 PC33 7E 4 CL = 3 PC33 75 Self Refresh Standard None Lowpower L Operating Temperature Commercial 0 o C to +70 o C None Industrial Temperature 40 o C +85 o C IT 3 Revision :C. Refer to Micron Technical Note TN Offcenter parting line. 3. Contact factory for availability. 4. Available on x4 and x8 only Figure : Pin Assignment Top View 54Pin TSOP x4 NC NC 0 NC NC NC NC NC x8 0 NC NC 2 NC 3 NC NC The # symbol indicates signal is active LOW. A dash indicates x8 and x4 pin function is same as x6 pin function. CONFIGURATION 32 MEG X 4 X 4 S 6 MEG X 8 X 4 S 8 MEG X 6 X 4 S Refresh Count 8K 8K 8K Row Addressing 8K A0 A2 8K A0 A2 8K A0A2 Bank Addressing 4 BA0, BA 4 BA0, BA 4 BA0, BA Column Addressing 4K A0 A9, A, A2 Key Timing Parameters SPEED GRADE x6 VDD 0 VD 2 VssQ 3 4 VD 5 6 VssQ 7 VDD ML WE# CAS# RAS# CS# BA0 BA A0 A0 A A2 A3 VDD CLOCK FREQUENCY ACCESS TIME 2K A0 A9, A CL = 2* CL = 3* SETUP TIME K A0A9 HOLD TIME 7E 43 MHz 5.4ns.5ns 0.8ns MHz 5.4ns.5ns 0.8ns 7E 33 MHz 5.4ns.5ns 0.8ns MHz 6ns.5ns 0.8ns x6 Vss 5 VssQ 4 3 VD 2 VssQ 0 9 VD 8 Vss NC x8 7 NC 6 NC 5 NC 4 NC MH CKE A2 A A9 A8 A7 A6 A5 A4 Vss M x4 NC NC 3 NC NC NC 2 NC M 52mbfront.fm Rev. G 2/04 EN 2004 Micron Technology, Inc. All rights reserved. PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.

2 General Description The 52Mb is a highspeed CMOS, dynamic randomaccess memory containing 536,870,92bits. It is internally configured as a quadbank DRAM with a synchronous interface all signals are registered on the positive edge of the clock signal,. Each of the x4 s 34,27,728bit banks is organized as 8,92 rows by 4,096 columns by 4bits. Each of the x8 s 34,27,728 bit banks is organized as 8,92 rows by 2,048 columns by 8bits. Each of the x6 s 34,27,728bit banks is organized as 8,92 rows by,024 columns by 6bits. Read and write accesses to the are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed BA0, BA select the bank; A0A2 select the row. The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. The provides for programmable READ or WRITE burst lengths of, 2, 4, or 8 locations, or the full page, with a burst terminate option. An auto precharge function may be enabled to provide a selftimed row precharge that is initiated at the end of the burst sequence. The 52Mb uses an internal pipelined architecture to achieve highspeed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a highspeed, fully random access. Precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, highspeed, randomaccess operation. The 52Mb is designed to operate at 3.3V. An auto refresh mode is provided, along with a powersaving, powerdown mode. All inputs and outputs are LVTTLcompatible. s offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic columnaddress generation, the ability to interleave between internal banks to hide precharge time and the capability to randomly change column addresses on each clock cycle during a burst access. 52mbfront.fm Rev. G 2/04 EN Micron Technology, Inc. All rights reserved.

3 Table of Contents 52Mb: x4, x8, x6 Features General Description Functional Description Initialization Register Definition Mode Register Burst Length Burst Type CAS Latency Operating Mode Write Burst Mode Commands INHIBIT NO OPERATION LOAD MODE REGISTER ACTIVE READ WRITE PRECHARGE AUTO PRECHARGE BURST TERMINATE AUTO REFRESH SELF REFRESH Operation Bank/Row Activation READs WRITEs PRECHARGE POWERDOWN CLOCK SUSPEND BURST READ/SINGLE WRITE CONCURRENT AUTO PRECHARGE Absolute Maximum Ratings Notes mbTOC.fm Rev. G 2/04 EN Micron Technology, Inc. All rights reserved.

4 List of Figures 52Mb: x4, x8, x6 Figure : Pin Assignment Top View 54Pin TSOP Figure 2: Functional Block Diagram 28 Meg x Figure 3: Functional Block Diagram 64 Meg x Figure 4: Functional Block Diagram 32 Meg x Figure 5: Mode Register Definition Figure 6: CAS Latency Figure 7: Activating a Specific Row In a Specific Bank Figure 8: Example Meeting RCD MIN When 2 < RCD MIN/CK Figure 9: Read Command Figure 0: CAS Latency Figure : Consecutive READ Bursts Figure 2: Random READ Accesses Figure 3: READ to WRITE Figure 4: READ to WRITE with Extra Clock Cycle Figure 5: Terminating a READ Burst Figure 6: WRITE Command Figure 7: WRITE Burst Figure 8: WRITE to WRITE Figure 9: Random WRITE Cycles Figure 20: WRITE To READ Figure 2: WRITE To PRECHARGE Figure 22: Terminating a WRITE Burst Figure 23: PRECHARGE Command Figure 24: PowerDown Figure 25: Clock Suspend During WRITE Burst Figure 26: Clock Suspend During READ Burst Figure 27: READ With Auto Precharge Interrupted by a READ Figure 28: READ With Auto Precharge Interrupted by a WRITE Figure 29: WRITE With Auto Precharge Interrupted by a READ Figure 30: WRITE With Auto Precharge Interrupted by a WRITE Figure 3: Initialize And Load Mode Register Figure 32: PowerDown Mode Figure 33: Clock Suspend Mode Figure 34: Auto Refresh Mode Figure 35: Self Refresh Mode Figure 36: READ Without Auto Precharge Figure 37: READ With Auto Precharge Figure 38: Single READ Without Auto Precharge Figure 39: Single READ With Auto Precharge Figure 40: Alternating Bank Read Accesses Figure 4: Read Fullpage Burst Figure 42: Read M Operation Figure 43: Write Without Auto Precharge Figure 44: Write With Auto Precharge Figure 45: Single Write Without Auto Precharge Figure 46: Single Write with Auto Precharge Figure 47: Alternating Bank Write Accesses Figure 48: Write Fullpage Burst Figure 49: Write M Operation Figure 50: 54Pin Plastic TSOP 400 mil mbLOF.fm Rev. G 2/04 EN Micron Technology, Inc. All rights reserved.

5 List of Tables 52Mb: x4, x8, x6 Table : Pin Descriptions Table 2: Burst Definition Table 3: CAS Latency Table 4: Truth Table Commands And M Operation Table 5: Truth Table 2 CKE Table 6: Truth Table 3 Current State Bank n Command To Bank n Table 7: Truth Table 4 Current State Bank n Command To Bank m Table 8: DC Electrical Characteristics And Operating Conditions Table 9: IDD Specifications And Conditions Table 0: Capacitance Table : Electrical Characteristics And Recommended AC Operating Conditions Table 2: AC Functional Characteristics mbLOT.fm Rev. G 2/04 EN Micron Technology, Inc. All rights reserved.

6 Figure 2: Functional Block Diagram 28 Meg x 4 52Mb: x4, x8, x6 CKE CS# WE# CAS# RAS# DECODE CONTROL LOGIC 3 2 MODE REGISTER 2 REFRESH COUNTER 3 3 MUX 3 0 LATCH & DECODER MEMORY ARRAY 8,92 x 4,096 x 4 M SENSE AMPLIFIERS DATA OUTPUT REGISTER A0A2, BA0, BA 5 REGISTER 2 2 CONTROL LOGIC I/O GATING M MASK LOGIC READ DATA LATCH WRITE DRIVERS 4096 x4 4 DATA INPUT REGISTER COLUMN DECODER 2 COLUMN COUNTER/ LATCH 2 52mb.fm Rev. G 2/04 EN Micron Technology, Inc. All rights reserved.

7 Figure 3: Functional Block Diagram 64 Meg x 8 52Mb: x4, x8, x6 CKE CS# WE# CAS# RAS# DECODE CONTROL LOGIC 3 2 MODE REGISTER 2 REFRESH COUNTER 3 3 MUX 3 0 LATCH & DECODER MEMORY ARRAY 8,92 x 2,048 x 8 M SENSE AMPLIFIERS DATA OUTPUT REGISTER A0A2, BA0, BA 5 REGISTER 2 2 CONTROL LOGIC I/O GATING M MASK LOGIC READ DATA LATCH WRITE DRIVERS 2048 x8 8 DATA INPUT REGISTER COLUMN DECODER COLUMN COUNTER/ LATCH 52mb.fm Rev. G 2/04 EN Micron Technology, Inc. All rights reserved.

8 Figure 4: Functional Block Diagram 32 Meg x 6 52Mb: x4, x8, x6 CKE CS# WE# CAS# RAS# DECODE CONTROL LOGIC 3 2 MODE REGISTER 2 REFRESH COUNTER 3 3 MUX 3 0 LATCH & DECODER MEMORY ARRAY 8,92 x,024 x ML, MH SENSE AMPLIFIERS DATA OUTPUT REGISTER A0A2, BA0, BA 5 REGISTER 2 2 CONTROL LOGIC I/O GATING M MASK LOGIC READ DATA LATCH WRITE DRIVERS 024 x6 6 DATA INPUT REGISTER COLUMN DECODER 0 COLUMN COUNTER/ LATCH 0 52mb.fm Rev. G 2/04 EN Micron Technology, Inc. All rights reserved.

9 Table : Pin Descriptions PIN NUMBERS SYMBOL TYPE DESCRIPTION 38 Input Clock: is driven by the system clock. All input signals are sampled on the positive edge of. also increments the internal burst counter and controls the output registers. 37 CKE Input Clock Enable: CKE activates HIGH and deactivates LOW the signal. Deactivating the clock provides PRECHARGE POWERDOWN and SELF REFRESH operation all banks idle, ACTIVE POWERDOWN row active in any bank or CLOCK SUSPEND operation burst/access in progress. CKE is synchronous except after the device enters powerdown and self refresh modes, where CKE becomes asynchronous until after exiting the same mode. The input buffers, including, are disabled during powerdown and self refresh modes, providing low standby power. CKE may be tied HIGH. 9 CS# Input Chip Select: CS# enables registered LOW and disables registered HIGH the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is considered part of the command code. 8, 7, 6 RAS#, CAS#, WE# 39 x4, x8: M 5, 39 x6: ML, MH Input Input Command Inputs: RAS#, CAS#, and WE# along with CS# define the command being entered. Input/Output Mask: M is an input mask signal for write accesses and an output enable signal for read accesses. Input data is masked when M is sampled HIGH during a WRITE cycle. The output buffers are placed in a HighZ state twoclock latency when M is sampled HIGH during a READ cycle. On the x4 and x8, ML Pin 5 is a NC and MH is M. On the x6, ML corresponds to 07 and MH corresponds to 85. ML and MH are considered same state when referenced as M. 20, 2 BA0, BA Input Bank Address Inputs: BA0 and BA define to which bank the ACTIVE, READ, WRITE, or PRECHARGE command is being applied. 2326, 29 34, 22, 35, 36 2, 4, 5, 7, 8, 0,, 3, 42, 44, 45, 47, 48, 50, 5, 53 2, 5, 8,, 44, 47, 50, 53 5,, 44, 50 A0A2 Input Address Inputs: A0A2 are sampled during the ACTIVE command rowaddress A0 A2 and READ/WRITE command columnaddress A0A9, A, A2 [x4]; A0A9, A [x8]; A0A9 [x6]; with A0 defining auto precharge to select one location out of the memory array in the respective bank. A0 is sampled during a PRECHARGE command to determine if all banks are to be precharged A0 [HIGH] or bank selected by A0 [LOW]. The address inputs also provide the opcode during a LOAD MODE REGISTER command. 05 x6: I/O Data Input/Output: Data bus for x6 4, 7, 0, 3, 5, 42, 45, 48, and 5 are NCs for x8; and 2, 4, 7, 8, 0, 3, 5, 42, 45, 47, 48, 5, and 53 are NCs for x4. 07 x8: I/O Data Input/Output: Data bus for x8 2, 8, 47, and 53 are NCs for x4. 03 x4: I/O Data Input/Output: Data bus for x4. 40 NC No Connect: This pin should be left unconnected. 3, 9, 43, 49 VD Supply Power: Isolated power to the die for improved noise immunity. 6, 2, 46, VSSQ Supply Ground: Isolated ground to the die for improved noise immunity. 52, 4, 27 VDD Supply Power Supply: +3.3V ±0.3V. 28, 4, 54 VSS Supply Ground. 52mb.fm Rev. G 2/04 EN Micron Technology, Inc. All rights reserved.

10 Functional Description In general, the 52Mb s 32 Meg x 4 x 4 banks, 6 Meg x 8 x 4 banks, and 8 Meg x 6 x 4 banks are quadbank DRAMs that operate at 3.3V and include a synchronous interface all signals are registered on the positive edge of the clock signal,. Each of the x4 s 34,27,728bit banks is organized as 8,92 rows by 4,096 columns by 4bits. Each of the x8 s 34,27,728bit banks is organized as 8,92 rows by 2,048 columns by 8bits. Each of the x6 s 34,27,728 bit banks is organized as 8,92 rows by,024 columns by 6bits. Read and write accesses to the are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed BA0 and BA select the bank, A0A2 select the row. The address bits x4: A0A9, A, A2; x8: A0A9, A; x6: A0A9 registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. Prior to normal operation, the must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation. Initialization s must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Once power is applied to VDD and VD simultaneously and the clock is stable stable clock is defined as a signal cycling within timing constraints specified for the clock pin, the requires a 00µs delay prior to issuing any command other than a COM MAND INHIBIT or. Starting at some point during this 00µs period and continuing at least through the end of this period, INHIBIT or commands should be applied. Once the 00µs delay has been satisfied with at least one INHIBIT or command having been applied, a PRECHARGE command should be applied. All banks must then be precharged, thereby placing the device in the all banks idle state. Once in the idle state, two AUTO REFRESH cycles must be performed. After the AUTO REFRESH cycles are complete, the is ready for Mode Register programming. Because the Mode Register will power up in an unknown state, it should be loaded prior to applying any operational command. Register Definition Mode Register The Mode Register is used to define the specific mode of operation of the. This definition includes the selection of a burst length, a burst type, a CAS latency, an operating mode and a write burst mode, as shown in Figure. The Mode Register is programmed via the LOAD MODE REGISTER command and will retain the stored information until it is programmed again or the device loses power. Mode Register bits M0M2 specify the burst length, M3 specifies the type of burst sequential or interleaved, M4M6 specify the CAS latency, M7 and M8 specify the operating mode, M9 specifies the write burst mode, and M0 and M are reserved for future use. Address A2 M2 is undefined but should be driven LOW during loading of the Mode Register. The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. Burst Length Read and write accesses to the are burst oriented, with the burst length being programmable, as shown in Figure. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of, 2, 4 or 8 locations are available for both the sequential and the interleaved burst types, and a fullpage burst is available for the sequential type. The fullpage burst is used in conjunction with the BURST TERMINATE command to generate arbitrary burst lengths. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by AA9, A, A2 x4; AA9, A x8; or A A9 x6 when the burst length is set to two; by A2A9, A, A2 x4; A2A9, A x8 or A2A9 x6 when the 52mb.fm Rev. G 2/04 EN Micron Technology, Inc. All rights reserved.

11 burst length is set to four; and by A3 A9, A, A2 x4; A3 A9, A x8 or A3 A9 x6 when the burst length is set to eight. The remaining least significant address bits is are used to select the starting location within the block. Fullpage bursts wrap within the page if the boundary is reached. Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 2. Figure 5: Mode Register Definition A2 A A0 A9 A8 A7 A6 A5 A4 A3 A2 A A Reserved* WB Op Mode CAS Latency BT Burst Length *Should program M2, M, M0 = 0, 0, 0 to ensure compatibility with future devices. M2 M M M3 = Reserved Reserved Reserved Full Page Address Bus Mode Register Mx Burst Length M3 = Reserved Reserved Reserved Reserved Table 2: BURST LENGTH STARTING COLUMN Burst Definition ORDER OF ACCESSES WITHIN A BURST TYPE = SEQUENTIAL TYPE = INTERLEAVED 2 A A A A2 A A Full Page y n = A0 A2//9 location 0y Cn, Cn +, Cn + 2 Cn + 3, Cn + 4 Cn, Cn Not Supported M9 0 M3 0 Burst Type Sequential Interleaved M6 M5 M4 CAS Latency Reserved Reserved 2 3 Reserved Reserved Reserved Reserved M8 0 M7 0 M6M0 Defined Operating Mode Standard Operation All other states reserved Write Burst Mode Programmed Burst Length Single Location Access. For fullpage accesses: y = 4,096 x4; y = 2,048 x8; y =,024 x6. 2. For a burst length of two, AA9, A, A2 x4; AA9, A x8; or AA9 x6 select the blockoftwo burst; A0 selects the starting column within the block. 3. For a burst length of four, A2A9, A, A2 x4; A2A9, A x8; or A2A9 x6 select the blockoffour burst; A0A select the starting column within the block. 4. For a burst length of eight, A3A9, A, A2 x4; A3A9, A x8; or A3A9 x6 select the blockofeight burst; A0A2 select the starting column within the block. 5. For a fullpage burst, the full row is selected and A0A9, A, A2 x4; A0A9, A x8; or A0A9 x6 select the starting column. 6. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 7. For a burst length of one, A0A9, A, A2 x4; A0A9, A x8; or A0A9 x6 select the unique column to be accessed, and Mode Register bit M3 is ignored. 52mb.fm Rev. G 2/04 EN 2004 Micron Technology, Inc. All rights reserved.

12 CAS Latency The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The s will start driving as a result of the clock edge one cycle earlier n + m, and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to two clocks, the s will start driving after T and the data will be valid by T2, as shown in Figure 2. Table 2 below indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result. Figure 6: CAS Latency T0 READ T tlz T2 t OH T3 Operating Mode The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. Write Burst Mode When M9 = 0, the burst length programmed via M0 M2 applies to both READ and WRITE bursts; when M9 =, the programmed burst length applies to READ bursts, but write accesses are singlelocation nonburst accesses. Table 3: SPEED CAS Latency ALLOWABLE OPERATING FREQUENCY MHZ CAS LATENCY = 2 CAS LATENCY = 3 7E CAS Latency = 2 T0 T T2 T3 T4 READ tlz t OH CAS Latency = 3 UNDEFINED 52mb.fm Rev. G 2/04 EN Micron Technology, Inc. All rights reserved.

13 Commands Table 4: Truth Table provides a quick reference of available commands. This is followed by a written description of each command. Three additional Truth Tables appear following the Operation section; these tables provide current state/next state information. Table 4: Truth Table Commands And M Operation NAME FUNCTION CS# RAS# CAS# WE# M ADDR S NOTES INHIBIT H X X X X X X NO OPERATION L H H H X X X ACTIVE Select bank and activate row L L H H X Bank/Row X 3 READ Select bank and column, and start READ burst L H L H L/H 8 Bank/Col X 4 WRITE Select bank and column, and start WRITE L H L L L/H 8 Bank/Col Valid 4 burst BURST TERMINATE L H H L X X Active PRECHARGE Deactivate row in bank or banks L L H L X Code X 5 AUTO REFRESH or SELF REFRESH L L L H X X X 6, 7 Enter self refresh mode LOAD MODE REGISTER L L L L X OpCode X 4 Write Enable/Output Enable L Active 8 Write Inhibit/Output HighZ H HighZ 8. CKE is HIGH for all commands shown except SELF REFRESH. 2. A0 A define the opcode written to the Mode Register, and A2 should be driven LOW. 3. A0 A2 provide row address, and BA0, BA determine which bank is made active. 4. A0 A9, A, A2 x4; A0 A9, A x8; or A0 A9 x6 provide column address; A0 HIGH enables the auto precharge feature nonpersistent, while A0 LOW disables the auto precharge feature; BA0, BA determine which bank is being read from or written to. 5. A0 LOW: BA0, BA determine the bank being precharged. A0 HIGH: All banks precharged and BA0, BA are Don t Care. 6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW. 7. Internal refresh counter controls row addressing; all inputs and I/Os are Don t Care except for CKE. 8. Activates or deactivates the s during WRITEs zeroclock delay and READs twoclock delay. 52mb.fm Rev. G 2/04 EN Micron Technology, Inc. All rights reserved.

14 INHIBIT The INHIBIT function prevents new commands from being executed by the, regardless of whether the signal is enabled. The is effectively deselected. Operations already in progress are not affected. NO OPERATION The NO OPERATION command is used to perform a to an which is selected CS# is LOW. This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. LOAD MODE REGISTER The Mode Register is loaded via inputs A0 A A2 should be driven LOW. See Mode Register heading in the Register Definition section. The LOAD MODE REGISTER command can only be issued when all banks are idle, and a subsequent executable command cannot be issued until t MRD is met. ACTIVE The ACTIVE command is used to open or activate a row in a particular bank for a subsequent access. The value on the BA0, BA inputs selects the bank, and the address provided on inputs A0 A2 selects the row. This row remains active or open for accesses until a PRECHARGE command is issued to that bank. A PRE CHARGE command must be issued before opening a different row in the same bank. READ The READ command is used to initiate a burst read access to an active row. The value on the BA0, BA inputs selects the bank, and the address provided on inputs A0 A9, A, A2 x4; A0 A9, A x8; or A0 A9 x6 selects the starting column location. The value on input A0 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the READ burst; if auto precharge is not selected, the row will remain open for subsequent accesses. Read data appears on the s subject to the logic level on the M inputs two clocks earlier. If a given M signal was registered HIGH, the corresponding s will be HighZ two clocks later; if the M signal was registered LOW, the s will provide valid data. WRITE The WRITE command is used to initiate a burst write access to an active row. The value on the BA0, BA inputs selects the bank, and the address provided on inputs A0 A9, A, A2 x4; A0 A9, A x8; or A0 A9 x6 selects the starting column location. The value on input A0 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the WRITE burst; if auto precharge is not selected, the row will remain open for subsequent accesses. Input data appearing on the s is written to the memory array subject to the M input logic level appearing coincident with the data. If a given M signal is registered LOW, the corresponding data will be written to memory; if the M signal is registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that byte/column location. PRECHARGE The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The banks will be available for a subsequent row access a specified time t RP after the PRECHARGE command is issued. Input A0 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA select the bank. Otherwise BA0, BA are treated as Don t Care. Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. AUTO PRECHARGE Auto precharge is a feature which performs the same individualbank PRECHARGE function described above, without requiring an explicit command. This is accomplished by using A0 to enable auto precharge in conjunction with a specific READ or WRITE command. A PRECHARGE of the bank/row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ or WRITE burst, except in the fullpage burst mode, where auto precharge does not apply. Auto precharge is nonpersistent in that it is either enabled or disabled for each individual READ or WRITE command. Auto precharge ensures that the precharge is initiated at the earliest valid stage within a burst. The user must not issue another command to the same bank until the precharge time t RP is completed. This is determined as if an explicit PRECHARGE command 52mb.fm Rev. G 2/04 EN Micron Technology, Inc. All rights reserved.

15 was issued at the earliest possible time, as described for each burst type in the Operation section of this data sheet. BURST TERMINATE The BURST TERMINATE command is used to truncate either fixedlength or fullpage bursts. The most recently registered READ or WRITE command prior to the BURST TERMINATE command will be truncated, as shown in the Operation section of this data sheet. AUTO REFRESH AUTO REFRESH is used during normal operation of the and is analogous to CAS#BEFORERAS# CBR REFRESH in conventional DRAMs. This command is nonpersistent, so it must be issued each time a refresh is required. All active banks must be PRE CHARGED prior to issuing a AUTO REFRESH comand. The AUTO REFRESH command should not be issued until the minimum t RP has been met after the PRE CHARGE command as shown in the operations section. The addressing is generated by the internal refresh controller. This makes the address bits Don t Care during an AUTO REFRESH command. The 52Mb requires 8,92 AUTO REFRESH cycles every 64ms t REF, regardless of width option. Providing a distributed AUTO REFRESH command every 7.8µs will meet the refresh requirement and ensure that each row is refreshed. Alternatively, 8,92 AUTO REFRESH commands can be issued in a burst at the minimum cycle rate t RC, once every 64ms. SELF REFRESH The SELF REFRESH command can be used to retain data in the, even if the rest of the system is powered down. When in the self refresh mode, the retains data without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is disabled LOW. Once the SELF REFRESH command is registered, all the inputs to the become Don t Care with the exception of CKE, which must remain LOW. Once self refresh mode is engaged, the provides its own internal clocking, causing it to perform its own AUTO REFRESH cycles. The must remain in self refresh mode for a minimum period equal to t RAS and may remain in self refresh mode for an indefinite period beyond that. The procedure for exiting self refresh requires a sequence of commands. First, must be stable stable clock is defined as a signal cycling within timing constraints specified for the clock pin prior to CKE going back HIGH. Once CKE is HIGH, the must have commands issued a minimum of two clocks for t XSR because time is required for the completion of any internal refresh in progress. Upon exiting the self refresh mode, AUTO REFRESH commands must be issued every 7.8µs or less as both SELF REFRESH and AUTO REFRESH utilize the row refresh counter. Operation Bank/Row Activation Before any READ or WRITE commands can be issued to a bank within the, a row in that bank must be opened. This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated see Figure 3. After opening a row issuing an ACTIVE command, a READ or WRITE command may be issued to that row, subject to the t RCD specification. t RCD MIN should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVE command on which a READ or WRITE command can be entered. For example, a t RCD specification of 20ns with a 25 MHz clock 8ns period results in 2.5 clocks, rounded to 3. This is reflected in Figure 4, which covers any case where 2 < t RCD MIN/ t CK 3. The same procedure is used to convert other specification limits from time units to clock cycles. A subsequentive command to a different row in the same bank can only be issued after the previous active row has been closed precharged. The minimum time interval between successive ACTIVE commands to the same bank is defined by t RC. 52mb.fm Rev. G 2/04 EN Micron Technology, Inc. All rights reserved.

16 Figure 7: Activating a Specific Row In a Specific Bank CKE CS# RAS# HIGH A subsequentive command to another bank can be issued while the first bank is being accessed, which results in a reduction of total rowaccess overhead. The minimum time interval between successive ACTIVE commands to different banks is defined by t RRD. Figure 8: Example Meeting RCD MIN When 2 < RCD MIN/CK 3 T0 T T2 T3 T4 CAS# ACTIVE READ or WRITE trcd WE# A0A2 BA0, BA 52mb.fm Rev. G 2/04 EN Micron Technology, Inc. All rights reserved.

17 READs READ bursts are initiated with a READ command, as shown in Figure 9. The starting column and bank addresses are provided with the READ command, and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic READ commands used in the following illustrations, auto precharge is disabled. During READ bursts, the valid dataout element from the starting column address will be available following the CAS latency after the READ command. Each subsequent dataout element will be valid by the next positive clock edge. Figure 0 shows general timing for each possible CAS latency setting. Figure 0: CAS Latency T0 T T2 T3 READ tlz t OH CAS Latency = 2 T0 T T2 T3 READ tlz t OH T4 Figure 9: Read Command CAS Latency = 3 CKE HIGH CS# UNDEFINED RAS# CAS# WE# A0A9, A, A2: x4 A0A9, A: x8 A0A9: x6 A2: x8 A, A2: x6 A0 BA0, COLUMN ENABLE AUTO PRECHARGE DISABLE AUTO PRECHARGE Upon completion of a burst, assuming no other commands have been initiated, the s will go High Z. A fullpage burst will continue until terminated. At the end of the page, it will wrap to the start address and continue. Data from any READ burst may be truncated with a subsequent READ command, and data from a fixedlength READ burst may be immediately followed by data from a READ command. In either case, a continuous flow of data can be maintained. The first data element from the new burst follows either the last element of a completed burst or the last desired data element of a longer burst that is being truncated. The new READ command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. This is shown in Figure for CAS latencies of two and three; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. The 52Mb uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch architecture. A READ command can be initiated on any clock cycle following a previous READ command. Fullspeed random read accesses can be performed to the same bank, as shown in Figure 2, or each subsequent READ may be performed to a different bank. 52mb.fm Rev. G 2/04 EN Micron Technology, Inc. All rights reserved.

18 T0 Figure : Consecutive READ Bursts T T2 T3 T4 T5 T6 READ READ, COL n, COL b X = cycle n n + n + 2 n + 3 b CAS Latency = 2 T0 T T2 T3 T4 T5 T6 T7 READ READ X = 2 cycles, COL n, COL b n n + n + 2 n + 3 b CAS Latency = 3 TRANSITIONING DATA Each READ command may be to any bank. M is LOW. 52mb.fm Rev. G 2/04 EN Micron Technology, Inc. All rights reserved.

19 Figure 2: Random READ Accesses T0 T T2 T3 T4 T5 READ READ READ READ, COL n, COL a, COL x, COL m n a x m CAS Latency = 2 T0 T T2 T3 T4 T5 T6 READ READ READ READ, COL n, COL a, COL x, COL m n a x m CAS Latency = 3 TRANSITIONING DATA Each READ command may be to any bank. M is LOW. Data from any READ burst may be truncated with a subsequent WRITE command, and data from a fixedlength READ burst may be immediately followed by data from a WRITE command subject to bus turnaround limitations. The WRITE burst may be initiated on the clock edge immediately following the last or last desired data element from the READ burst, provided that I/O contention can be avoided. In a given system design, there may be a possibility that the device driving the input data will go LowZ before the s go HighZ. In this case, at least a singlecycle delay should occur between the last read data and the WRITE command. The M input is used to avoid I/O contention, as shown in Figure 3 and Figure 4 on page 20. The M signal must be asserted HIGH at least two clocks prior to the WRITE command M latency is two clocks for output buffers to suppress dataout from the READ. Once the WRITE command is registered, the s will go HighZ or remain HighZ, regardless of the state of the M signal; provided the M was active on the clock just prior to the WRITE command that truncated the READ command. If not, the second WRITE will be an invalid WRITE. For example, if M was LOW during T4 in Figure 4 on page 20, then the WRITEs at T5 and T7 would be valid, while the WRITE at T6 would be invalid. The M signal must be deasserted prior to the WRITE command M latency is zero clocks for input buffers to ensure that the written data is not masked. Figure 3 shows the case where the clock frequency allows for bus contention to be avoided without adding a cycle, and Figure 4 shows the case where the additional is needed. 52mb.fm Rev. G 2/04 EN Micron Technology, Inc. All rights reserved.

20 Figure 3: READ to WRITE T0 T T2 T3 T4 M Figure 4: READ to WRITE with Extra Clock Cycle M T0 T T2 T3 T4 T5 READ WRITE READ WRITE, COL n t HZ t CK n, COL b b tds, COL n t HZ n TRANSITIONING DATA, COL b b tds TRANSITIONING DATA A CAS latency of three is used for illustration. The READ command may be to any bank, and the WRITE command may be to any bank. A CAS latency of three is used for illustration. The READ command may be to any bank, and the WRITE command may be to any bank. If a burst of one is used, then M is not required. A fixedlength READ burst may be followed by, or truncated with, a PRECHARGE command to the same bank provided that auto precharge was not activated, and a fullpage burst may be truncated with a PRE CHARGE command to the same bank. The PRE CHARGE command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. This is shown in Figure for each possible CAS latency; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. Following the PRE CHARGE command, a subsequent command to the same bank cannot be issued until t RP is met. Note that part of the row precharge time is hidden during the access of the last data elements. In the case of a fixedlength burst being executed to completion, a PRECHARGE command issued at the optimum time as described above provides the same operation that would result from the same fixedlength burst with auto precharge. The disadvantage of the PRECHARGE command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the PRECHARGE command is that it can be used to truncate fixedlength or fullpage bursts. Fullpage READ bursts can be truncated with the BURST TERMINATE command, and fixedlength READ bursts may be truncated with a BURST TERMI NATE command, provided that auto precharge was not activated. The BURST TERMINATE command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. This is shown in Figure 2 for each possible CAS latency; data element n + 3 is the last desired data element of a longer burst. 52mb.fm Rev. G 2/04 EN Micron Technology, Inc. All rights reserved.

21 Figure 5: Terminating a READ Burst 52Mb: x4, x8, x6 T0 T T2 T3 T4 T5 T6 READ BURST TERMINATE, COL n X = cycle n n + n + 2 n + 3 CAS Latency = 2 T0 T T2 T3 T4 T5 T6 T7 READ BURST TERMINATE, COL n X = 2 cycles n n + n + 2 n + 3 CAS Latency = 3 TRANSITIONING DATA M is LOW. 52mb.fm Rev. G 2/04 EN Micron Technology, Inc. All rights reserved.

22 WRITEs WRITE bursts are initiated with a WRITE command, as shown in Figure 3. The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic WRITE commands used in the following illustrations, auto precharge is disabled. During WRITE bursts, the first valid datain element will be registered coincident with the WRITE command. Subsequent data elements will be registered on each successive positive clock edge. Upon completion of a fixedlength burst, assuming no other commands have been initiated, the s will remain HighZ and any additional input data will be ignored see Figure 4 Write Burst. A fullpage burst will continue until terminated. At the end of the page, it will wrap to the start address and continue. Data for any WRITE burst may be truncated with a subsequent WRITE command, and data for a fixedlength WRITE burst may be immediately followed by data for a WRITE command. The new WRITE command can be issued on any clock following the previous WRITE command, and the data provided coincident with the new command applies to the new command. An example is shown in Figure 5 Write to Write. Data n + is either the last of a burst of two or the last desired of a longer burst. The 52Mb uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch architecture. A WRITE command can be initiated on any clock cycle following a previous WRITE command. Fullspeed random write accesses within a page can be performed to the same bank, as shown in Figure 6, or each subsequent WRITE may be performed to a different bank. Figure 6: WRITE Command CKE HIGH Figure 7: WRITE Burst T0 T T2 T3 CS# WRITE RAS#, COL n CAS# WE# A0A9, A, A2: x4 A0A9, A: x8 A0A9: x6 A2: x8 A, A2: x6 A0 COLUMN ENABLE AUTO PRECHARGE DISABLE AUTO PRECHARGE n n + Burst length = 2. M is LOW. Figure 8: WRITE to WRITE TRANSITIONING DATA T0 T T2 BA0, BA, WRITE WRITE, COL n, COL b n n + b TRANSITIONING DATA M is LOW. Each WRITE command may be to any bank. 52mb.fm Rev. G 2/04 EN Micron Technology, Inc. All rights reserved.

23 Data for any WRITE burst may be truncated with a subsequent READ command, and data for a fixedlength WRITE burst may be immediately followed by a READ command. Once the READ command is registered, the data inputs will be ignored, and WRITEs will not be executed. An example is shown in Figure 20. Data n + is either the last of a burst of two or the last desired of a longer burst. Data for a fixedlength WRITE burst may be followed by, or truncated with, a PRECHARGE command to the same bank provided that auto precharge was not activated, and a fullpage WRITE burst may be truncated with a PRECHARGE command to the same bank. The PRECHARGE command should be issued t WR after the clock edge at which the last desired input data element is registered. The auto precharge mode requires a t WR of at least one clock plus time, regardless of frequency. In addition, when truncating a WRITE burst, the M signal must be used to mask input data for the clock edge prior to, and the clock edge coincident with, the PRECHARGE command. An example is shown in Figure 8. Data n + is either the last of a burst of two or the last desired of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until t RP is met. The precharge can be issued coincident with the first coincident clock edge T2 in Figure 2 on an A Version and with the second clock on an A2 Version Figure 2. In the case of a fixedlength burst being executed to completion, a PRE CHARGE command issued at the optimum time as described above provides the same operation that would result from the same fixedlength burst with auto precharge. The disadvantage of the PRECHARGE command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the PRECHARGE command is that it can be used to truncate fixedlength or fullpage bursts. Fixedlength or fullpage WRITE bursts can be truncated with the BURST TERMINATE command. When truncating a WRITE burst, the input data applied coincident with the BURST TERMINATE command will be ignored. The last data written provided that M is LOW at that time will be the input data applied one clock previous to the BURST TERMINATE command. This is shown in Figure 22, where data n is the last desired data element of a longer burst. Figure 9: Random WRITE Cycles T0 WRITE, COL n n T a Figure 20: WRITE To READ Figure 2: WRITE To PRECHARGE t t 5ns M t WR = t < 5ns M T2 x T3 WRITE WRITE WRITE, COL a, COL x TRANSITIONING DATA, COL m Each WRITE command may be to any bank. M is LOW. T0 WRITE, COL n n T n + T2 T3 m READ, COL b TRANSITIONING DATA T4 b T5 b + The WRITE command may be to any bank, and the READ command may be to any bank. M is LOW. CAS latency = 2 for illustration. T0 a, COL n T T2 T3 T4 WRITE PRECHARGE n a, COL n n + t WR a or all t RP T5 ACTIVE a, WRITE PRECHARGE n n + t WR a or all t RP T6 ACTIVE a, TRANSITIONING DATA M could remain LOW in this example if the WRITE burst is a fixed length of two. 52mb.fm Rev. G 2/04 EN Micron Technology, Inc. All rights reserved.