DOUBLE DATA RATE (DDR) SDRAM

Transcription

1 DOUBLE DATA RATE DDR SDRAM FEATURES VDD = +2.5V ±.2V, VD = +2.5V ±.2V Bidirectional data stroe transmitted/ received with data, i.e., source-synchronous data capture x6 has two one per yte Internal, pipelined doule-data-rate DDR architecture; two data accesses per clock cycle Differential clock inputs and Commands entered on each positive edge edge-aligned with data for READs; centeraligned with data for WRITEs DLL to align and transitions with Four internal anks for concurrent operation Data mask for masking write data x6 has two one per yte Programmale urst lengths: 2, 4, or 8 Auto Refresh and Self Refresh Modes Longer lead TSOP for improved reliaility OCPL 2.5V I/O SSTL_2 compatile Concurrent auto precharge option is supported OPTIONS MARKING Configuration 64 Meg x 4 6 Meg x 4 x 4 anks 64M4 32 Meg x 8 8 Meg x 8 x 4 anks 32M8 6 Meg x 6 4 Meg x 6 x 4 anks 6M6 x6 IOL / IOH Drive Plastic Package OCPL 66-pin TSOP TG 4 mil width,.65mm pin pitch Timing Cycle Time CL = 2 DDR266A -75Z CL = 2.5 DDR266B 2-75 CL = 2 DDR2 3-8 Self Refresh Standard none Low Power L NOTE:. Supports PC2 modules with timing 2. Supports PC2 modules with timing 3. Supports PC6 modules with timing KEY TIMING PARAMETERS MT46V64M4 6 Meg x 4 x 4 anks MT46V32M8 8 Meg x 8 x 4 anks MT46V6M6 4 Meg x 6 x 4 anks For the latest data sheet revisions, please refer to the Micron We site: x4 VDD VD VSSQ VD VSSQ VD VDD WE# CAS# RAS# CS# BA BA A/AP A A A2 A3 VDD PIN ASSIGNMENT TOP VIEW x8 VDD VD VSSQ 2 VD 3 VSSQ VD VDD DNU WE# CAS# RAS# CS# BA BA A/AP A A A2 A3 VDD x6 VDD VD 2 VssQ 3 4 VD 5 6 VssQ 7 VD L VDD DNU L WE# CAS# RAS# CS# BA BA A/AP A A A2 A3 VDD 66-Pin TSOP Meg x 4 32 Meg x 8 6 Meg x 6 Configuration 6 Meg x 4 x 4 anks 8 Meg x 8 x 4 anks 4 Meg x 6 x 4 anks Refresh Count 8K 8K 8K Row Addressing 8K A A2 8K A A2 8K A A2 Bank Addressing 4 BA, BA 4 BA, BA 4 BA, BA Column Addressing 2K A A9, A K A A9 52 A A8 SPEED CLO RATE DATA-OUT ACCESS - GRADE CL = 2** CL = 2.5** WINDOW* WINDOW SKEW -75Z 33 MHz 33 MHz 2.5ns ±.75ns +.5ns -75 MHz 33 MHz 2.5ns ±.75ns +.5ns -8 MHz 25 MHz 3.4ns ±.8ns +.6ns x6 VSS 5 VSSQ 4 3 VD 2 VSSQ 9 VD 8 VSSQ U DNU VREF VSS U E A2 A A9 A8 A7 A6 A5 A4 VSS x8 VSS 7 VSSQ 6 VD 5 VSSQ 4 VD VSSQ DNU VREF VSS E A2 A A9 A8 A7 A6 A5 A4 VSS x4 VSS VSSQ 3 VD VSSQ 2 VD VSSQ DNU VREF VSS E A2 A A9 A8 A7 A6 A5 A4 VSS *Minimum clock CL = 2-75Z and -8 and CL = **CL = CAS Read Latency 256Mx4x8x6DDR_C.p65 Rev.C; Pu. 4/ 2, Micron Technology, Inc. PRODUCTS AND SPECIFICATIONS SCUSSED HEREIN ARE FOR EVALUATION AND REFEREE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON S PRODUCTION DATA SHEET SPECIFICATIONS.

2 256M PART NUMBERS Note: xx= -75, -75Z, or -8 PART NUMBER CONFIGURATION I/O DRIVE LEVEL REFRESH OPTION MT46V64M4TG-xx 64 Meg x 4 Full Drive Standard MT46V64M4TG-xxL 64 Meg x 4 Full Drive Low Power MT46V32M8TG-xx 32 Meg x 8 Full Drive Standard MT46V32M8TG-xxL 32 Meg x 8 Full Drive Low Power MT46V6M6TG-xx 6 Meg x 6 Programmale Drive Standard MT46V6M6TG-xxL 6 Meg x 6 Programmale Drive Low Power GENERAL DESCRIPTION The 256M is a high-speed CMOS, dynamic random-access memory containing 268,435,456 its. It is internally configured as a quadank DRAM. The 256M uses a doule data rate architecture to achieve high-speed operation. The doule data rate architecture is essentially a 2nprefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 256M effectively consists of a single 2n-it wide, one-clockcycle data transfer at the internal DRAM core and two corresponding n-it wide, one-half-clock-cycle data transfers at the I/O pins. A idirectional data stroe is transmitted externally, along with data, for use in data capture at the receiver. is a stroe transmitted y the DDR SDRAM during READs and y the memory controller during WRITEs. is edge-aligned with data for READs and center-aligned with data for WRITEs. The x6 offering has two data stroes, one for the lower yte and one for the upper yte. The 256M operates from a differential clock and ; the crossing of going HIGH and going LOW will e referred to as the positive edge of. Commands address and control signals are registered at every positive edge of. Input data is registered on oth edges of, and output data is referenced to oth edges of, as well as to oth edges of. Read and write accesses to the are urst oriented; accesses start at a selected location and continue for a programmed numer of locations in a programmed sequence. Accesses egin with the registration of an ACTIVE command, which is then followed y a READ or WRITE command. The address its registered coincident with the ACTIVE command are used to select the ank and row to e accessed. The address its registered coincident with the READ or WRITE command are used to select the ank and the starting column location for the urst access. The provides for programmale READ or WRITE urst lengths of 2, 4, or 8 locations. An auto precharge function may e enaled to provide a selftimed row precharge that is initiated at the end of the urst access. As with standard SDR SDRAMs, the pipelined, multiank architecture of s allows for concurrent operation, therey providing high effective andwidth y hiding row precharge and activation time. An auto refresh mode is provided, along with a power-saving power-down mode. All inputs are compatile with the JEDEC Standard for SSTL_2. All full drive option outputs are SSTL_2, Class II compatile. NOTE:. The functionality and the timing specifications discussed in this data sheet are for the DLLenaled mode of operation. 2. Throughout the data sheet, the various figures and text refer to s as. The term is to e interpreted as any and all collectively, unless specifically stated otherwise. Additionally, the x6 is divided in to two ytes the lower yte and upper yte. For the lower yte through 7 refers to L and refers to L; and for the upper yte 8 through 5 refers to U and refers to U. 256Mx4x8x6DDR_C.p65 Rev. C; Pu. 4/ 2 2, Micron Technology, Inc.

3 TABLE OF CONTENTS Functional Block Diagram 64 Meg x Functional Block Diagram 32 Meg x Functional Block Diagram 6 Meg x Pin Descriptions... 7 Functional Description... 9 Initialization... 9 Register Definition... 9 Mode Register... 9 Burst Length... 9 Burst Type... Read Latency... Operating Mode... Extended Mode Register... 2 DLL Enale/Disale... 2 Commands... 3 Truth Tale Commands... 3 Truth Tale A Operation... 3 Deselect... 4 No Operation NOP... 4 Load Mode Register... 4 Active... 4 Read... 4 Write... 4 Precharge... 4 Auto Precharge... 4 Burst Terminate... 4 Auto Refresh... 5 Self Refresh... 5 Operation... 6 Bank/Row Activation... 6 Reads... 7 Read Burst... 8 Consecutive Read Bursts... 9 Nonconsecutive Read Bursts... 2 Random Read Accesses... 2 Terminating a Read Burst Read to Write Read to Precharge Writes Write Burst Consecutive Write to Write Nonconsecutive Write to Write Random Writes... 3 Write to Read Uninterrupting... 3 Write to Read Interrupting Write to Read Odd, Interrupting Write to Precharge Uninterrupting Write to Precharge Interrupting Write to Precharge Odd, Interrupting Precharge Power-Down Truth Tale 2 E Truth Tale 3 Current State, Same Bank Truth Tale 4 Current State, Different Bank... 4 Operating Conditions Asolute Maximum Ratings DC Electrical and Operating Conditions AC Input Operating Conditions Clock Input Operating Conditions Capacitance x4, x IDD Specifications and Conditions x4, x Capacitance x IDD Specifications and Conditions - x AC Electrical Characteristics Timing Tale Data Valid Window Derating Voltage and Timing Waveforms Nominal Output Drive Curves Reduced Output Drive Curves x6 only Output Timing t Q and t QH x4, x Output Timing t Q and t QH x Output Timing t AC and t Input Timing Input Voltage Initialize and Load Mode Registers... 6 Power-Down Mode... 6 Auto Refresh Mode Self Refresh Mode Reads Bank Read Without Auto Precharge Bank Read With Auto Precharge Writes Bank Write Without Auto Precharge Bank Write With Auto Precharge Write Operation pin TSOP dimensions Mx4x8x6DDR_C.p65 Rev. C; Pu. 4/ 3 2, Micron Technology, Inc.

4 FUTIONAL BLO AGRAM 64 Meg x 4 E CS# WE# CAS# RAS# COMMAND DECODE CONTROL LOGIC BANK3 BANK2 BANK MODE REGISTERS 3 REFRESH COUNTER 3 3 ROW- ADDRESS MUX 3 BANK ROW- ADDRESS 892 LATCH & DECODER BANK MEMORY ARRAY 8,92 x,24 x 8 4 DATA DLL SENSE AMPLIFIERS 8 READ LATCH 4 MUX 4 DRVRS A-A2, BA, BA 5 ADDRESS REGISTER 2 2 BANK CONTROL LOGIC COLUMN- ADDRESS COUNTER/ LATCH 892 I/O GATING MASK LOGIC 24 x8 COLUMN DECODER 8 8 COL MASK WRITE FIFO 2 & DRIVERS 8 clk clk out in DATA COL GENERATOR INPUT REGISTERS RCVRS - 3, 256Mx4x8x6DDR_C.p65 Rev. C; Pu. 4/ 4 2, Micron Technology, Inc.

5 FUTIONAL BLO AGRAM 32 Meg x 8 E CS# WE# CAS# RAS# COMMAND DECODE CONTROL LOGIC BANK3 BANK2 BANK MODE REGISTERS 3 REFRESH COUNTER 3 3 ROW- ADDRESS MUX 3 BANK ROW- ADDRESS 892 LATCH & DECODER BANK MEMORY ARRAY 892 x 52 x 6 8 DATA DLL SENSE AMPLIFIERS 6 READ LATCH 8 MUX 8 DRVRS A-A2, BA, BA 5 ADDRESS REGISTER 2 2 BANK CONTROL LOGIC COLUMN- ADDRESS COUNTER/ LATCH I/O GATING MASK LOGIC 52 x6 COLUMN DECODER 6 6 COL MASK WRITE FIFO 2 & DRIVERS 6 clk clk out in DATA COL GENERATOR INPUT REGISTERS RCVRS - 7, 256Mx4x8x6DDR_C.p65 Rev. C; Pu. 4/ 5 2, Micron Technology, Inc.

6 FUTIONAL BLO AGRAM 6 Meg x 6 E CS# WE# CAS# RAS# COMMAND DECODE CONTROL LOGIC REFRESH COUNTER BANK3 BANK BANK2 3 MODE REGISTERS 3 3 ROW- ADDRESS MUX 3 BANK ROW- ADDRESS LATCH & DECODER 892 BANK MEMORY ARRAY 8,92 x 256 x 32 6 DATA DLL SENSE AMPLIFIERS 32 READ LATCH 6 MUX 6 DRVRS A-A2, BA, BA 5 ADDRESS REGISTER BANK CONTROL LOGIC COLUMN- ADDRESS COUNTER/ LATCH I/O GATING MASK LOGIC 256 x32 COLUMN DECODER WRITE FIFO & DRIVERS clk out clk in COL MASK 4 DATA COL 32 GENERATOR INPUT REGISTERS RCVRS - 5, L, U L U 256Mx4x8x6DDR_C.p65 Rev. C; Pu. 4/ 6 2, Micron Technology, Inc.

7 PIN DESCRIPTIONS TSOP PIN NUMBERS SYMBOL TYPE DESCRIPTION 45, 46, Input Clock: and are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of and negative edge of. Output data s and is referenced to the crossings of and. 44 E Input Clock Enale: E HIGH activates and E LOW deactivates the internal clock, input uffers and output drivers. Taking E LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations all anks idle, or ACTIVE POWER-DOWN row ACTIVE in any ank. E is synchronous for POWER-DOWN entry and exit, and for SELF REFRESH entry. E is asynchronous for SELF REFRESH exit and for disaling the outputs. E must e maintained HIGH throughout read and write accesses. Input uffers excluding, and E are disaled during POWER-DOWN. Input uffers excluding E are disaled during SELF REFRESH. E is an SSTL_2 input ut will detect an LVCMOS LOW level after VDD is applied. 24 CS# Input Chip Select: CS# enales registered LOW and disales registered HIGH the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external ank selection on systems with multiple anks. CS# is considered part of the command code. 23, 22, 2 RAS#, CAS#, Input Command Inputs: RAS#, CAS#, and WE# along with CS# define the WE# command eing entered. 47 Input Input Data Mask: is an input mask signal for write data. Input 2, 47 L, U data is masked when is sampled HIGH along with that input data during a WRITE access. is sampled on oth edges of. Although pins are input-only, the loading is designed to match that of and pins. For the x6, L is for - 7 and U is for 8-5. Pin 2 is a on x4 and x8 26, 27 BA, BA Input Bank Address Inputs: BA and BA define to which ank an ACTIVE, READ, WRITE, or PRECHARGE command is eing applied , 35-4, A A2 Input Address Inputs: Provide the row address for ACTIVE commands, and 28, 4, 42 the column address and auto precharge it A for READ/WRITE commands, to select one location out of the memory array in the respective ank. A sampled during a PRECHARGE command determines whether the PRECHARGE applies to one ank A LOW, ank selected y BA, BA or all anks A HIGH. The address inputs also provide the op-code during a MODE REGISTER SET command. BA and BA define which mode register mode register or extended mode register is loaded during the LOAD MODE REGISTER command. 2, 4, 5, 7, 8,,, 3, 5 I/O Data Input/Output: Data us for x6 4, 7,, 3, 54, 57, 6, and 63 54, 56, 57, 59, 6, 62, are for x8, 2, 4, 7, 8,, 3, 54, 57, 59, 6, 63, and 65 are 63, 65 for the x4. 2, 5, 8,, 56, 59, 62, 65 7 I/O Data Input/Output: Data us for x8 2, 8, 59 and 65 are for x4. continued on next page 256Mx4x8x6DDR_C.p65 Rev. C; Pu. 4/ 7 2, Micron Technology, Inc.

8 PIN DESCRIPTIONS continued TSOP PIN NUMBERS SYMBOL TYPE DESCRIPTION 5,, 56, 62-3 I/O Data Input/Output: Data us for x4. 5 I/O Data Stroe: Output with read data, input with write data. is 6, 5 L, U edge-aligned with read data, centered in write data. It is used to capture data. For the x6, L is for -7 and U is for 8-5. Pin 6 is on x4 and x8. 3, 9, 5, 55, 6 VD Supply Power Supply: +2.5V ±.2V. Isolated on the die for improved noise immunity. 6, 2, 52, 58, 64 VSSQ Supply Ground. Isolated on the die for improved noise immunity., 8, 33 VDD Supply Power Supply: +2.5V ±.2V. 34, 48, 66 VSS Supply Ground. 49 VREF Supply SSTL_2 reference voltage. 4, 7, 9, 25, 43, 53 No Connect: These pins should e left unconnected. 5 DNU Do Not Use: Must float to minimize noise. RESERVED PINS TSOP PIN NUMBERS SYMBOL TYPE DESCRIPTION 7 A3 I Address input for G devices. NOTE:. pins not listed may also e reserved for other uses now or in the future. This tale simply defines specific pins deemed to e of importance. 256Mx4x8x6DDR_C.p65 Rev. C; Pu. 4/ 8 2, Micron Technology, Inc.

9 FUTIONAL DESCRIPTION The 256M is a high-speed CMOS, dynamic random-access memory containing 268,435,456 its. The 256M is internally configured as a quad-ank DRAM. The 256M uses a doule data rate architecture to achieve high-speed operation. The doule data rate architecture is essentially a 2nprefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 256M consists of a single 2n-it wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding n-it wide, one-half-clock-cycle data transfers at the I/O pins. Read and write accesses to the are urst oriented; accesses start at a selected location and continue for a programmed numer of locations in a programmed sequence. Accesses egin with the registration of an ACTIVE command, which is then followed y a READ or WRITE command. The address its registered coincident with the ACTIVE command are used to select the ank and row to e accessed BA, BA select the ank; A-A2 select the row. The address its registered coincident with the READ or WRITE command are used to select the starting column location for the urst access. Prior to normal operation, the must e initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation. Initialization s must e powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Power must first e applied to VDD and VD simultaneously, and then to VREF and to the system VTT. VTT must e applied after VD to avoid device latch-up, which may cause permanent damage to the device. VREF can e applied any time after VD ut is expected to e nominally coincident with VTT. Except for E, inputs are not recognized as valid until after VREF is applied. E is an SSTL_2 input ut will detect an LVCMOS LOW level after VDD is applied. Maintaining an LVCMOS LOW level on E during power-up is required to ensure that the and outputs will e in the High-Z state, where they will remain until driven in normal operation y a read access. After all power supply and reference voltages are stale, and the clock is stale, the requires a 2µs delay prior to applying an executale command. Once the 2µs delay has een satisfied, a DESE- LECT or NOP command should e applied, and E should e rought HIGH. Following the NOP command, a PRECHARGE ALL command should e applied. Next a LOAD MODE REGISTER command should e issued for the extended mode register BA LOW and BA HIGH to enale the DLL, followed y another LOAD MODE REGISTER command to the mode register BA/ BA oth LOW to reset the DLL and to program the operating parameters. Two-hundred clock cycles are required etween the DLL reset and any READ command. A PRECHARGE ALL command should then e applied, placing the device in the all anks idle state. Once in the idle state, two AUTO REFRESH cycles must e performed t RFC must e satisfied. Additionally, a LOAD MODE REGISTER command for the mode register with the reset DLL it deactivated i.e., to program operating parameters without resetting the DLL is required. Following these requirements, the DDR SDRAM is ready for normal operation. Register Definition MODE REGISTER The mode register is used to define the specific mode of operation of the. This definition includes the selection of a urst length, a urst type, a CAS latency and an operating mode, as shown in Figure. The mode register is programmed via the MODE REGISTER SET command with BA = and BA = and will retain the stored information until it is programmed again or the device loses power except for it A8, which is self-clearing. Reprogramming the mode register will not alter the contents of the memory, provided it is performed correctly. The mode register must e loaded reloaded when all anks are idle and no ursts are in progress, and the controller must wait the specified time efore initiating the susequent operation. Violating either of these requirements will result in unspecified operation. Mode register its A-A2 specify the urst length, A3 specifies the type of urst sequential or interleaved, A4-A6 specify the CAS latency, and A7-A2 specify the operating mode. Burst Length Read and write accesses to the are urst oriented, with the urst length eing programmale, as shown in Figure. The urst length determines the maximum numer of column locations that can e accessed for a given READ or WRITE command. 256Mx4x8x6DDR_C.p65 Rev. C; Pu. 4/ 9 2, Micron Technology, Inc.

10 Burst lengths of 2, 4, or 8 locations are availale for oth the sequential and the interleaved urst types. Reserved states should not e used, as unknown operation or incompatiility with future versions may result. When a READ or WRITE command is issued, a lock of columns equal to the urst length is effectively selected. All accesses for that urst take place within this lock, meaning that the urst will wrap within the lock if a oundary is reached. The lock is uniquely selected y A-Ai when the urst length is set to two, y A2-Ai when the urst length is set to four and y A3-Ai when the urst length is set to eight where Ai is the most significant column address it for a given configuration. The remaining least significant address its is are used to select the starting location within the lock. The programmed urst length applies to oth READ and WRITE ursts. Burst Type Accesses within a given urst may e programmed to e either sequential or interleaved; this is referred to as the urst type and is selected via it M3. The ordering of accesses within a urst is determined y the urst length, the urst type and the starting column address, as shown in Tale. BA BA A2 A A A9 A8 A7 A6 A5 A4 A3 A2 A A Address Bus Tale Burst Definition 4 * * Operating Mode CAS Latency BT Burst Length * M4 and M3 BA and BA must e, to select the ase mode register vs. the extended mode register. M6 M5 M4 M3 M2 M M M9 M8 M7 M6-M Valid Valid - M2 M M CAS Latency Reserved Reserved 2 Reserved Reserved Reserved 2.5 Reserved Figure Mode Register Definition Mode Register Mx Burst Length M3 = M3 = Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Burst Type Sequential Interleaved Operating Mode Normal Operation Normal Operation/Reset DLL All other states reserved Burst Starting Column Order of Accesses Within a Burst Length Address Type = Sequential Type = Interleaved A A A A2 A A NOTE:. For a urst length of two, A-Ai select the twodata-element lock; A selects the first access within the lock. 2. For a urst length of four, A2-Ai select the fourdata-element lock; A-A select the first access within the lock. 3. For a urst length of eight, A3-Ai select the eightdata-element lock; A-A2 select the first access within the lock. 4. Whenever a oundary of the lock is reached within a given sequence aove, the following access wraps within the lock. 256Mx4x8x6DDR_C.p65 Rev. C; Pu. 4/ 2, Micron Technology, Inc.

11 Read Latency The READ latency is the delay, in clock cycles, etween the registration of a READ command and the availaility of the first it of output data. The latency can e set to 2, or 2.5 clocks, as shown in Figure 2. If a READ command is registered at clock edge n, and the latency is m clocks, the data will e availale nominally coincident with clock edge n + m. Tale 2 indicates the operating frequencies at which each CAS latency setting can e used. Reserved states should not e used as unknown operation or incompatiility with future versions may result. Tale 2 CAS Latency CL ALLOWABLE OPERATING FREQUEY MHz SPEED CL = 2 CL = Z 75 f f f 75 f f 75 f 25 COMMAND COMMAND T T T2 T2n T3 T3n READ NOP NOP NOP CL = 2 T T T2 T2n T3 T3n READ NOP NOP NOP CL = 2.5 Operating Mode The normal operating mode is selected y issuing a MODE REGISTER SET command with its A7-A2 each set to zero, and its A-A6 set to the desired values. A DLL reset is initiated y issuing a MODE REGISTER SET command with its A7 and A9-A2 each set to zero, it A8 set to one, and its A-A6 set to the desired values. Although not required y the Micron device, JEDEC specifications recommend when a LOAD MODE REGISTER command is issued to reset the DLL, it should always e followed y a LOAD MODE REGIS- TER command to select normal operating mode. All other cominations of values for A7-A2 are reserved for future use and/or test modes. Test modes and reserved states should not e used ecause unknown operation or incompatiility with future versions may result. Burst Length = 4 in the cases shown Shown with nominal t AC and nominal t DS TRANSITIONING DATA DON T CARE Figure 2 CAS Latency 256Mx4x8x6DDR_C.p65 Rev. C; Pu. 4/ 2, Micron Technology, Inc.

12 EXTENDED MODE REGISTER The extended mode register controls functions eyond those controlled y the mode register; these additional functions are DLL enale/disale, output drive strength, and QFC#. These functions are controlled via the its shown in Figure 3. The extended mode register is programmed via the LOAD MODE REGISTER command to the mode register with BA = and BA = and will retain the stored information until it is programmed again or the device loses power. The enaling of the DLL should always e followed y a LOAD MODE REGISTER command to the mode register BA/BA oth LOW to reset the DLL. The extended mode register must e loaded when all anks are idle and no ursts are in progress, and the controller must wait the specified time efore initiating any susequent operation. Violating either of these requirements could result in unspecified operation. Output Drive Strength The normal drive strength for all outputs are specified to e SSTL2, Class II. The x6 supports a programmale option for reduced drive. This option is intended for the support of the lighter load and/or point-topoint environments. The selection of the reduced drive strength will alter the s and s from SSTL2, Class II drive strength to a reduced drive strength, which is approximately 54% of the SSTL2, Class II drive strength. DLL Enale/Disale The DLL must e enaled for normal operation. DLL enale is required during power-up initialization and upon returning to normal operation after having disaled the DLL for the purpose of deug or evaluation. When the device exits self refresh mode, the DLL is enaled automatically. Any time the DLL is enaled, 2 clock cycles must occur efore a READ command can e issued. BA BA A2 A A A9 A8 A7 A6 A5 A4 A3 A2 A A Operating Mode QFC# DS DLL E2 E E E9 E8 E7 E6 E5 E4 E3 E2, E, E Valid E2 3 E 2 Operating Mode Reserved Reserved Figure 3 Extended Mode Register Definition E Address Bus Extended Mode Register Ex DLL Enale Disale Drive Strength Normal Reduced QFC# Function Disaled Reserved NOTE:. E4 and E3 BA and BA must e, to select the Extended Mode Register vs. the ase Mode Register. 2. The reduced drive strength option is not supported on the x4 and x8 versions, and is only availale on the x6 version. 3. The QFC# option is not supported. 256Mx4x8x6DDR_C.p65 Rev. C; Pu. 4/ 2 2, Micron Technology, Inc.

13 COMMANDS Truth Tale provides a quick reference of availale commands. This is followed y a veral description of each command. Two additional Truth Tales appear following the Operation section; these tales provide current state/next state information. TRUTH TABLE COMMANDS Note: NAME FUTION CS# RAS# CAS# WE# ADDR NOTES DESELECT NOP H X X X X 9 NO OPERATION NOP L H H H X 9 ACTIVE Select ank and activate row L L H H Bank/Row 3 READ Select ank and column, and start READ urst L H L H Bank/Col 4 WRITE Select ank and column, and start WRITE urst L H L L Bank/Col 4 BURST TERMINATE L H H L X 8 PRECHARGE Deactivate row in ank or anks L L H L Code 5 AUTO REFRESH or SELF REFRESH L L L H X 6, 7 Enter self refresh mode LOAD MODE REGISTER L L L L Op-Code 2 TRUTH TABLE A OPERATION Note: NAME FUTION s NOTES Write Enale L Valid Write Inhiit H X NOTE:. E is HIGH for all commands shown except SELF REFRESH. 2. BA-BA select either the mode register or the extended mode register BA =, BA = select the mode register; BA =, BA = select extended mode register; other cominations of BA-BA are reserved. A-A2 provide the op-code to e written to the selected mode register. 3. BA-BA provide ank address and A-A2 provide row address. 4. BA-BA provide ank address; A-Ai provide column address where i = 8 for x6, 9 for x8, and 9, for x4; A HIGH enales the auto precharge feature nonpersistent, and A LOW disales the auto precharge feature. 5. A LOW: BA-BA determine which ank is precharged. A HIGH: all anks are precharged and BA-BA are Don t Care. 6. This command is AUTO REFRESH if E is HIGH, SELF REFRESH if E is LOW. 7. Internal refresh counter controls row addressing; all inputs and I/Os are Don t Care except for E. 8. Applies only to read ursts with auto precharge disaled; this command is undefined and should not e used for READ ursts with auto precharge enaled and for WRITE ursts. 9. DESELECT and NOP are functionally interchangeale.. Used to mask write data; provided coincident with the corresponding data. 256Mx4x8x6DDR_C.p65 Rev. C; Pu. 4/ 3 2, Micron Technology, Inc.

14 DESELECT The DESELECT function CS# HIGH prevents new commands from eing executed y the. The is effectively deselected. Operations already in progress are not affected. NO OPERATION NOP The NO OPERATION NOP command is used to instruct the selected to perform a NOP CS# LOW. This prevents unwanted commands from eing registered during idle or wait states. Operations already in progress are not affected. LOAD MODE REGISTER The mode registers are loaded via inputs A-A2. See mode register descriptions in the Register Definition section. The LOAD MODE REGISTER command can only e issued when all anks are idle, and a susequent executale command cannot e issued until t MRD is met. ACTIVE The ACTIVE command is used to open or activate a row in a particular ank for a susequent access. The value on the BA, BA inputs selects the ank, and the address provided on inputs A-A2 selects the row. This row remains active or open for accesses until a PRECHARGE command is issued to that ank. A PRECHARGE command must e issued efore opening a different row in the same ank. READ The READ command is used to initiate a urst read access to an active row. The value on the BA, BA inputs selects the ank, and the address provided on inputs A-Ai where i = 8 for x6, 9 for x8, or 9, for x4 selects the starting column location. The value on input A determines whether or not auto precharge is used. If auto precharge is selected, the row eing accessed will e precharged at the end of the READ urst; if auto precharge is not selected, the row will remain open for susequent accesses. WRITE The WRITE command is used to initiate a urst write access to an active row. The value on the BA, BA inputs selects the ank, and the address provided on inputs A-Ai where i = 8 for x6, 9 for x8, or 9, for x4 selects the starting column location. The value on input A determines whether or not auto precharge is used. If auto precharge is selected, the row eing accessed will e precharged at the end of the WRITE urst; if auto precharge is not selected, the row will remain open for susequent accesses. Input data appearing on the s is written to the memory array suject to the input logic level appearing coincident with the data. If a given signal is registered LOW, the corresponding data will e written to memory; if the signal is registered HIGH, the corresponding data inputs will e ignored, and a WRITE will not e executed to that yte/column location. PRECHARGE The PRECHARGE command is used to deactivate the open row in a particular ank or the open row in all anks. The anks will e availale for a susequent row access a specified time trp after the precharge command is issued. Except in the case of concurrent auto precharge, where a READ or WRITE command to a different ank is allowed as long as it does not interrupt the data transfer in the current ank and does not violate any other timing parameters. Input A determines whether one or all anks are to e precharged, and in the case where only one ank is to e precharged, inputs BA, BA select the ank. Otherwise BA, BA are treated as Don t Care. Once a ank has een precharged, it is in the idle state and must e activated prior to any READ or WRITE commands eing issued to that ank. A PRECHARGE command will e treated as a NOP if there is no open row in that ank idle state, or if the previously open row is already in the process of precharging. AUTO PRECHARGE Auto precharge is a feature which performs the same individual-ank precharge function descried aove, ut without requiring an explicit command. This is accomplished y using A to enale auto precharge in conjunction with a specific READ or WRITE command. A precharge of the ank/row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ or WRITE urst. Auto precharge is nonpersistent in that it is either enaled or disaled for each individual Read or Write command. This device supports concurrent auto precharge if the command to the other ank does not interrupt the data transfer to the current ank. Auto precharge ensures that the precharge is initiated at the earliest valid stage within a urst. This earliest valid stage is determined as if an explicit PRECHARGE command was issued at the earliest possile time, without violating t RAS MIN, as descried for each urst type in the Operation section of this data sheet. The user must not issue another command to the same ank until the precharge time t RP is completed. 256Mx4x8x6DDR_C.p65 Rev. C; Pu. 4/ 4 2, Micron Technology, Inc.

15 BURST TERMINATE The BURST TERMINATE command is used to truncate READ ursts with auto precharge disaled. The most recently registered READ command prior to the BURST TERMINATE command will e truncated, as shown in the Operation section of this data sheet. The open page which the READ urst was terminated from remains open. AUTO REFRESH AUTO REFRESH is used during normal operation of the and is analogous to CAS#-BEFORE- RAS# CBR REFRESH in FPM/EDO DRAMs. This command is nonpersistent, so it must e issued each time a refresh is required. The addressing is generated y the internal refresh controller. This makes the address its a Don t Care during an AUTO REFRESH command. The 256M DDR SDRAM requires AUTO REFRESH cycles at an average interval of 7.825µs maximum. To allow for improved efficiency in scheduling and switching etween tasks, some flexiility in the asolute refresh interval is provided. A maximum of eight AUTO REFRESH command can e posted to any given, meaning that the maximum asolute interval etween any AUTO REFRESH command and the next AUTO REFRESH command is µs 7.3µs. This maximum asolute interval is to allow future support for DLL updates internal to the DDR SDRAM to e restricted to AUTO REFRESH cycles, without allowing excessive drift in t AC etween updates. Although not a JEDEC requirement, to provide for future functionality features, E must e active High during the AUTO REFRESH period. The AUTO REFRESH period egins when the AUTO REFRESH command is registered and ends t RFC later. SELF REFRESH The SELF REFRESH command can e used to retain data in the, even if the rest of the system is powered down. When in the self refresh mode, the retains data without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command except E is disaled LOW. The DLL is automatically disaled upon entering SELF RE- FRESH and is automatically enaled upon exiting SELF REFRESH 2 clock cycles must then occur efore a READ command can e issued. Input signals except E are Don t Care during SELF REFRESH. The procedure for exiting self refresh requires a sequence of commands. First, must e stale prior to E going ack HIGH. Once E is HIGH, the DDR SDRAM must have NOP commands issued for t XSNR ecause time is required for the completion of any internal refresh in progress. A simple algorithm for meeting oth refresh and DLL requirements is to apply NOPs for 2 clock cycles efore applying any other command. 256Mx4x8x6DDR_C.p65 Rev. C; Pu. 4/ 5 2, Micron Technology, Inc.

16 Operations BANK/ROW ACTIVATION Before any READ or WRITE commands can e issued to a ank within the, a row in that ank must e opened. This is accomplished via the ACTIVE command, which selects oth the ank and the row to e activated, as shown in Figure 4. After a row is opened with an ACTIVE command, a READ or WRITE command may e issued to that row, suject to the t RCD specification. t RCD MIN should e divided y the clock period and rounded up to the next whole numer to determine the earliest clock edge after the ACTIVE command on which a READ or WRITE command can e entered. For example, a t RCD specification of 2ns with a 33 MHz clock 7.5ns period results in 2.7 clocks rounded to 3. This is reflected in Figure 5, which covers any case where 2 < t RCD MIN/ t 3. Figure 5 also shows the same case for t RCD; the same procedure is used to convert other specification limits from time units to clock cycles. A susequent ACTIVE command to a different row in the same ank can only e issued after the previous active row has een closed precharged. The minimum time interval etween successive ACTIVE commands to the same ank is defined y t RC. A susequent ACTIVE command to another ank can e issued while the first ank is eing accessed, which results in a reduction of total row-access overhead. The minimum time interval etween successive ACTIVE commands to different anks is defined y t RRD. E CS# RAS# CAS# WE# A-A2 BA, HIGH RA BA RA = Row Address BA = Bank Address Figure 4 Activating a Specific Row in a Specific Bank T T T2 T3 T4 T5 T6 T7 COMMAND ACT NOP NOP ACT NOP NOP RD/WR NOP A-A2 Row Row Col BA, BA Bank x Bank y Bank y trrd t RCD Figure 5 Example: Meeting t RCD t RRD MIN When 2 < t RCD t RRD MIN/ t 3 DON T CARE 256Mx4x8x6DDR_C.p65 Rev. C; Pu. 4/ 6 2, Micron Technology, Inc.

17 READs READ ursts are initiated with a READ command, as shown in Figure 6. The starting column and ank addresses are provided with the READ command and auto precharge is either enaled or disaled for that urst access. If auto precharge is enaled, the row eing accessed is precharged at the completion of the urst. For the generic READ commands used in the following illustrations, auto precharge is disaled. During READ ursts, the valid data-out element from the starting column address will e availale following the CAS latency after the READ command. Each susequent data-out element will e valid nominally at the next positive or negative clock edge i.e., at the next crossing of and. Figure 7 shows general timing for each possile CAS latency setting. is driven y the along with output data. The initial LOW state on is known as the read preamle; the LOW state coincident with the last dataout element is known as the read postamle. Upon completion of a urst, assuming no other commands have een initiated, the s will go High-Z. A detailed explanation of t Q valid dataout skew, t QH data-out window hold, the valid data window are depicted in Figure 27. A detailed explanation of t transition skew to and t AC data-out transition skew to is depicted in Figure 28. Data from any READ urst may e concatenated with or truncated with data from a susequent READ command. In either case, a continuous flow of data can e maintained. The first data element from the new urst follows either the last element of a completed urst or the last desired data element of a longer urst which is eing truncated. The new READ command should e issued x cycles after the first READ command, where x equals the numer of desired data element pairs pairs are required y the 2n-prefetch architecture. This is shown in Figure 8. A READ command can e initiated on any clock cycle following a previous READ command. Nonconsecutive read data is shown for illustration in Figure 9. Full-speed random read accesses within a page or pages can e performed as shown in Figure. E CS# RAS# CAS# WE# x4: A A9, A x8: A A9 x6: A A8 x4: A2 x8: A, A2 x6: A9, A, A2 A BA, HIGH CA EN AP S AP BA CA = Column Address BA = Bank Address EN AP = Enale Auto Precharge S AP = Disale Auto Precharge Figure 6 READ Command DON T CARE 256Mx4x8x6DDR_C.p65 Rev. C; Pu. 4/ 7 2, Micron Technology, Inc.

18 T T T2 T2n T3 T3n T4 T5 COMMAND READ NOP NOP NOP NOP NOP ADDRESS Bank a, Col n CL = 2 DO n COMMAND T T T2 T2n T3 T3n T4 T5 READ NOP NOP NOP NOP NOP ADDRESS Bank a, Col n CL = 2.5 DO n NOTE:. DO n = data-out from column n. 2. Burst length = 4. DON T CARE TRANSITIONING DATA 3. Three susequent elements of data-out appear in the programmed order following DO n. 4. Shown with nominal tac, t, and tq. Figure 7 READ Burst 256Mx4x8x6DDR_C.p65 Rev. C; Pu. 4/ 8 2, Micron Technology, Inc.

19 T T T2 T2n T3 T3n T4 T4n T5 T5n COMMAND READ NOP READ NOP NOP NOP ADDRESS Bank, Col n CL = 2 Bank, Col DO n DO T T T2 T2n T3 T3n T4 T4n T5 T5n COMMAND READ NOP READ NOP NOP NOP ADDRESS Bank, Col n CL = 2.5 Bank, Col DO n DO DON T CARE TRANSITIONING DATA NOTE:. DO n or = data-out from column n or column. 2. Burst length = 4 or 8 if 4, the ursts are concatenated; if 8, the second urst interrupts the first. 3. Three susequent elements of data-out appear in the programmed order following DO n. 4. Three or seven susequent elements of data-out appear in the programmed order following DO. 5. Shown with nominal t AC, t, and t Q. 6. Example applies only when READ commands are issued to same device. Figure 8 Consecutive READ Bursts 256Mx4x8x6DDR_C.p65 Rev. C; Pu. 4/ 9 2, Micron Technology, Inc.

20 T T T2 T2n T3 T3n T4 T5 T5n T6 COMMAND READ NOP NOP READ NOP NOP NOP ADDRESS Bank, Col n CL = 2 Bank, Col DO n DO COMMAND T T T2 T2n T3 T3n T4 T5 T5n T6 READ NOP NOP READ NOP NOP NOP ADDRESS Bank, Col n CL = 2.5 Bank, Col DO n DO DON T CARE TRANSITIONING DATA NOTE:. DO n or = data-out from column n or column. 2. Burst length = 4 or 8 if 4, the ursts are concatenated; if 8, the second urst interrupts the first. 3. Three susequent elements of data-out appear in the programmed order following DO n. 4. Three or seven susequent elements of data-out appear in the programmed order following DO. 5. Shown with nominal t AC, t, and t Q. 6. Example applies when READ commands are issued to different devices or nonconsecutive READs. Figure 9 Nonconsecutive READ Bursts 256Mx4x8x6DDR_C.p65 Rev. C; Pu. 4/ 2 2, Micron Technology, Inc.

21 T T T2 T2n T3 T3n T4 T4n T5 T5n COMMAND READ READ READ READ NOP NOP ADDRESS Bank, Col n Bank, Col x CL = 2 Bank, Col Bank, Col g DO n DO n' DO x DO x' DO DO ' DO g COMMAND T T T2 T2n T3 T3n T4 T4n T5 READ READ READ READ NOP NOP T5n ADDRESS Bank, Col n Bank, Col x CL = 2.5 Bank, Col Bank, Col g DO n DO n' DO x DO x' DO DO ' DON T CARE TRANSITIONING DATA NOTE:. DO n or x or or g = data-out from column n or column x or column or column g. 2. Burst length = 2 or 4 or 8 if 4 or 8, the following urst interrupts the previous. 3. n' or x' or ' or g' indicates the next data-out following DO n or DO x or DO or DO g, respectively. 4. READs are to an active row in any ank. 5. Shown with nominal t AC, t, and t Q. Figure Random READ Accesses 256Mx4x8x6DDR_C.p65 Rev. C; Pu. 4/ 2 2, Micron Technology, Inc.

22 READs continued Data from any READ urst may e truncated with a BURST TERMINATE command, as shown in Figure. The BURST TERMINATE latency is equal to the READ CAS latency, i.e., the BURST TERMINATE command should e issued x cycles after the READ command, where x equals the numer of desired data element pairs pairs are required y the 2n-prefetch architecture. Data from any READ urst must e completed or truncated efore a susequent WRITE command can e issued. If truncation is necessary, the BURST TER- MINATE command must e used, as shown in Figure 2. The t S MIN case is shown; the t S MAX case has a longer us idle time. t S [MIN] and t S [MAX] are defined in the section on WRITEs. A READ urst may e followed y, or truncated with, a PRECHARGE command to the same ank provided that auto precharge was not activated. The PRECHARGE command should e issued x cycles after the READ command, where x equals the numer of desired data element pairs pairs are required y the 2n-prefetch architecture. This is shown in Figure 3. Following the PRECHARGE command, a susequent command to the same ank cannot e issued until t RP is met. Note that part of the row precharge time is hidden during the access of the last data elements. 256Mx4x8x6DDR_C.p65 Rev. C; Pu. 4/ 22 2, Micron Technology, Inc.

23 T T T2 T2n T3 T4 T5 COMMAND READ BST 5 NOP NOP NOP NOP ADDRESS Bank a, Col n CL = 2 DO n COMMAND T T T2 T2n T3 T4 T5 READ BST 5 NOP NOP NOP NOP ADDRESS Bank a, Col n CL = 2.5 DO n NOTE:. DO n = data-out from column n. DON T CARE TRANSITIONING DATA 2. Burst length = Susequent element of data-out appears in the programmed order following DO n. 4. Shown with nominal tac, t, and tq. 5. BST = BURST TERMINATE command, page remains open. Figure Terminating a READ Burst 256Mx4x8x6DDR_C.p65 Rev. C; Pu. 4/ 23 2, Micron Technology, Inc.

24 T T T2 T2n T3 T4 T4n T5 T5n COMMAND READ BST 7 NOP WRITE NOP NOP ADDRESS Bank, Col n CL = 2 Bank, Col ts MIN DO n T T T2 T2n T3 T4 T5 T5n COMMAND READ BST 7 NOP NOP WRITE NOP ADDRESS Bank a, Col n CL = 2.5 ts MIN DO n NOTE:. DO n = data-out from column n. DON T CARE TRANSITIONING DATA 2. = data-in from column. 3. Burst length = 4 in the cases shown applies for ursts of 8 as well; if the urst length is 2, the BST command shown can e NOP. 4. One susequent element of data-out appears in the programmed order following DO n. 5. Data-in elements are applied following in the programmed order. 6. Shown with nominal t AC, t, and t Q. 7. BST = BURST TERMINATE command, page remains open. Figure 2 READ to WRITE 256Mx4x8x6DDR_C.p65 Rev. C; Pu. 4/ 24 2, Micron Technology, Inc.

25 T T T2 T2n T3 T3n T4 T5 COMMAND 6 READ NOP PRE NOP NOP ACT ADDRESS Bank a, Col n CL = 2 Bank a, a or all trp Bank a, Row DO n COMMAND 6 T T T2 T2n T3 T3n T4 T5 READ NOP PRE NOP NOP ACT ADDRESS Bank a, Col n CL = 2.5 Bank a, a or all trp Bank a, Row DO n DON T CARE TRANSITIONING DATA NOTE:. DO n = data-out from column n. 2. Burst length = 4, or an interrupted urst of Three susequent elements of data-out appear in the programmed order following DO n. 4. Shown with nominal tac, t, and tq. 5. READ to PRECHARGE equals two clocks, which allows two data pairs of data-out. 6. A READ command with AUTO-PRECHARGE enaled would cause a precharge to e performed at x numer of clock cycles after the READ command, where x = BL / PRE = PRECHARGE command; ACT = ACTIVE command. Figure 3 READ to PRECHARGE 256Mx4x8x6DDR_C.p65 Rev. C; Pu. 4/ 25 2, Micron Technology, Inc.

26 WRITEs WRITE ursts are initiated with a WRITE command, as shown in Figure 4. The starting column and ank addresses are provided with the WRITE command, and auto precharge is either enaled or disaled for that access. If auto precharge is enaled, the row eing accessed is precharged at the completion of the urst. For the generic WRITE commands used in the following illustrations, auto precharge is disaled. During WRITE ursts, the first valid data-in element will e registered on the first rising edge of following the WRITE command, and susequent data elements will e registered on successive edges of. The LOW state on etween the WRITE command and the first rising edge is known as the write preamle; the LOW state on following the last data-in element is known as the write postamle. The time etween the WRITE command and the first corresponding rising edge of t S is specified with a relatively wide range from 75 percent to 25 percent of one clock cycle. All of the WRITE diagrams show the nominal case, and where the two extreme cases i.e., t S [MIN] and t S [MAX] might not e intuitive, they have also een included. Figure 5 shows the nominal case and the extremes of t S for a urst of 4. Upon completion of a urst, assuming no other commands have een initiated, the s will remain High-Z and any additional input data will e ignored. Data for any WRITE urst may e concatenated with or truncated with a susequent WRITE command. In either case, a continuous flow of input data can e maintained. The new WRITE command can e issued on any positive edge of clock following the previous WRITE command. The first data element from the new urst is applied after either the last element of a completed urst or the last desired data element of a longer urst which is eing truncated. The new WRITE command should e issued x cycles after the first WRITE command, where x equals the numer of desired data element pairs pairs are required y the 2n-prefetch architecture. Figure 6 shows concatenated ursts of 4. An example of nonconsecutive WRITEs is shown in Figure 7. Full-speed random write accesses within a page or pages can e performed as shown in Figure 8. Data for any WRITE urst may e followed y a susequent READ command. To follow a WRITE without truncating the WRITE urst, t WTR should e met as shown in Figure 9. Data for any WRITE urst may e truncated y a susequent READ command, as shown in Figure 2. E CS# RAS# CAS# WE# x4: A A9, A x8: A A9 x6: A A8 x4: A2 x8: A, A2 x6: A9, A, A2 A BA, HIGH Figure 4 WRITE Command Note that only the data-in pairs that are registered prior to the t WTR period are written to the internal array, and any susequent data-in should e masked with as shown in Figure 2. Data for any WRITE urst may e followed y a susequent PRECHARGE command. To follow a WRITE without truncating the WRITE urst, t WR should e met as shown in Figure 22. Data for any WRITE urst may e truncated y a susequent PRECHARGE command, as shown in Figures 23 and 24. Note that only the data-in pairs that are registered prior to the t WR period are written to the internal array, and any susequent data-in should e masked with as shown in Figures 23 and 24. After the PRECHARGE command, a susequent command to the same ank cannot e issued until t RP is met. CA EN AP S AP BA CA = Column Address BA = Bank Address EN AP = Enale Auto Precharge S AP = Disale Auto Precharge DON T CARE 256Mx4x8x6DDR_C.p65 Rev. C; Pu. 4/ 26 2, Micron Technology, Inc.

27 T T T2 T2n T3 COMMAND WRITE NOP NOP NOP ADDRESS Bank a, Col t S NOM ts t S MIN ts ts MAX ts DON T CARE TRANSITIONING DATA NOTE:. = data-in for column. 2. Three susequent elements of data-in are applied in the programmed order following. 3. An uninterrupted urst of 4 is shown. 4. A is LOW with the WRITE command auto precharge is disaled. Figure 5 WRITE Burst 256Mx4x8x6DDR_C.p65 Rev. C; Pu. 4/ 27 2, Micron Technology, Inc.

28 T T Tn T2 T2n T3 T3n T4 T4n T5 COMMAND WRITE NOP WRITE NOP NOP NOP ADDRESS Bank, Col Bank, Col n t S NOM t S n DON T CARE TRANSITIONING DATA NOTE:., etc. = data-in for column, etc. 2. Three susequent elements of data-in are applied in the programmed order following. 3. Three susequent elements of data-in are applied in the programmed order following n. 4. An uninterrupted urst of 4 is shown. 5. Each WRITE command may e to any ank. Figure 6 Consecutive WRITE to WRITE 256Mx4x8x6DDR_C.p65 Rev. C; Pu. 4/ 28 2, Micron Technology, Inc.

29 T T Tn T2 T2n T3 T4 T4n T5 T5n COMMAND WRITE NOP NOP WRITE NOP NOP ADDRESS Bank, Col Bank, Col n t S NOM t S n DON T CARE TRANSITIONING DATA NOTE:., etc. = data-in for column, etc. 2. Three susequent elements of data-in are applied in the programmed order following. 3. Three susequent elements of data-in are applied in the programmed order following n. 4. An uninterrupted urst of 4 is shown. 5. Each WRITE command may e to any ank. FIGURE 7 Nonconsecutive WRITE to WRITE 256Mx4x8x6DDR_C.p65 Rev. C; Pu. 4/ 29 2, Micron Technology, Inc.