DQ18 DQ19 VDD DQ20 NC *VREF **CKE1 VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 VSS **CLK2 NC NC SDA SCL VDD

Size: px
Start display at page:

Download "DQ18 DQ19 VDD DQ20 NC *VREF **CKE1 VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 VSS **CLK2 NC NC SDA SCL VDD"

Transcription

1 PIN CONFIGURATIONS (Front side/back side) Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back DQ8 DQ CB0 CB1 WE **0 DU A0 A2 A4 A6 A8 A10/AP BA1 **CLK0 DU **2 2 3 DU CB2 CB *VREF **CKE **CLK2 SDA SCL CB4 CB5 CAS **1 RAS A1 A3 A5 A7 A9 BA0 A11 **CLK1 A12 **CKE0 **3 6 7 *A13 CB6 CB *VREF REGE **CLK3 SA0 SA1 SA2 Note : 1. * These pins are not used in this module. 2. Pins 82,83,165,166,167 should be in the system which does not support SPD. 3. Pins 21,22,52,53,105,106,136,137are used only ECC(x72) Module. 4. ** About these pins, Refer to the Block Diagram of each. Pin Description Pin Name Function Pin Name Function A0 ~ A12 Address input (Multiplexed) 0 ~ 7 BA0 ~ BA1 Select bank Power supply (3.3V) ~ 3 Data input/output Ground CB0 ~ CB7 Check bit (Data-in/data-out) VREF Power supply for reference CLK0 ~ 3 Clock input REGE Register enable CKE0, CKE1 Clock enable input SDA Serial data I/O 0 ~ 3 Chip select input SCL Serial clock RAS Row address strobe SA0 ~ 2 Address in EEPROM CAS Colume address strobe DU Don t use WE Write enable No connection RamTek TECH NOLOGY I. reserves the right to change products and specifications without notice.

2 PIN CONFIGURATION DESCRIPTION Pin Name Input Function CLK System clock Active on the positive going edge to sample all inputs. CKE A0 ~ A12 BA0 ~ BA1 RAS CAS WE 0 ~ 7 REGE Chip select Clock enable Address Bank select address Row address strobe Column address strobe Write enable Data input/output mask Register enable Disables or enables device operation by masking or enabling all inputs except CLK, CKE and Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled 1CLK+tss prior to valid command. Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA12 Column address : (x8 : CA0 ~ CA9), (x16 : CA0 ~ CA8) Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS, WE active. Makes data output Hi-Z, tshz after the clock and masks the output. Blocks data input when active. (Byte masking) The device operates in the transparent mode when REGE is low. When REGE is high, the device operates in the registered mode. In registered mode, the Address and control inputs are latched if CLK is held at a high or low logic level. the inputs are stored in the latch/flip-flop on the rising edge of CLK. REGE is tied to through 10K ohm Resistor on PCB. So if REGE of module is floating, this module will be operated as registered mode. ~ 63 Data input/output Data inputs/outputs are multiplexed on the same pins. CB0 ~ 7 Check bit Check bits for ECC. / Power supply/ground Power and ground for the input buffers and the core logic.

3 256MB,32Mx64 Non ECC Module(KBL47S262T0-AB)(Populated as 1 bank of x8 SDRAM Module) FUTIONAL BLOCK DIAGRAM 0 0 U U4 1 DQ8 DQ U U U U A0 ~ A12, BA0 & 1 RAS CAS WE CKE0 DQn 10Ω U3 Every DQpin of SDRAM CLK0/2 U7 SCL 47KΩ WP A0 Serial PD A1 A2 SA0 SA1 SA2 U0/U2 10Ω U4/U6 U1/U3 U5/U7 3.3 *1 SDA Vss One 0.1uF and one 0.22 uf Cap. per each SDRAM To all SDRAMs CLK2/3 10Ω 10

4 ABSOLUTE MAIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN, VOUT -1.0 ~ 4.6 V Voltage on supply relative to Vss, Q -1.0 ~ 4.6 V Storage temperature TSTG -55 ~ +1 C Power dissipation PD 1.0 * # of component W Short circuit current IOS ma Note : Permanent device damage may occur if "ABSOLUTE MAIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITIONS AND CHARACTERISTI Recommended operating conditions (Voltage referenced to = 0V, TA = 0 to 70 C) Parameter Symbol Min Typ Max Unit Note Supply voltage V Input high voltage VIH Q+0.3 V 1 Input low voltage VIL V 2 Output high voltage VOH V IOH = -2mA Output low voltage VOL V IOL = 2mA Input leakage current ILI ua 3 Notes : 1. VIH (max) = 5.6V AC.The overshoot voltage duration is 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is 3ns. 3. Any input 0V VIN Q. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. CAPACITAE ( = 3.3V, TA = 23 C, f = 1MHz, VREF = 1.4V ± 200 mv) Parameter Input capacitance (A0 ~ A11) Input capacitance (RAS, CAS, WE) Input capacitance (CKE) Input capacitance (CLK) Input capacitance () Input capacitance (0 ~ 7) Data input/output capacitance ( ~ 3) Symbol CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 COUT M366S1654ETS M366S3253ETS(U) M366S6453ETS(U) Min Max Min Max Min Max Unit Pin Input capacitance (A0 ~ A11) Input capacitance (RAS, CAS, WE) Input capacitance (CKE) Input capacitance (CLK) Input capacitance () Input capacitance (0 ~ 7) Data input/output capacitance ( ~ 3) Symbol CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 COUT M374S3253ETS(U) M374S6453ETS(U) Min Max Min Max Unit

5 AC OPERATING TEST CONDITIONS ( = 3.3V ± 0.3V, TA = 0 to 70 C) Parameter Value Unit AC input levels (Vih/Vil) 2.4/0.4 V Input timing measurement reference level 1.4 V Input rise and fall time tr/tf = 1/1 ns Output timing measurement reference level 1.4 V Output load condition See Fig V Vtt = 1.4V 1200Ω Ω Output VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA Output Z0 = Ω 870Ω (Fig. 1) DC output load circuit OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) (Fig. 2) AC output load circuit Parameter Symbol Version Unit Note 7A Row active to row active delay trrd(min) 15 ns 1 RAS to CAS delay trcd(min) 20 ns 1 Row precharge time trp(min) 20 ns 1 Row active time tras(min) 45 ns 1 tras(max) 100 us Row cycle time trc(min) 65 ns 1 Last data in to row precharge trdl(min) 2 CLK 2,5 Last data in to Active delay tdal(min) 2 CLK + trp - 5 Last data in to new col. address delay tcdl(min) 1 CLK 2 Last data in to burst stop tbdl(min) 1 CLK 2 Col. address to col. address delay tccd(min) 1 CLK 3 Number of valid output data CAS latency=3 2 ea 4 CAS latency=2 1 Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. 5. In 100MHz and below 100MHz operating conditions, trdl=1clk and tdal=1clk + 20ns is also supported. SAMSUNG recommends trdl=2clk and tdal=2clk + trp.

6 AC CHARACTERISTI (AC operating conditions unless otherwise noted) REFER TO THE INDIVIDUAL COMPONENET, NOT THE WHOLE MODULE. CLK cycle time CLK to valid output delay Output data hold time Parameter Symbol Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. Min CAS latency=3 tcc 7.5 CAS latency=2 10 7A Max CAS latency=3 tsac 5.4 CAS latency=2 6 CAS latency=3 toh 3 CAS latency=2 3 Unit Note 1000 ns 1 ns 1,2 ns 2 CLK high pulse width tch 2.5 ns 3 CLK low pulse width tcl 2.5 ns 3 Input setup time tss 1.5 ns 3 Input hold time tsh 0.8 ns 3 CLK to output in Low-Z tslz 1 ns 2 CLK to output in Hi-Z CAS latency=3 tshz 5.4 CAS latency=2 6 ns

7 SIMPLIFIED TRUTH TABLE (V=Valid, =Don t care, H=Logic high, L=Logic low) Command CKEn-1 CKEn RAS CAS WE BA0,1 A10/AP A0 ~ A9, A11, A12 Register Mode register set H L L L L OP code 1,2 Refresh Auto refresh Self refresh H 3 H L L L H Entry L 3 Exit L H Note L H H H 3 H 3 Bank active & row addr. H L L H H V Row address Read & Auto precharge disable L Column 4 column address H L H L H V address Auto precharge enable H 4,5 Write & column address Auto precharge disable L Column 4 H L H L L V address Auto precharge enable H 4,5 Burst stop H L H H L 6 Precharge Bank selection H L L H L V L All banks H Clock suspend or active power down Precharge power down mode Entry H L H L V V V Exit L H Entry H L Exit L H H L H H H H L V V V H V 7 H No operation command H L H H H Notes : 1. OP Code : Operand code A0 ~ A12 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 clock cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected. If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at trp after the end of burst. 6. Burst stop command is valid at every burst length. 7. sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read latency is 2)

8 PACKAGE DIMENSIONS :32Mx64 (KBL47S262T0-AB) Units : Inches (Millimeters) (9.5) (2.44) (.575) 0.1 (3.000) (3.) 0.1 (3.000) 5.2 (133.3) (127.3) (2.26) R (R /-0.0) R (R 2.000) ± (4.000 ± 0.100) (17.780).1DIA / (3.000DIA /-0.000) 0.3 (8.890) A B C.4 (11.430) 0.2 (6.3) 1.4 (36.830) 4.5 (115.57) 0.2 (6.3) 2.1 (54.61) ±0.008 (2.0 ±0.2) Max (2.54 Max) Min (4.19 Min) 0.0 ± (1.270 ± 0.10) 0.2 (6.3) 0.2 (6.3) ±0.008 (2.0 ±0.2) ± (1.000 ± 0.0) Detail A ± (2.000 ± 0.100) ± (3.125 ± 0.125) Detail B ± (2.000 ± 0.100) ± (3.125 ± 0.125) ±0.006 (0.200 ±0.1) 0.0 (1.270) Detail C Tolerances : ±.005(.13) unless otherwise specified The used device is Hynix 32Mx8 SDRAM, TSOPII SDRAM Part No. : HY 57V56820

Revision History. REV. 0.1 June Revision 0.0 (May, 1999) PC133 first published.

Revision History. REV. 0.1 June Revision 0.0 (May, 1999) PC133 first published. Revision History Revision 0.0 (May, 1999) PC133 first published. Revision 0.1 (June, 1999) - Changed PCB Dimensions in PACKAGE DIMENSIONS This datasheet has been downloaded from http://www.digchip.com

More information

M464S1724CT1 SDRAM SODIMM 16Mx64 SDRAM SODIMM based on 8Mx16,4Banks,4K Refresh,3.3V Synchronous DRAMs with SPD. Pin. Pin. Back. Front DQ53 DQ54 DQ55

M464S1724CT1 SDRAM SODIMM 16Mx64 SDRAM SODIMM based on 8Mx16,4Banks,4K Refresh,3.3V Synchronous DRAMs with SPD. Pin. Pin. Back. Front DQ53 DQ54 DQ55 M464S1724CT1 SDRAM SODIMM 16Mx64 SDRAM SODIMM based on 8Mx16,4Banks,4K Refresh,3.3V Synchronous DRAMs with SPD GENERAL DESCRIPTION The Samsung M464S1724CT1 is a 16M bit x 64 Synchronous Dynamic RAM high

More information

Shrink-TSOP. M464S3323CN0 SDRAM SODIMM 32Mx64 SDRAM SODIMM based on stsop2 16Mx8, 4Banks, 4K Refresh, 3.3V SDRAMs with SPD. Pin. Front. Pin.

Shrink-TSOP. M464S3323CN0 SDRAM SODIMM 32Mx64 SDRAM SODIMM based on stsop2 16Mx8, 4Banks, 4K Refresh, 3.3V SDRAMs with SPD. Pin. Front. Pin. M464S3323CN0 SDRAM SODIMM 32Mx64 SDRAM SODIMM based on stsop2 16Mx8, 4Banks, 4K Refresh, 3.3V SDRAMs with SPD GENERAL DESCRIPTION The Samsung M464S3323CN0 is a 32M bit x 64 Synchronous Dynamic RAM high

More information

Advantage Memory Corporation reserves the right to change products and specifications without notice

Advantage Memory Corporation reserves the right to change products and specifications without notice SDRAM DIMM 32MX72 SDRAM DIMM with PLL & Register based on 32MX4, 4 Internal Banks, 4K Refresh, 3.3V DRAMs with SPD GENERAL DESCRIPTION The Advantage is a 32MX72 Synchronous Dynamic RAM high density memory

More information

Advantage Memory Corporation reserves the right to change products and specifications without notice

Advantage Memory Corporation reserves the right to change products and specifications without notice SD872-8X8-72VS4 SDRAM DIMM 8MX72 SDRAM DIMM with ECC based on 8MX8, 4B, 4K Refresh, 3.3V DRAMs with SPD GENERAL DESCRIPTION The Advantage SD872-8X8-72VS4 is a 8MX72 Synchronous Dynamic RAM high-density

More information

SDRAM Unbuffered SODIMM. 144pin Unbuffered SODIMM based on 256Mb H-die. 54 TSOP-II/sTSOP II with Pb-Free. (RoHS compliant)

SDRAM Unbuffered SODIMM. 144pin Unbuffered SODIMM based on 256Mb H-die. 54 TSOP-II/sTSOP II with Pb-Free. (RoHS compliant) Unbuffered SODIMM 144pin Unbuffered SODIMM based on 256Mb H-die 54 TSOP-II/sTSOP II with Pb-Free (RoHS compliant) INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT

More information

Revision History Revision 1.0 (August, 2003) - First release. Revision 1.1 (February, 2004) -Corrected typo.

Revision History Revision 1.0 (August, 2003) - First release. Revision 1.1 (February, 2004) -Corrected typo. stacked 1Gb B-die SDRAM Specification Revision 1.1 February 2004 * Samsung Electronics reserves the right to change products or specification without notice. Revision History Revision 1.0 (August, 2003)

More information

Advantage Memory Corporation reserves the right to change products and specifications without notice

Advantage Memory Corporation reserves the right to change products and specifications without notice SDRAM SODIMM 4MX64 SDRAM SO DIMM based on 4MX16, 4Banks, 4K Refresh, 3.3V DRAMs with SPD GENERAL DESCRIPTION The Advantage is a 4MX64 Synchronous Dynamic RAM high density memory module. The Advantage consists

More information

256Mbit SDRAM. 8M x 8bit x 4 Banks Synchronous DRAM LVTTL. Revision 0.1 Sept. 2001

256Mbit SDRAM. 8M x 8bit x 4 Banks Synchronous DRAM LVTTL. Revision 0.1 Sept. 2001 256Mbit SDRAM 8M x 8bit x 4 Banks Synchronous DRAM LVTTL Revision 0.1 Sept. 2001 * Samsung Electronics reserves the right to change products or specification without notice. Revision History Revision 0.0

More information

M390S3320AT1 SDRAM DIMM 32Mx72 SDRAM DIMM with PLL & Register based on 32Mx4, 4Banks 4K Ref., 3.3V Synchronous DRAMs with SPD GENERAL DESCRIPTION The

M390S3320AT1 SDRAM DIMM 32Mx72 SDRAM DIMM with PLL & Register based on 32Mx4, 4Banks 4K Ref., 3.3V Synchronous DRAMs with SPD GENERAL DESCRIPTION The Revision History Revision 0.0 (Sep. 1999) PC133 first published M390S3320AT1 SDRAM DIMM 32Mx72 SDRAM DIMM with PLL & Register based on 32Mx4, 4Banks 4K Ref., 3.3V Synchronous DRAMs with SPD GENERAL DESCRIPTION

More information

TS1SSG S (TS16MSS64V6G)

TS1SSG S (TS16MSS64V6G) Description The TS1SSG10005-7S (TS16MSS64V6G) is a 16M bit x 64 Synchronous Dynamic RAM high-density memory module. The TS1SSG10005-7S (TS16MSS64V6G) consists of 4 piece of CMOS 16Mx16bits Synchronous

More information

128Mb Synchronous DRAM Specification

128Mb Synchronous DRAM Specification 128Mb Synchronous DRAM Specification A3V28S40JTP Zentel Electronics Corp. I Revision 1.0 General Description A3V28S40JTP is organized as 4-bank x 2,097,154-word x 16-bit Synchronous DRAM with LVTTL interface.

More information

128Mb Synchronous DRAM Specification

128Mb Synchronous DRAM Specification 128Mb Synchronous DRAM Specification A3V28S40JTP/JBF Zentel Electronics Corp. Revision 1.1 28M Single Data Rate Synchronous DRAM General Description A3V28S40JTP/JBF is organized as 4-bank x 2,097,154-word

More information

PT483208FHG PT481616FHG

PT483208FHG PT481616FHG Table of Content- 8M x 4Banks x 8bits SDRAM 4M x 4Banks x 16bits SDRAM 1. GENERAL DESCRIPTION...3 2. FEATURES...3 3. PART NUMBER INFORMATION...3 4. PIN CONFIGURATION...4 5. PIN DESCRIPTION...5 6. BLOCK

More information

256Mb Synchronous DRAM Specification

256Mb Synchronous DRAM Specification 256Mb Synchronous DRAM Specification P3V56S30ETP P3V56S40ETP Deutron Electronics Corp. 8F, 68, Sec. 3, NanKing E. RD., Taipei 104, Taiwan, R.O.C. TEL: (886)-2-2517-7768 FAX: (886)-2-2517-4575 http://www.deutron.com.tw

More information

512K x 16Bit x 2Banks Synchronous DRAM. (TSOPII 50L, 400milX825mil Body, 0.8mm Pin Pitch)

512K x 16Bit x 2Banks Synchronous DRAM. (TSOPII 50L, 400milX825mil Body, 0.8mm Pin Pitch) SDRAM 512K x 16Bit x 2Banks Synchronous DRAM FEATURES JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Dual banks operation MRS cycle with address key programs - Latency (2 &

More information

2M x 16 Bit x 4 Banks Synchronous DRAM. Rev. No. History Issue Date Remark

2M x 16 Bit x 4 Banks Synchronous DRAM. Rev. No. History Issue Date Remark Preliminary 2M x 16 Bit x 4 Banks Synchronous DRAM Document Title 2M x 16 Bit x 4 Banks Synchronous DRAM Revision History Rev. No. History Issue Date Remark 0.0 Initial issue August 7, 2007 Preliminary

More information

ESMT M52S32162A. Operation Temperature Condition -40 C ~85 C. Revision History : Revision 1.0 (Jul. 25, 2007) - Original

ESMT M52S32162A. Operation Temperature Condition -40 C ~85 C. Revision History : Revision 1.0 (Jul. 25, 2007) - Original Revision History : Revision 1.0 (Jul. 25, 2007) - Original Revision : 1.0 1/30 SDRAM 1M x 16Bit x 2Banks Synchronous DRAM FEATURES 2.5V power supply LVCMOS compatible with multiplexed address Dual banks

More information

ESMT M52D32321A. Revision History : Revision 1.0 (Nov. 02, 2006) -Original. Revision 1.1 (Mar. 02, 2007) - Delete BGA ball name of packing dimensions

ESMT M52D32321A. Revision History : Revision 1.0 (Nov. 02, 2006) -Original. Revision 1.1 (Mar. 02, 2007) - Delete BGA ball name of packing dimensions Revision History : Revision 1.0 (Nov. 02, 2006) -Original Revision 1.1 (Mar. 02, 2007) - Delete BGA ball name of packing dimensions Revision 1.2 (May. 03, 2007) - Modify DC Characteristics Revision 1.3

More information

ESMT M52D16161A. Mobile Synchronous DRAM FEATURES GENERAL DESCRIPTION ORDERING INFORMATION PIN CONFIGURATION (TOP VIEW)

ESMT M52D16161A. Mobile Synchronous DRAM FEATURES GENERAL DESCRIPTION ORDERING INFORMATION PIN CONFIGURATION (TOP VIEW) Mobile SDRAM 512K x 16Bit x 2Banks Mobile Synchronous DRAM FEATURES 1.8V power supply LVCMOS compatible with multiplexed address Dual banks operation MRS cycle with address key programs - Latency (2 &

More information

M52D128168A (2E) BALL CONFIGURATION (TOP VIEW) (BGA54, 8mmX8mmX1mm Body, 0.8mm Ball Pitch) VDDQ VDDQ VSSQ DQ6 DQ5 CAS BA0

M52D128168A (2E) BALL CONFIGURATION (TOP VIEW) (BGA54, 8mmX8mmX1mm Body, 0.8mm Ball Pitch) VDDQ VDDQ VSSQ DQ6 DQ5 CAS BA0 Mobile SDRAM 2M x 16 Bit x 4 Banks Mobile Synchronous DRAM FEATURES 1.8V power supply LVCMOS compatible with multiplexed address Four banks operation MRS cycle with address key programs - CAS Latency (2

More information

ESMT M12L16161A. Revision History. Revision 0.1 (Oct ) -Original. Revision 0.2 (Dec ) -Add 200MHZ

ESMT M12L16161A. Revision History. Revision 0.1 (Oct ) -Original. Revision 0.2 (Dec ) -Add 200MHZ Revision History Revision 0.1 (Oct. 23 1998) -Original Revision 0.2 (Dec. 4 1998) -Add 200MHZ Revision 1.0 (Dec. 10 1999) -Delete Preliminary -Rename the filename Revision 1.1 (Jan. 26 2000) -Add 5.5 Spec.

More information

A43L2616B. 1M X 16 Bit X 4 Banks Synchronous DRAM. Document Title 1M X 16 Bit X 4 Banks Synchronous DRAM. Revision History. AMIC Technology, Corp.

A43L2616B. 1M X 16 Bit X 4 Banks Synchronous DRAM. Document Title 1M X 16 Bit X 4 Banks Synchronous DRAM. Revision History. AMIC Technology, Corp. 1M X 16 Bit X 4 Banks Synchronous DRAM Document Title 1M X 16 Bit X 4 Banks Synchronous DRAM Revision History Rev. No. History Issue Date Remark 0.0 Initial issue August 24, 2006 Preliminary 0.1 Change

More information

M52D A (2F) BALL CONFIGURATION (TOP VIEW) (BGA54, 8mmX8mmX1mm Body, 0.8mm Ball Pitch)

M52D A (2F) BALL CONFIGURATION (TOP VIEW) (BGA54, 8mmX8mmX1mm Body, 0.8mm Ball Pitch) Mobile SDRAM FEATURES 1.8V power supply LVCMOS compatible with multiplexed address Four banks operation MRS cycle with address key programs - CAS Latency (3) - Burst Length (1, 2, 4, 8 & full page) - Burst

More information

Part No. Organization tck Frequency Package. Part No. Organization tck Frequency Package

Part No. Organization tck Frequency Package. Part No. Organization tck Frequency Package Features Clock frequency: 166, 133 MHz Fully synchronous; all signals referenced to a positive clock edge Four banks operation Single 3.3V power supply LVTTL interface Programmable burst length -- (1,

More information

512K x 32 Bit x 4 Banks Synchronous DRAM

512K x 32 Bit x 4 Banks Synchronous DRAM SDRAM FEATURES JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs - Latency ( 2 & 3 ) - Burst Length ( 1, 2, 4, 8 & full

More information

ESMT M52S128168A. Revision History. Elite Semiconductor Memory Technology Inc. Publication Date: Oct Revision: 1.1 1/47

ESMT M52S128168A. Revision History. Elite Semiconductor Memory Technology Inc. Publication Date: Oct Revision: 1.1 1/47 Revision History Revision 1.0 (May. 29, 2007) -Original Revision 1.1 (Oct. 08, 2007) -Add Speed -7 spec. -Modify Icc spec Revision: 1.1 1/47 Mobile SDRAM FEATURES ORDERING INFORMATION 2M x 16 Bit x 4 Banks

More information

A43L8316A. 128K X 16 Bit X 2 Banks Synchronous DRAM. Document Title 128K X 16 Bit X 2 Banks Synchronous DRAM. Revision History. AMIC Technology, Corp.

A43L8316A. 128K X 16 Bit X 2 Banks Synchronous DRAM. Document Title 128K X 16 Bit X 2 Banks Synchronous DRAM. Revision History. AMIC Technology, Corp. 128K X 16 Bit X 2 Banks Synchronous DRAM Document Title 128K X 16 Bit X 2 Banks Synchronous DRAM Revision History Rev. No. History Issue Date Remark 0.0 Initial issue February 23, 2001 Preliminary 1.0

More information

PMS306416B. Document Title. Revision History. 64Mb (4Mb x 16) SDRAM Datasheet

PMS306416B. Document Title. Revision History. 64Mb (4Mb x 16) SDRAM Datasheet Document Title 64Mb (4Mb x 16) SDRAM Datasheet Revision History Revision Date Page Notes 1.0 November, 2010 Original 1.1 August, 2014 7 Idd spec revision This document is a general product description

More information

ESMT M12L64164A. Revision History. Elite Semiconductor Memory Technology Inc. Publication Date: Dec Revision: 1.2 1/45

ESMT M12L64164A. Revision History. Elite Semiconductor Memory Technology Inc. Publication Date: Dec Revision: 1.2 1/45 Revision History Revision 0.1 (Dec. 12 2004) - Original Revision 1.0 (Jun. 13 2006) - Add Pb free Revision 1.1 (Dec. 29 2006) - Add -5TIG and -5BIG spec Revision 1.2 (Dec. 13 2007) - Add BGA type to ordering

More information

SYNCHRONOUS DRAM. 256Mb: x4, x8, x16 SDRAM 3.3V

SYNCHRONOUS DRAM. 256Mb: x4, x8, x16 SDRAM 3.3V SYNCHRONOUS DRAM 256Mb: x4, x8, x16 Features: Intel PC133 (3-3-3) compatible Fully synchronous; all signals registered on positive edge of system clock Internal pipelined operation; column address can

More information

DATA SHEET. 512M bits SDRAM. EDS5104ABTA (128M words 4 bits) EDS5108ABTA (64M words 8 bits) EDS5116ABTA (32M words 16 bits) EOL Product VDD NC DQ0

DATA SHEET. 512M bits SDRAM. EDS5104ABTA (128M words 4 bits) EDS5108ABTA (64M words 8 bits) EDS5116ABTA (32M words 16 bits) EOL Product VDD NC DQ0 DATA SHEET 512M bits SDRAM EDS5104ABTA (128M words 4 bits) EDS5108ABTA (64M words 8 bits) EDS5116ABTA (32M words 16 bits) Description The EDS5104AB is a 512M bits SDRAM organized as 33,554,432 words 4

More information

参考資料 PRELIMINARY DATA SHEET. 128M bits SDRAM. EDS1216AGTA (8M words 16 bits) DQ7 VDD LDQM /WE /CAS /RAS /CS BA0 BA1 A10 A0 A1 A2 A3 VDD

参考資料 PRELIMINARY DATA SHEET. 128M bits SDRAM. EDS1216AGTA (8M words 16 bits) DQ7 VDD LDQM /WE /CAS /RAS /CS BA0 BA1 A10 A0 A1 A2 A3 VDD PRELIMINARY DATA SHEET 128M bits SDRAM (8M words 16 bits) Specifications Density: 128M bits Organization 2M words 16 bits 4 banks Package: 54-pin plastic TSOP (II) Lead-free (RoHS compliant) Power supply:

More information

PMS306416C. Document Title. 64Mb (4Mb x 16) SDRAM (C die) Datasheet

PMS306416C. Document Title. 64Mb (4Mb x 16) SDRAM (C die) Datasheet Document Title 64Mb (4Mb x 16) SDRAM (C die) Datasheet This document is a general product description and subject to change without notice. 64MBIT SDRAM Features JEDEC SDR Compliant All signals referenced

More information

IS42S Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM FEATURES OVERVIEW. PIN CONFIGURATIONS 54-Pin TSOP (Type II)

IS42S Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM FEATURES OVERVIEW. PIN CONFIGURATIONS 54-Pin TSOP (Type II) 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM JANUARY 2008 FEATURES Clock frequency: 166, 143 MHz Fully synchronous; all signals referenced to a positive clock edge Internal bank for

More information

IS42S Meg x MBIT SYNCHRONOUS DRAM SEPTEMBER 2009

IS42S Meg x MBIT SYNCHRONOUS DRAM SEPTEMBER 2009 16Meg x16 256-MBIT SYNCHRONOUS DRAM SEPTEMBER 2009 FEATURES Clock frequency: 166, 143, 133 MHz Fully synchronous; all signals referenced to a positive clock edge Internal bank for hiding row access/precharge

More information

128Mb Synchronous DRAM. Features High Performance: Description. REV 1.0 May, 2001 NT5SV32M4CT NT5SV16M8CT NT5SV8M16CT

128Mb Synchronous DRAM. Features High Performance: Description. REV 1.0 May, 2001 NT5SV32M4CT NT5SV16M8CT NT5SV8M16CT Features High Performance: f Clock Frequency -7K 3 CL=2-75B, CL=3-8B, CL=2 Single Pulsed RAS Interface Fully Synchronous to Positive Clock Edge Four Banks controlled by BS0/BS1 (Bank Select) Units 133

More information

IS42S16400J IS45S16400J

IS42S16400J IS45S16400J 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM JULY 2014 FEATURES Clock frequency: 200, 166, 143, 133 MHz Fully synchronous; all signals referenced to a positive clock edge Internal bank

More information

512K 4 BANKS 32BITS SDRAM

512K 4 BANKS 32BITS SDRAM Table of Contents- 512K 4 BANKS 32BITS SDRAM 1. GENERAL DESCRIPTION... 3 2. FEATURES... 3 3. ORDER INFORMATION... 3 4. PIN CONFIGURATION... 4 5. PIN DESCRIPTION... 5 6. BLOCK DIAGRAM... 6 7. FUNCTIONAL

More information

4Byte 4Mx36 SIMM. (4Mx16 & Quad CAS 4Mx4 base) Revision 0.1. June

4Byte 4Mx36 SIMM. (4Mx16 & Quad CAS 4Mx4 base) Revision 0.1. June 4Byte 4Mx36 SIMM (4Mx16 & Quad CAS 4Mx4 base) Revision 0.1 June 1998 Revision History Version 0.0 (Sept. 1997) Removed two AC parameters P(access time from CAS) and P(access time from col. addr.) in AC

More information

IS42S32160B IS45S32160B

IS42S32160B IS45S32160B IS42S32160B IS45S32160B 16M x 32 512Mb SYNCHRONOUS DRAM DECEMBER 2009 FEATURES Clock frequency: 166, 143 MHz Fully synchronous; all signals referenced to a positive clock edge Internal bank for hiding

More information

512K 4 BANKS 32BITS SDRAM

512K 4 BANKS 32BITS SDRAM 512K 4 BANKS 32BITS SDRAM Table of Contents- 1. GENERAL DESCRIPTION... 3 2. FEATURES... 3 3. ORDER INFORMATION... 3 4. BALL CONFIGURATION... 4 5. BALL DESCRIPTION... 5 6. BLOCK DIAGRAM... 6 7. FUNCTIONAL

More information

ESMT M12L A (2A) SDRAM. 4M x 16 Bit x 4 Banks Synchronous DRAM ORDERING INFORMATION FEATURES GENERAL DESCRIPTION

ESMT M12L A (2A) SDRAM. 4M x 16 Bit x 4 Banks Synchronous DRAM ORDERING INFORMATION FEATURES GENERAL DESCRIPTION SDRAM 4M x 16 Bit x 4 Banks Synchronous DRAM FEATURES JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs - CAS Latency (

More information

IS42S86400B IS42S16320B, IS45S16320B

IS42S86400B IS42S16320B, IS45S16320B IS42S86400B IS42S16320B, IS45S16320B 64M x 8, 32M x 16 512Mb SYNCHRONOUS DRAM DECEMBER 2011 FEATURES Clock frequency: 166, 143, 133 MHz Fully synchronous; all signals referenced to a positive clock edge

More information

DTM68102D. 16GB Pin 2Rx4 Registered ECC DDR4 DIMM. DTM68102D 2Gx72 16G 2Rx4 PC4-2133P-RBP-10

DTM68102D. 16GB Pin 2Rx4 Registered ECC DDR4 DIMM. DTM68102D 2Gx72 16G 2Rx4 PC4-2133P-RBP-10 Features 288-pin JEDEC-compliant DIMM, 133.35 mm wide by 31.25 mm high Operating Voltage: VDD/VDDQ = 1.2V (1.14V to 1.26V) VPP = 2.5V (2.375V to 2.75V) VDDSPD = 2.25V to 2.75V I/O Type: 1.2 V signaling

More information

1M 4 BANKS 16 BITS SDRAM

1M 4 BANKS 16 BITS SDRAM 1M 4 BANKS 16 BITS SDRAM Table of Contents- 1. GENERAL DESCRIPTION... 3 2. FEATURES... 3 3. ORDER INFORMATION... 3 4. BALL CONFIGURATION... 4 5. BALL DESCRIPTION... 5 6. BLOCK DIAGRAM... 6 7. FUNCTIONAL

More information

ESMT M13L32321A -7.5BG2G DDR SDRAM. 512K x 32 Bit x 2 Banks Double Data Rate SDRAM. Features. Ordering Information

ESMT M13L32321A -7.5BG2G DDR SDRAM. 512K x 32 Bit x 2 Banks Double Data Rate SDRAM. Features. Ordering Information DDR SDRAM 512K x 32 Bit x 2 Banks Double Data Rate SDRAM Features Double-data-rate architecture, two data transfers per clock cycle Bi-directional data strobe () Differential clock inputs ( and ) DLL aligns

More information

IS42S32200C1. 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM

IS42S32200C1. 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM JANUARY 2007 FEATURES Clock frequency: 183, 166, 143 MHz Fully synchronous; all signals referenced to a positive clock edge Internal bank

More information

IS42S32200L IS45S32200L

IS42S32200L IS45S32200L IS42S32200L IS45S32200L 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM OCTOBER 2012 FEATURES Clock frequency: 200, 166, 143, 133 MHz Fully synchronous; all signals referenced to a positive

More information

ESMT M13S A (2K) DDR SDRAM. 4M x 16 Bit x 4 Banks Double Data Rate SDRAM. Features. Ordering Information

ESMT M13S A (2K) DDR SDRAM. 4M x 16 Bit x 4 Banks Double Data Rate SDRAM. Features. Ordering Information DDR SDRAM 4M x 16 Bit x 4 Banks Double Data Rate SDRAM Features Double-data-rate architecture, two data transfers per clock cycle Bi-directional data strobe () Differential clock inputs ( and ) DLL aligns

More information

IS42S16800A. 8Meg x MBIT SYNCHRONOUS DRAM JUNE 2007

IS42S16800A. 8Meg x MBIT SYNCHRONOUS DRAM JUNE 2007 8Meg x16 128-MBIT SYNCHRONOUS DRAM JUNE 2007 FEATURES Clock frequency: 143, 100 MHz Fully synchronous; all signals referenced to a positive clock edge Internal bank for hiding row access/precharge Power

More information

512K 4 BANKS 32BITS SDRAM

512K 4 BANKS 32BITS SDRAM 512K 4 BANKS 32BITS SDRAM Table of Contents- 1. GENERAL DESCRIPTION... 3 2. FEATURES... 3 3. AVAILABLE PART NUMBER... 3 4. PIN CONFIGURATION...4 5. PIN DESCRIPTION... 5 6. BLOCK DIAGRAM... 6 7. FUNCTIONAL

More information

IS42S32400B. 4Meg x MBIT SYNCHRONOUS DRAM

IS42S32400B. 4Meg x MBIT SYNCHRONOUS DRAM 4Meg x 32 128-MBIT SYNCHRONOUS DRAM PRELIMINARY INFORMATION MARCH 2009 FEATURES Clock frequency: 166, 143, 125, 100 MHz Fully synchronous; all signals referenced to a positive clock edge Internal bank

More information

PMD706416A. Document Title. 64Mb (4M x 16) DDR SDRAM (A die) Datasheet

PMD706416A. Document Title. 64Mb (4M x 16) DDR SDRAM (A die) Datasheet Document Title 64Mb (4M x 16) DDR SDRAM (A die) Datasheet This document is a general product description and subject to change without notice. 64MBIT DDR DRAM Features JEDEC DDR Compliant Differential

More information

IS42S81600D IS42S16800D

IS42S81600D IS42S16800D IS42S81600D IS42S16800D 16Meg x 8, 8Meg x16 128-MBIT SYNCHRONOUS DRAM JULY 2008 FEATURES Clock frequency: 166, 143, 133 MHz Fully synchronous; all signals referenced to a positive clock edge Internal bank

More information

1. GENERAL DESCRIPTION

1. GENERAL DESCRIPTION 1. GENERAL DESCRIPTION The Winbond 512Mb Low Power SDRAM is a low power synchronous memory containing 536,870,912 memory cells fabricated with Winbond high performance process technology. It is designed

More information

Feature. 512Mb DDR SDRAM. REV 1.1 Jul CAS Latency Frequency NT5DS64M8DS NT5DS32M16DS CONSUMER DRAM. 2KB page size for all configurations.

Feature. 512Mb DDR SDRAM. REV 1.1 Jul CAS Latency Frequency NT5DS64M8DS NT5DS32M16DS CONSUMER DRAM. 2KB page size for all configurations. Feature CAS Latency Frequency DDR-333 DDR400 DDR500 Speed Sorts Units -6K/-6KI -5T/-5TI -4T CL-tRCD-tRP 2.5-3-3 3-3-3 3-4-4 tck CL=2 266 266-2KB page size for all configurations. DQS is edge-aligned with

More information

4 M 4 BANKS 16 BITS SDRAM

4 M 4 BANKS 16 BITS SDRAM 4 M 4 BANKS 16 BITS SDRAM Table of Contents- 1. GENERAL DESCRIPTION... 3 2. FEATURES... 3 3. ORDER INFORMATION... 4 4. PIN CONFIGURATION... 4 5. PIN DESCRIPTION... 5 6. BLOCK DIAGRAM... 6 7. FUNCTIONAL

More information

PMD709408C/PMD709416C. Document Title. Revision History. 512Mb (64M x 8 / 32M x 16) DDR SDRAM C die Datasheet

PMD709408C/PMD709416C. Document Title. Revision History. 512Mb (64M x 8 / 32M x 16) DDR SDRAM C die Datasheet Document Title 512Mb (64M x 8 / 32M x 16) DDR SDRAM C die Datasheet Revision History Revision Date Page Notes 0.1 October, 2013 Preliminary 1.0 March, 2014 Official release 1.1 April, 2014 500Mbps speed

More information

1M 4 BANKS 32 BITS SDRAM

1M 4 BANKS 32 BITS SDRAM 1M 4 BANKS 32 BITS SDRAM Table of Contents- 1. GENERAL DESCRIPTION... 3 2. FEATURES... 3 3. ORDER INFORMATION... 4 4. BALL CONFIGURATION... 5 5. BALL DESCRIPTION... 6 6. BLOCK DIAGRAM (SINGLE CHIP)...

More information

Ordering Information. Row Address. Row Decoder. Buffer & Refresh Counter. Column. Address. Buffer & Refresh Counter

Ordering Information. Row Address. Row Decoder. Buffer & Refresh Counter. Column. Address. Buffer & Refresh Counter Mobile DDR SDRAM Features JEDEC Standard Internal pipelined double-data-rate architecture, two data access per clock cycle Bi-directional data strobe () No DLL; to is not synchronized. Differential clock

More information

8. OPERATION Read Operation Write Operation Precharge... 18

8. OPERATION Read Operation Write Operation Precharge... 18 128Mb Mobile LPSDR Table of Contents- 1. GENERAL DESCRIPTION... 4 2. FEATURES... 4 3. ORDER INFORMATION... 4 4. BALL CONFIGURATION... 5 4.1 Ball Assignment: LPSDR x16... 5 4.2 Ball Assignment: LPSDR x32...

More information

SDRAM DEVICE OPERATION

SDRAM DEVICE OPERATION POWER UP SEQUENCE SDRAM must be initialized with the proper power-up sequence to the following (JEDEC Standard 21C 3.11.5.4): 1. Apply power and start clock. Attempt to maintain a NOP condition at the

More information

SDRAM AS4SD8M Mb: 8 Meg x 16 SDRAM Synchronous DRAM Memory. PIN ASSIGNMENT (Top View)

SDRAM AS4SD8M Mb: 8 Meg x 16 SDRAM Synchronous DRAM Memory. PIN ASSIGNMENT (Top View) 128 Mb: 8 Meg x 16 SDRAM Synchronous DRAM Memory FEATURES Full Military temp (-55 C to 125 C) processing available Configuration: 8 Meg x 16 (2 Meg x 16 x 4 banks) Fully synchronous; all signals registered

More information

128Mb/ 8M x 16 bit Synchronous DRAM (SDRAM)

128Mb/ 8M x 16 bit Synchronous DRAM (SDRAM) Alliance Memory 128Mb/ 8M x 16 bit Synchronous DRAM (SDRAM) Features Fast access time from clock: 5/5.4 ns Fast clock rate: 166/143 MHz Fully synchronous operation Internal pipelined architecture 2M word

More information

V58C2256(804/404/164)SH HIGH PERFORMANCE 256 Mbit DDR SDRAM 4 BANKS X 8Mbit X 8 (804) 4 BANKS X 4Mbit X 16 (164) 4 BANKS X 16Mbit X 4 (404)

V58C2256(804/404/164)SH HIGH PERFORMANCE 256 Mbit DDR SDRAM 4 BANKS X 8Mbit X 8 (804) 4 BANKS X 4Mbit X 16 (164) 4 BANKS X 16Mbit X 4 (404) V58C2256804/404/164SH HIGH PERFORMAE 256 Mbit DDR SDRAM 4 BANKS X 8Mbit X 8 804 4 BANKS X 4Mbit X 16 164 4 BANKS X 16Mbit X 4 404 4 5 6 DDR500 DDR400 DDR333 Clock Cycle Time t CK2 5ns 7.5ns 7.5ns Clock

More information

2M 4 BANKS 16 BITS SDRAM

2M 4 BANKS 16 BITS SDRAM 2M 4 BANKS 16 BITS SDRAM Table of Contents- 1. GENERAL DESCRIPTION... 3 2. FEATURES... 3 3. AVAILABLE PART NUMBER... 3 4. BALL CONFIGURATION... 4 5. BALL DESCRIPTION... 5 6. BLOCK DIAGRAM... 6 7. FUNCTIONAL

More information

A48P4616B. 16M X 16 Bit DDR DRAM. Document Title 16M X 16 Bit DDR DRAM. Revision History. AMIC Technology, Corp. Rev. No. History Issue Date Remark

A48P4616B. 16M X 16 Bit DDR DRAM. Document Title 16M X 16 Bit DDR DRAM. Revision History. AMIC Technology, Corp. Rev. No. History Issue Date Remark 16M X 16 Bit DDR DRAM Document Title 16M X 16 Bit DDR DRAM Revision History Rev. No. History Issue Date Remark 1.0 Initial issue January 9, 2014 Final (January, 2014, Version 1.0) AMIC Technology, Corp.

More information

4 M 4 BANKS 16 BITS SDRAM

4 M 4 BANKS 16 BITS SDRAM 4 M 4 BANKS 16 BITS SDRAM Table of Contents- 1. GENERAL DESCRIPTION... 3 2. FEATURES... 3 3. AVAILABLE PART NUMBER... 3 4. PIN CONFIGURATION... 4 5. PIN DESCRIPTION... 5 6. BLOCK DIAGRAM... 6 7. FUNCTIONAL

More information

SYNCHRONOUS DRAM. 128Mb: x32 SDRAM. MT48LC4M32B2-1 Meg x 32 x 4 banks

SYNCHRONOUS DRAM. 128Mb: x32 SDRAM. MT48LC4M32B2-1 Meg x 32 x 4 banks SYNCHRONOUS DRAM 128Mb: x32 MT48LC4M32B2-1 Meg x 32 x 4 banks For the latest data sheet, please refer to the Micron Web site: www.micron.com/sdramds FEATURES PC100 functionality Fully synchronous; all

More information

1M 4 BANKS 32BIT SDRAM

1M 4 BANKS 32BIT SDRAM 1M 4 BANKS 32BIT SDRAM Table of Contents- 1 GENERAL DESCRIPTION... 3 2 FEATURES... 3 3 AVAILABLE PART NUMBER... 3 4 PIN CONFIGURATION... 4 5 PIN DESCRIPTION... 5 6 BLOCK DIAGRAM... 6 7 FUNCTIONAL DESCRIPTION...

More information

1M 4 BANKS 32BITS SDRAM

1M 4 BANKS 32BITS SDRAM 1M 4 BANKS 32BITS SDRAM Table of Contents- 1. GENERAL DESCRIPTION... 3 2. FEATURES... 3 3. AVAILABLE PART NUMBER... 3 4. BALL CONFIGURATION... 4 5. BALL DESCRIPTION... 5 6. BLOCK DIAGRAM... 6 7. FUNCTIONAL

More information

1M 4 BANKS 16 BITS SDRAM

1M 4 BANKS 16 BITS SDRAM 1M 4 BANKS 16 BITS SDRAM Table of Contents- 1. GENERAL DESCRIPTION... 3 2. FEATURES... 3 3. AVAILABLE PART NUMBER... 4 4. PIN CONFIGURATION...4 5. PIN DESCRIPTION... 5 6. BLOCK DIAGRAM... 6 7. FUNCTIONAL

More information

SDRAM Device Operations

SDRAM Device Operations DEVICE OPERATIONS SDRAM Device Operations * Samsung Electronics reserves the right to change products or specification without notice. EECTRONICS DEVICE OPERATIONS A. MODE REGISTER FIED TABE TO PROGRAM

More information

512K 2 BANKS 16 BITS SDRAM

512K 2 BANKS 16 BITS SDRAM 512K 2 BANKS 16 BITS SDRAM Table of Contents- 1. GENERAL DESCRIPTION... 3 2. FEATURES... 3 3. AVAILABLE PART NUMBER... 3 4. PIN CONFIGURATION...4 5. PIN DESCRIPTION... 5 6. BLOCK DIAGRAM... 6 7. FUNCTIONAL

More information

DTM68116D 32GB Pin 2Rx4 Registered ECC DDR4 DIMM

DTM68116D 32GB Pin 2Rx4 Registered ECC DDR4 DIMM Features 288-pin JEDEC-compliant DIMM, 133.35 mm wide by 31.25 mm high Operating Voltage: VDD/VDDQ = 1.2V (1.14V to 1.26V) VPP = 2.5V (2.375V to 2.75V) VDDSPD = 2.25V to 2.75V I/O Type: 1.2 V signaling

More information

256K x 32 / 512K x 32 / 1M x 32 Synchronous Graphic RAM

256K x 32 / 512K x 32 / 1M x 32 Synchronous Graphic RAM 256K x 32 / 512K x 32 / 1M x 32 Synchronous Graphic RAM ADDRESS TRANSLATION TABLE DEVICE OPERATIONS TIMING DIAGRAM PACKAGE DIAGRAM Samsung Electronics reserves the right to change products or specification

More information

1M 4 BANKS 16 BITS SDRAM

1M 4 BANKS 16 BITS SDRAM 1M 4 BANKS 16 BITS SDRAM Table of Contents- 1. GENERAL DESCRIPTION... 3 2. FEATURES... 3 3. ORDER INFORMATION... 3 4. PIN CONFIGURATION... 4 5. PIN DESCRIPTION... 5 6. BLOCK DIAGRAM... 6 7. FUNCTIONAL

More information

V58C2512(804/164)SH HIGH PERFORMANCE 512 Mbit DDR SDRAM 4 BANKS X 16Mbit X 8 (804) 4 BANKS X 8Mbit X 16 (164) Description

V58C2512(804/164)SH HIGH PERFORMANCE 512 Mbit DDR SDRAM 4 BANKS X 16Mbit X 8 (804) 4 BANKS X 8Mbit X 16 (164) Description V58C2512804/164SH HIGH PERFORMAE 512 Mbit DDR SDRAM 4 BANKS X 16Mbit X 8 804 4 BANKS X 8Mbit X 16 164 4 5 6 DDR500 DDR400 DDR333 Clock Cycle Time t CK2 7.5ns 7.5ns 7.5ns Clock Cycle Time t CK2.5 6ns 6ns

More information

OKI Semiconductor MD56V82160

OKI Semiconductor MD56V82160 4-Bank 4,194,304-Word 16-Bit SYNCHRONOUS DYNAMIC RAM FEDD56V82160-01 Issue Date:Feb.14, 2008 DESCRIPTION The is a 4-Bank 4,194,304-word 16-bit Synchronous dynamic RAM. The device operates at 3.3 V. The

More information

V58C SJ HIGH PERFORMANCE 256 Mbit DDR SDRAM 4 BANKS X 4Mbit X 16. Description

V58C SJ HIGH PERFORMANCE 256 Mbit DDR SDRAM 4 BANKS X 4Mbit X 16. Description HIGH PERFORMANCE 256 Mbit DDR SDRAM 4 BANKS X 4Mbit X 16 4 5 6 DDR500 DDR400 DDR333 Clock Cycle Time t CK2 5ns 7.5ns 7.5ns Clock Cycle Time t CK2.5 5ns 6ns 6ns Clock Cycle Time t CK3 4ns 5ns 6ns System

More information

MOS INTEGRATED CIRCUIT

MOS INTEGRATED CIRCUIT DATA SHEET 128M-bit Synchronous DRAM 4-bank, LVTTL MOS INTEGRATED CIRCUIT µpd45128163 Description The µpd45128163 is high-speed 134,217,728-bit synchronous dynamic random-access memory, organized as 2,097,152

More information

256M (16Mx16bit) Hynix SDRAM Memory

256M (16Mx16bit) Hynix SDRAM Memory 256Mb Synchronous DRAM based on 4M x 4Bank x16 I/O 256M (16Mx16bit) Hynix SDRAM Memory Memory Cell Array - Organized as 4banks of 4,194,304 x 16 This document is a general product description and is subject

More information

Mobile Low-Power SDR SDRAM

Mobile Low-Power SDR SDRAM Mobile Low-Power SDR SDRAM MT48H8M6LF 2 Meg x 6 x 4 banks MT48H4M32LF Meg x 32 x 4 banks 28Mb: 8 Meg x 6, 4 Meg x 32 Mobile SDRAM Features Features V DD /V D =.7.95V Fully synchronous; all signals registered

More information

128Mb DDR SDRAM. Features. Description. REV 1.1 Oct, 2006

128Mb DDR SDRAM. Features. Description. REV 1.1 Oct, 2006 Features Double data rate architecture: two data transfers per clock cycle Bidirectional data strobe () is transmitted and received with data, to be used in capturing data at the receiver is edge-aligned

More information

DOUBLE DATA RATE (DDR) SDRAM

DOUBLE DATA RATE (DDR) SDRAM UBLE DATA RATE Features VDD = +2.5V ±.2V, VD = +2.5V ±.2V Bidirectional data strobe transmitted/ received with data, i.e., source-synchronous data capture x6 has two one per byte Internal, pipelined double-data-rate

More information

TC59SM816/08/04BFT/BFTL-70,-75,-80

TC59SM816/08/04BFT/BFTL-70,-75,-80 TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC 4,194,304-WORDS 4 BANKS 16-BITS SYHRONOUS DYNAMIC RAM 8,388,608-WORDS 4 BANKS 8-BITS SYHRONOUS DYNAMIC RAM 16,777,216-WORDS 4 BANKS 4-BITS

More information

PRODUCT NO. MAX FREQ VDD PACKAGE COMMENTS M13S128168A -5TG 200MHz Pb-free 2.5V TSOPII M13S128168A -6TG 166MHz

PRODUCT NO. MAX FREQ VDD PACKAGE COMMENTS M13S128168A -5TG 200MHz Pb-free 2.5V TSOPII M13S128168A -6TG 166MHz DDR SDRAM 2M x 16 Bit x 4 Banks Double Data Rate SDRAM Features JEDEC Standard Internal pipelined double-data-rate architecture, two data access per clock cycle Bi-directional data strobe (DQS) On-chip

More information

Mobile SDRAM AVM121632S- 32M X 16 bit AVM123216S- 16M X 32 bit

Mobile SDRAM AVM121632S- 32M X 16 bit AVM123216S- 16M X 32 bit Mobile SDRAM AVM2632S- 32M X 6 bit AVM2326S- 6M X 32 bit Features V DD /V D =.7.95V Fully synchronous; all signals registered on positive edge of system clock Internal, pipelined operation; column address

More information

HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. B Data Sheet Jan. 2003, V1.1. Features. Description

HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. B Data Sheet Jan. 2003, V1.1. Features. Description Data Sheet Jan. 2003, V1.1 Features CAS Latency and Frequency Maximum Operating Frequency (MHz) CAS Latency DDR200-8 DDR266A -7 DDR266-7F DDR333-6 2 100 133 133 133 2.5 125 143 143 166 Double data rate

More information

TABLE OF CONTENTS 1. GENERAL DESCRIPTION FEATURES PIN DESCRIPTION Signal Descriptions BLOCK DIAGRAM...

TABLE OF CONTENTS 1. GENERAL DESCRIPTION FEATURES PIN DESCRIPTION Signal Descriptions BLOCK DIAGRAM... TABLE OF CONTENTS 1. GENERAL DESCRIPTION... 3 2. FEATURES... 3 3. PIN DESCRIPTION... 4 3.1 Signal Descriptions... 5 4. BLOCK DIAGRAM... 7 4.1 Block Diagram... 7 4.2 Simplified State Diagram... 8 5. FUNCTION

More information

4 M 4 BANKS 16 BITS SDRAM

4 M 4 BANKS 16 BITS SDRAM 4 M 4 BANKS 16 BITS SDRAM Table of Contents- 1. GENERAL DESCRIPTION... 3 2. FEATURES... 3 3. ORDER INFORMATION... 4 4. PIN CONFIGURATION... 4 5. PIN DESCRIPTION... 5 6. BLOCK DIAGRAM... 6 7. FUNCTIONAL

More information

t WR = 2 CLK A2 Notes:

t WR = 2 CLK A2 Notes: SDR SDRAM MT48LC16M4A2 4 Meg x 4 x 4 Banks MT48LC8M8A2 2 Meg x 8 x 4 Banks MT48LC4M16A2 1 Meg x 16 x 4 Banks 64Mb: x4, x8, x16 SDRAM Features Features PC100- and PC133-compliant Fully synchronous; all

More information

HYB25D256400B[T/C](L) HYB25D256800B[T/C](L) HYB25D256160B[T/C](L)

HYB25D256400B[T/C](L) HYB25D256800B[T/C](L) HYB25D256160B[T/C](L) Data Sheet, Rev. 1.21, Jul. 2004 HYB25D256400B[T/C](L) HYB25D256800B[T/C](L) HYB25D256160B[T/C](L) 256 Mbit Double Data Rate SDRAM DDR SDRAM Memory Products N e v e r s t o p t h i n k i n g. Edition 2004-07

More information

Notes: Clock Frequency (MHz) Target t RCD- t RP-CL t RCD (ns) t RP (ns) CL (ns) -6A

Notes: Clock Frequency (MHz) Target t RCD- t RP-CL t RCD (ns) t RP (ns) CL (ns) -6A SDR SDRAM MT48LC4M32B2 1 Meg x 32 x 4 s 128Mb: x32 SDRAM Features Features PC100-compliant Fully synchronous; all signals registered on positive edge of system clock Internal pipelined operation; column

More information

Notes: Clock Frequency (MHz) Target t RCD- t RP-CL t RCD (ns) t RP (ns) CL (ns) -6A E

Notes: Clock Frequency (MHz) Target t RCD- t RP-CL t RCD (ns) t RP (ns) CL (ns) -6A E SDR SDRAM MT48LC32M4A2 8 Meg x 4 x 4 Banks MT48LC16M8A2 4 Meg x 8 x 4 Banks MT48LC8M16A2 2 Meg x 16 x 4 Banks 128Mb: x4, x8, x16 SDRAM Features Features PC100- and PC133-compliant Fully synchronous; all

More information

HYB25D256400/800AT 256-MBit Double Data Rata SDRAM

HYB25D256400/800AT 256-MBit Double Data Rata SDRAM 256-MBit Double Data Rata SDRAM Features CAS Latency and Frequency Maximum Operating Frequency (MHz) CAS Latency DDR266A -7 DDR200-8 2 133 100 2.5 143 125 Double data rate architecture: two data transfers

More information

SDR SDRAM. MT48LC8M8A2 2 Meg x 8 x 4 Banks MT48LC4M16A2 1 Meg x 16 x 4 Banks. Features. 64Mb: x8, x16 SDRAM. Features

SDR SDRAM. MT48LC8M8A2 2 Meg x 8 x 4 Banks MT48LC4M16A2 1 Meg x 16 x 4 Banks. Features. 64Mb: x8, x16 SDRAM. Features SDR SDRAM MT48LC8M8A2 2 Meg x 8 x 4 Banks MT48LC4M16A2 1 Meg x 16 x 4 Banks 64Mb: x8, x16 SDRAM Features Features PC100- and PC133-compliant Fully synchronous; all signals registered on positive edge of

More information

SDR SDRAM. MT48LC32M4A2 8 Meg x 4 x 4 Banks MT48LC16M8A2 4 Meg x 8 x 4 Banks MT48LC8M16A2 2 Meg x 16 x 4 Banks. Features. 128Mb: x4, x8, x16 SDRAM

SDR SDRAM. MT48LC32M4A2 8 Meg x 4 x 4 Banks MT48LC16M8A2 4 Meg x 8 x 4 Banks MT48LC8M16A2 2 Meg x 16 x 4 Banks. Features. 128Mb: x4, x8, x16 SDRAM SDR SDRAM MT48LC32M4A2 8 Meg x 4 x 4 Banks MT48LC16M8A2 4 Meg x 8 x 4 Banks MT48LC8M16A2 2 Meg x 16 x 4 Banks 128Mb: x4, x8, x16 SDRAM Features Features PC100- and PC133-compliant Fully synchronous; all

More information

EM828164PAY-xxUx. Document Title. Revision History. 1 Rev M: 8M x 16 Mobile SDRAM. 128M: 8M x 16 Mobile SDRAM. Revision No.

EM828164PAY-xxUx. Document Title. Revision History. 1 Rev M: 8M x 16 Mobile SDRAM. 128M: 8M x 16 Mobile SDRAM. Revision No. Document Title Revision History Revision No. Date History 0.0 Oct 15, 2009 -. Initial Draft 0.1 Dec 23, 2009 -. Product code changed to EM828164PAY-xxUx 0.2 Jun 7, 2010 -. toh updated in Table8 OPERATING

More information