( DOC No. HX8678-A-DS ) HX8678-A

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1 ( DOC No. HX8678-A-DS ) HX8678-A Preliminary version 01 July, 2006

Preliminary Version 01 July, 2006 1. General Description The HX8678-A is a 480/320 channels output gate driver used for driving the gate electrode of TFT LCD panel.

2 Preliminary Version 01 July, General Description The HX8678-A is a 480/320 channels output gate driver used for driving the gate electrode of TFT LCD panel. It is designed for 2-level output with maximum +40V output driving voltage. 2. Features 2-level output gate driver for TFT LCD panel 480/320 channels output selectable gate driver with 2 dummy output Maximum +40V output driving voltage Bi-directional data shift capability 200KHz maximum operation frequency High voltage CMOS process technology COG/COF package -P.1-

3 3. Block Diagram OUT481 OUT480 OUT479 OUT478 OUT3 OUT2 OUT1 OUT0 Output Buffer Level Shifter CPV L/R Bi-directional Shifter Register STV1 STV2 OE1 OE2 OE3 /XAO MODE Input Buffer VSS Note: OUT0 and OUT481 are LCD panel auxiliary pins, these pins always output level. -P.2-

4 4. Pin Description Pin name I/O Function Description CPV In Shift clock input This is the clock input for chip internal shift register. Data is shifted at each rising edge of this clock. This pin controls the output shifting direction as listed L/R In L/R =L:STV2 OUT480 OUT2 OUT1 STV1 Shift direction below. control pin L/R =H:STV1 OUT1 OUT2 OUT480 STV2 STV1 STV2 OE1 OE2 OE3 /XAO MODE OUT1 ~ OUT480 OUT0 I/O In In In Out Start pulse input/output pin Output enable control Output all-on control Output Channel number selection Driver output pins for driving gate electrode of LCD Out Auxiliary pins These two pins are the device start pulse input or output pin. The function of these two pins depends on the status of L/R pin. STV1 STV2 L/R=H input output L/R=L output input These three pins are used to control the driver output. When OE1 ~ OE3 input are H, driver output is fixed to regardless CPV. However, the internal shift register is not cleared even if OE1 ~ OE3 input are inactive. When /XAO input pin is L, all the output pins are forced to level. Note that this pin has higher priority than OE. Also it has an internal pull high resistor, keep it to is preferred when unused. The chip internal shift register is not cleared when /XAO input is active. They is the output channel number selection pin: MODE Output L 320 channels H 480 channels The output voltage is either or for driving the gate electrode of TFT LCD panel depending on the data stored in shift register and the state of OE. LCD panel auxiliary pins, these pins always output level. OUT481 In Power supply Power supply for LCM drive output High In Power supply Digital power VSS In Power supply Digital ground In Power supply Power supply for LCM drive output low. PATH In Internal link Linked together internal. -P.3-

5 5. Function Description 5.1 Device operation In the condition of MODE=H & L/R=H, the STV1 start pulse input is sensed at the rising edge of CPV and stored in the first stage of shift register, which causes the first scan signal is outputted from the OUT1 output pin. While stored data is transferred to the next stage shift register at the rising edge of next CPV, new data of STV1 is sensed and stored simultaneously. The output pin (OUT1 to OUT480) supplies voltage or voltage to the LCD panel depending on the data stored in the shift register. For normal operation, a voltage is outputted one by one from OUT1 to OUT480 in sync with CPV pulse. After 480 CPV rising edge are past, the STV2 goes up to high level at the 480th falling edge of CPV and goes down to low level at the 481 st falling edge of CPV. This STV2 output signal becomes the STV1 start pulse input of next cascaded gate driver device. During any H state of OE, the corresponding output channels are forced to level regardless of CPV. The channel output returns to normal status as soon as OE go back to L. Example of input/output timing (MODE=H, L/R=H) CPV STV1 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT479 OUT STV2 -P.4-

6 Example of input/output timing (MODE=H, L/R=L) CPV STV OUT480 OUT479 OUT478 OUT477 OUT476 OUT475 OUT2 OUT1 STV1 Example of input/output timing (MODE=H, L/R=H with OE & /XAO) CPV STV OE1 OE2 OE3 /XAO OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT479 OUT480 STV2 -P.5-

7 5.2 Relationship among L/R, and STV1/STV2 L/R Start pulse Input Output Data transfer direction H STV1 STV2 OUT1 OUT2 OUT3 OUT480 L STV2 STV1 OUT480 OUT479 OUT478 OUT1 5.3 Output channel mode Output channel number is selectable between 480/320 by MODE pin. The following table explains MODE vs. output channel and OE[1:3] vs. output channel. The disable output that is fixed to must be kept open. MODE=L MODE=H Output Channel Output Output 320CH 480CH control control OUT1 1st OE1 1st OE1 OUT2 2nd OE2 2nd OE2 OUT3 3rd OE3 3rd OE3 : : : : : OUT th OE1 160th OE1 OUT161 Fix to : 161st OE2 OUT162 Fix to : 162nd OE3 OUT163 Fix to : 163rd OE1 : : : : : OUT201 Fix to : 201st OE3 OUT202 Fix to : 202nd OE1 OUT203 Fix to : 203rd OE2 OUT204 Fix to : 204th OE3 : : : : : OUT279 Fix to : 279th OE3 OUT280 Fix to : 280th OE1 OUT281 Fix to : 281st OE2 OUT282 Fix to : 282nd OE3 : : : : : OUT320 Fix to : 320th OE2 OUT st OE2 321st OE3 OUT nd OE3 322nd OE1 OUT rd OE1 323rd OE2 : : : : : OUT th OE1 479th OE2 OUT th OE2 480th OE3 -P.6-

8 5.4 Device power supply The HX8678-A must be used by the following conditions. - = 40V (max.) VSS = 7 ~ 35V Example: OUT1 to OUT480 VSS Logic input The input signal level of CPV, L/R, OE, STV1 and STV2 have to swing between and VSS. The signal output level of start pulse (STV1 or STV2) to the next stage cascaded device is for H and VSS for L. 5.5 Power ON/OFF sequence To prevent the device damage from latch up, the power ON/OFF sequence shown below must be followed. When power on: When power off: VSS -P.7-

9 6. DC Characteristics 6.1 Absolute Maximum Rating (VSS=0V) Parameter Symbol Rating Unit Power supply voltage (1) -0.3 to V Power supply voltage (2) -0.3 to +7.0 V Power supply voltage (3) -42 to +0.3 V Input voltage V IN -0.3 to +0.3 V Storage temperature T STG -55 to +125 Note: (1)All of the voltages listed above are with respective to VSS=0V. (2)Device is subject to be damaged permanently if stresses beyond those absolute maximum ratings listed above. 6.2 Recommended Operating Conditions (VSS=0V) Parameter Symbol Rating Min. Typ. Max. Unit Power supply voltage (1) V Power supply voltage (2) V Power supply voltage (3) V Power supply voltage (4) V Operation frequency F CPV KHz Operation temperature Ta Electrical Characteristics (VSS=0V) Parameter Symbol Condition Rating Application Unit Min. Typ. Max. pin Input H voltage V IH All input Input L voltage V IL - VSS All input V Output H voltage V OH I OH = 40µA STV1,2 Output L voltage V OL I OL = 40µA VSS - VSS+0.4 STV1,2 Output H resistance R OH V OUT = OUT0 ~ Ω -0.5V OUT481 Output L resistance R OL V OUT = OUT0 ~ Ω +0.5V OUT481 Input leakage current I IN µa Note (2) Pull high resistance R PU V IN =VSS kω /XAO Power I consumption Note (1) µa Power I consumption Note: (1)Power consumption with the following condition: Output no load, =20V, = -8V, =3.0V, V IH=, V IL=VSS, F CPV=50KHz, OE =V IL, /XAO=V IH. (2)All input except /XAO -P.8-

10 7. AC Characteristics Parameter Symbol Condition Spec Min. Typ. Max. CPV period t CPV CPV pulse width t CPVH, t CPVL 50% duty cycle OE pulse width t WOE /XAO pulse width t WXAO Data setup time t SU Data hold time t HD CPV to output delay time t PD1 CL=300pF Start pulse output delay time t PD2 CL=30pF OE to output delay time t PD3 CL=300pF /XAO to output delay time t PD4 CL=300pF Note: (1)The measurement point for all of above signals is at 50% of input/output amplitude. Unit µs -P.9-

11 8. Waveform t CPV t CPVH t CPVL CPV 50% t SU t HD STV1 50% t PD1 t PD1 OUT1 50% OUT2 ~ OUT480 t PD1 t PD1 50% CPV 50% OUT480 50% t PD2 t PD2 STV2 50% t WOE OE 50% OUT1 ~ OUT480 t PD3 t PD3 t PD4 t PD4 50% /XAO 50% t WXAO -P.10-

12 9. Pad Coordinate 9.1 HX8678-A Gate Driver Bump Location /XAO OE1 OE2 OE3 L/R CPV PATH STV2 MODE DUMMY OUT481 OUT Y (0,0) X VG H VG H VG H VG H OUT2 OUT1 OUT0 3 2 DUMMY /XAO OE1 OE2 OE3 L/R CPV PATH STV1 MODE MODE VSS VSS DUMMY DUMMY DUMMY DUMMY VSS VSS View from bump side MODE Chip size: 13530µm x 1047µm (scribe line included) Scribe line: 100µm -P.11-

13 9.2 Bump Outline Dimensions A5 A1 A2 A A3 484 x m2 x m4 m4 A4 C1 m2 m3 C2 30 x m1 x m m1 m7 Y (0,0) X 30 x m1 x m m1 C3 m6 C1 m B3 B1 D1 B4 B2 B5 m8 m10 m9 m5 B5 D1 m B3 23 x m6 x m5 71 x m8x m5 23 x m6 x m5 9.3 Alignment Mark Symbol Dimensions in µm Symbol Dimensions in µm A 715 C A1 75 D1 110 A2 65 m 50 A3 50 m1 45 A4 25 m2 84 A m3 119 B1 671 m4 25 B2 52 m5 85 B3 445 m6 40 B4 80 m7 609 B m8 105 C1 75 m9 30 C2 71 m (Scribe line included) Left 105um Right 105um 15um 15um 25um 25um 25um 105um 105um 25um 25um 25um 15um 15um 15um 25um 25um 25um 15um 15um 25um 25um 25um 15um -P.12-

14 9.4 Bump Center Coordinate No. Name X Y Bump size(µm) No. Name X Y Bump size(µm) 1 DUMMY x OUT x 84 2 OUT x OUT x 84 3 OUT x OUT x 84 4 OUT x OUT x 84 5 OUT x OUT x 84 6 OUT x OUT x 84 7 OUT x OUT x 84 8 OUT x OUT x 84 9 OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x 84 -P.13-

15 No. Name X Y Bump size(µm) No. Name X Y Bump size(µm) 121 OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x 84 -P.14-

16 No. Name X Y Bump size(µm) No. Name X Y Bump size(µm) 241 OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x 84 -P.15-

17 No. Name X Y Bump size(µm) No. Name X Y Bump size(µm) 361 OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x OUT x 84 -P.16-

18 No. Name X Y Bump size(µm) No. Name X Y Bump size(µm) 481 OUT x DUMMY x OUT x DUMMY x OUT x DUMMY x DUMMY x DUMMY x /XAO x DUMMY x /XAO x DUMMY x /XAO x DUMMY x /XAO x DUMMY x OE x DUMMY x OE x DUMMY x OE x DUMMY x OE x DUMMY x OE x DUMMY x OE x DUMMY x L/R x DUMMY x L/R x DUMMY x CPV x DUMMY x CPV x DUMMY x PASS x DUMMY x PASS x DUMMY x STV x DUMMY x STV x DUMMY x x DUMMY x x DUMMY x x DUMMY x x DUMMY x x DUMMY x x DUMMY x x DUMMY x x DUMMY x MODE x DUMMY x MODE x DUMMY x MODE x DUMMY x MODE x DUMMY x x DUMMY x x DUMMY x x DUMMY x x DUMMY x x DUMMY x x DUMMY x x DUMMY x x DUMMY x x DUMMY x x DUMMY x x DUMMY x x DUMMY x MODE x DUMMY x VSS x DUMMY x VSS x DUMMY x VSS x DUMMY x VSS x DUMMY x VSS x DUMMY x VSS x DUMMY x VSS x DUMMY x VSS x DUMMY x VSS x DUMMY x VSS x DUMMY x DUMMY x DUMMY x DUMMY x DUMMY x DUMMY x DUMMY x 85 -P.17-

19 No. Name X Y Bump size(µm) No. Name X Y Bump size(µm) 601 DUMMY x MODE x DUMMY x MODE x DUMMY x MODE x DUMMY x MODE x DUMMY x x DUMMY x x DUMMY x x DUMMY x x VSS x x VSS x x VSS x x VSS x x VSS x STV x VSS x STV x VSS x PASS x VSS x PASS x VSS x CPV x VSS x CPV x MODE x L/R x x L/R x x OE x x OE x x OE x x OE x x OE x x OE x x /XAO x x /XAO x x /XAO x x /XAO x x Alignment Mark center coordinate Name X Y L_AMK R_AMK P.18-

20 10. Ordering Information Part NO. HX8678-A000PDxxx Package PD: mean COG xxx: mean chip thickness (µm), (default 400 µm) 11. Revision History Version EFF.DATE DESCRIPTION OF CHANGES /05/11 New setup 2006/05/23 Page 11 Revise chip size. Page 12 Revise bmmp outline dimensions. 2006/07/05 Page 11~12 Revise the drawing of alignment mark. -P.19-

( DOC No. HX8678-B-DS )

( DOC No. HX8678-B-DS ) Preliminary version 01 1. General Description The HX8678-B is a 480-channel outputs gate driver, which is used for driving the gate line of TFT LCD panel. It is designed for 2-level