( DOC No. HX8705-B-DS ) HX8705-B

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1 ( DOC No. HX8705-B-DS ) HX8705-B 800x600CH EPD Source+Gate Driver Preliminary version 01

800x600CH EPD Source+Gate Driver Preliminary Version 01 1.

2 800x600CH EPD Source+Gate Driver Preliminary Version General Description The HX8705-B is a 800-channel outputs source driver and 600-channel outputs gate driver, which is used for driving the EPD panel. For source driver, it consists of a 800-bit long 2-bit wide shift register with 4-groups 2-bit wide input, a 800-bit long 2-bit wide latch, and a 800-channel 3 level-voltage driver. Each 2-bit wide data in the latch and the OE signal are decoded to 3 control signals. After level shifted, the control signals make the 3 level-voltage driver output VPOS, VNEG, or VSSA voltage. For gate driver, it is designed for 2-level gate output with 43V driving voltage range. The circuits are made of CMOS process, consuming low power. 2. Features 3-level source output 800 channel source outputs Maximum 25MHz source driver operation frequency Source driving voltage range: ±16V 4-group 2-bit wide data input 2-level gate output 600 channel gate outputs Maximum 200KHz gate driver operation frequency Gate driving voltage range: 43V Digital supply voltage:2.7v to 3.6V Bi-directional data shift capability High voltage CMOS process technology COG package -P.2-

3 3. Block Diagram VPOS VDD VSSA VNEG Level Shifter and Output Buffer Decoder Output Buffer VDD VSSD 800-bit long 2-bit wide Latch Level Shifter VGH VDD VSSD VGL 800-bit long 2-bit wide Bi-direction Shift Register Bi-direction Shift Register Input Buffer and Control Logic -P.3-

4 4. Pin Description Pin name I/O Function Description The clock for the source driver internal shift registers. CLK In Shift clock input CLK senses start pulse and captures data D[0:7] at its rising edge. This pin is internally pull down. D[0:7] In Display data input Shift register data input pins. These pins are pull down internally. The shift direction of device internal shift register is controlled by this pin as shown below: R/L In R/L=H, S797~S800 are the first data output, S1~S4 are Shift direction the 200 th data output control pin R/L=L, S1~S4 are the first data output, S797~S800 are the 200 th data output. This pin is pull down internally. STH is used for start pulse input R/L=H, S797~S800 are the first data output, S1~S4 are STH In Start pulse input pin the 200 th data output R/L=L, S1~S4 are the first data output, S797~S800 are the 200 th data output. LE In Latch enable Load shift register data into the latch when LE is high. This pin is pull down internally. OE In Output enable OE is asynchronous with CLK. When OE=H: Outputs are enabled. When OE=L: Outputs are forced to VSSA. This pin is pull down internally. S1~ Source driver According to the data in the latch and OE level, the output Out S800 output voltage is one of VPOS, VSSA, or VNEG CPV In Shift clock input The clock for the gate driver internal shift registers. The shift direction of device internal shift register is U/D In controlled by this pin as shown below: Shift direction U/D =H, STV G1 G2 G600 control pin U/D =L, STV G600 G2 G1 This pin is pull down internally. STV MODE2 MODE1 G1~ G600 In In Out Start pulse Input pin Gate output mode selection Driver output pins for driving gate electrode of EPD STV is used for start pulse input Gate output mode selection Output mode MODE2 MODE1 One pulse mode H H Continuous double pulse mode H L Jumping double pulse mode L H Fixed to VGL L L The output voltage is either VGH or VGL for driving the gate electrode of EPD panel depending on the data stored in shift register and the state of CPV. VPOS In Power supply Power supply for positive source drive output VNEG In Power supply Power supply for negative source drive output VDD In Power supply Logic power VSSD In Power supply Logic ground -P.4-

5 Pin name I/O Function Description Analog ground for driver output. VSSA In Power supply Don t short VSSA with VSSD by ITO on EPD panel. Connect it to VSSD on PCB or FPC. VGH In Power supply Power supply for gate drive output high VGL In Power supply Power supply for gate drive output low TEST1 Test pin Please keep this pin floating -P.5-

6 5. Function Description 5.1 Device operation Source Block operation HX8705-B is a 800-channel outputs source driver used for driving the source electrodes of an EPD panel. It consists of a 800-bit long 2-bit wide shift register with 4-groups 2-bit wide input, a 800-bit long 2-bit wide latch, and a 800-channel 3 level-voltage driver. Each 2-bit wide data in the latch and the OE signal are decoded to 3 control signals. After level shifted, the control signals make the 3 level-voltage driver output VPOS, VNEG, or VSSA voltage When R/L=H, the device start pulse input pin STH is sensed at CLK rising edge which makes the internal shift register enabled. At first CLK rising edge, first data D[0:7] stored in the 797 st ~800 th latch circuit. When 200 th CLK rising edge, data D[0:7] stored in the 1 st ~4 th latch circuit. LE controls the 800-bit long 2-bit wide latch. It loads the data in the shift register data into the latch when it is high, and the driver output starts to change its output according to the data in the latch. R/L pin decides the shift direction of the shift register. When R/L is high, S797~S800 are the first data output,. When R/L is low, S1~S4 are the first data output. Chip enable pin OE is asynchronous to the clock CLK. When OE is high, outputs enabled. When OE is low, outputs forced to VSSA level. However, the data of the shift register is not cleared even if OE is low. Each source driver output pin is switched to one of [VSSA, VPOS, VNEG] according to the data in the latch and OE level. To maintain VNEG at a safe voltage when the supply is turned off, an external schottky diode from VNEG to VSSA may be required. -P.6-

7 Driver Output Control OE D[2n+1] D[2n] OUT[n+1+4K] H L L VSSA H L H VPOS H H L VNEG H H H VSSA L X X VSSA Note: n = 0 to 3, k = 0 to 199 Latch Block LE H L Data in 800-bit long 2-bit wide latch Load data into latch from shifter register Hold latch data Shift Register Block R/L = H First data: D[1:0]-> S797 D[3:2]-> S798 D[5:4]-> S799 D[7:6]-> S th data: D[1:0]-> S1 D[3:2]-> S2 D[5:4]-> S3 D[7:6]-> S Gate Block operation First data: D[1:0]-> S1 D[3:2]-> S2 D[5:4]-> S3 D[7:6]-> S4 200 th data: D[1:0]-> S797 D[3:2]-> S798 D[5:4]-> S799 D[7:6]-> S800 R/L = L When U/D=H, the STV start pulse input is sensed on the rising edge of CPV and stored in the first stage of shift register at the 3 rd /4 th /5 th rising edge of CPV which are corresponding to jumping double pulse mode, continuous double pulse mode, or one pulse mode respectively. The stored data is inverted and logic AND operation with CPV. Then, it is level shifted and output from the OUT1 pin. While stored data is transferred to the next stage shift register on the every rising edge of CPV, new data of STV is sensed simultaneously. The output pin (G1 to G600) supplies VGH voltage or VGL voltage to the EPD panel depending on the data stored in the shift register and CPV level. For normal operation, a VGH voltage is outputted one by one from G1 to G600 in synchronization with CPV pulse. -P.7-

8 Example of input/output timing (U/D=H, MODE2=H, MODE1=H) CPV STV G1 G2 G3 G596 G597 G598 G599 G Example of input/output timing (U/D=L, MODE2=H, MODE1=H) CPV STV G600 G599 G598 G5 G4 G3 G2 G P.8-

9 Example of input/output timing (U/D=H, MODE2= H, MODE1= L) CPV STV G1 G2 G3 G596 G597 G598 G599 G Example of input/output timing (U/D=L, MODE2=H, MODE1=L) CPV STV G600 G599 G598 G5 G4 G3 G2 G P.9-

10 Example of input/output timing (U/D=H, MODE2=L, MODE1=H) CPV STV G1 G2 G3 G596 G597 G598 G599 G Example of input/output timing (U/D=L, MODE2=L, MODE1= H) CPV STV G600 G599 G598 G5 G4 G3 G2 G P.10-

11 5.2 Power level VGH VPOS VDD VSSD VNEG VGL Logic level S1 to S800 G1 to G600 The logic levels of CLK, D[0:7[, R/L, STH, LE, OE, CPV, U/D, MODE1, MODE2 and STV have to swing between VDD for H and VSSD for L. 5.3 Power on/off sequence To prevent the device from damage due to latch up, the power on/off sequence shown below must be followed. To avoid possible power off noise, below power off sequence must be followed. According to the RC loading of the display, an adequate delay time help to make sure that the display can discharge completely. When power on: VDD=>VGL=> VNEG/VPOS/VGH=>OE When power off: OE=> VPOS/VGH/VNEG=> VGL=> VDD VPOS/VGH VSSD/VSSA VDD OE VGL VNEG VPOS Source output VNEG delay time VSSA -P.11-

12 6. DC Characteristics 6.1 Absolute maximum rating (VSSD=VSSA=0V) Parameter Symbol Spec. Min. Typ. Max. Unit Power supply voltage 1 VPOS V Power supply voltage 2 VNEG V Power supply voltage 3 VGH V Power supply voltage 4 VDD V Power supply voltage 5 VGL VGH V Input voltage V IN VDD+0.3 V Storage temperature T STG Note: Device will probably be damaged permanently in case that the stresses are over the absolute maximum ratings listed above. 6.2 Recommended operating conditions (VSSD=VSSA=0V) Parameter Symbol Spec. Min. Typ. Max. Unit Power supply voltage 1 VPOS V Power supply voltage 2 VNEG V Power supply voltage 3 VGH 10 - VGL+43 V Power supply voltage 4 VDD V Power supply voltage 5 VGL V Power supply voltage 6 VGH -VGL V Power supply voltage 7 VNEG -VGL 0-10 V Operation frequency F CLK MHz Operation frequency F CPV KHz Operation temperature T A DC Electrical characteristics (VSSD=VSSA=0V) (VDD=2.7~3.6V, VPOS=15V, VNEG=-15V, VGH=20V, VGL=-20V, TA=25º, VSSD=VSSA=0V Parameter Spec. Symbol Applicable Condition pin Min. Typ. Max. Unit Input H voltage V IH All input - 0.7VDD - VDD V Input L voltage V IL All input VDD V Input leakage current I IN Note (1) µa Pull low resistance R Pl Note (2) V IN =VDD kω Output resistance R ON S1~S800 VPOS=15V, VNEG=-15V, KΩ I OUT =1mA Output H resistance R ONH G1 ~ G600 V OUT = VGH-0.5V Ω Output L resistance R ONL G1 ~ G600 V OUT = VGL+0.5V Ω VDD static current I DD, static - V IN =0V µa VPOS static current I POS, static - V IN =0V µa VNEG static current I NEG, static - V IN =0V µa -P.12-

13 Parameter VDD operation current VPOS operation current Symbol Applicable pin Condition Spec. Min. Typ. Max. Unit I DD, AC - VDD = 3V, F CLK =20MHz, V IH =VDD, V IL = ma I POS, AC - C LOAD =100pF, VPOS=15V, ma VNEG=-15V, I NEG, AC - t LINE =25us, DC VCOM ma No load VNEG operation current VGH operation current I VGH, AC - VDD = 3V, VGH=20V, VGL operation current I VDD, AC - VGL=-20V, F CPV =50KHz, Note: (1) ll input except for pull low pins (2) LK, D[0:7], R/L, LE, OE, U/D µa -P.13-

14 7. AC Characteristics Spec. Parameter Symbol Condition Unit Min. Typ. Max. CLK period PW CLK ns CLK pulse width PW CLKH, PW CLKL ns D[0:7], STH setup time t SU ns D[0:7], STH hold time t HD ns LE high-level pulse width PW LE ns LE on delay time t PD ns LE off delay time t PD ns R/L setup time t SU ns R/L hold time t HD ns Output settle time to ±30mV t OUT C LOAD =50pF us CPV period t CPV µs CPV pulse width t CPVH, t CPVL 50% duty cycle µs STV setup time t SU µs STV hold time t HD µs CPV to output delay time t PD3 CL=300pF µs Note: The measurement point for all of above signals is at 50% of input/output amplitude. VDD=2.7V~3.6V, VPOS=15V, VNEG=-15V, VGH=20V, VGL=-10V, VSSD=VSSA=0V, T A=25, -P.14-

15 8. Waveform PWCLK PWCLKH PWCLKL CLK t SU1 t HD1 D0~D7 STH 201th rising edge after STH low First rising edge after STH low CLK STH tpd1 PWLE tpd2 LE tsu2 t HD2 R/L tout Sn t CPV tcpvh t CPVL CPV STV tsu3 thd3 CPV G1 tpd3 tpd3 G2~600 tpd3 tpd3 -P.15-

16 1 HX8705-B 9. Pad Coordinates 9.1 HX8705-B bump location & outline dimensions Bump hardness: 60Hv + 15Hv Bump height: 15 ±3µm Scribe line: 80µm Output pitch: 15um Chip size: 21702µm x 1112µm (scribe line included) DUM1 DUM2 DUM3 DUM52 DUM53 DUM54 VGL VGL VGL VGL VGH VGH VGH VGH VSSA VSSA VSSA VSSA DUM55 VNEG VNEG VNEG VNEG DUM56 VPOS VPOS VPOS VPOS DUM57 VSSD VSSD VSSD VSSD VDD VDD VDD VDD DUM58 TEST1 TEST1 DUM59 MODE2 MODE2 MODE1 MODE1 UD UD CPV CPV STV STV CPV CPV DUM60 CLK CLK LE LE OE OE RL RL STH STH D0 D0 DUM61 D1 D1 DUM62 D2 D2 DUM63 D3 D3 DUM64 D4 D4 DUM65 D5 D5 DUM66 D6 D6 DUM67 D7 D7 DUM68 CLK CLK DUM69 STH STH DUM70 LE LE DUM71 OE OE DUM72 RL RL DUM73 DUM99 DUM100 VDD VDD VDD VDD VSSD VSSD VSSD VSSD DUM101 VPOS VPOS VPOS VPOS DUM102 VNEG VNEG VNEG VNEG DUM103 VSSA VSSA VSSA VSSA VGH VGH VGH VGH VGL VGL VGL VGL DUM104 DUM105 DUM106 DUM155 DUM156 DUM (0,0) X Y DUM177 DUM176 S1 S3 S797 S799 DUM175 DUM174 DUM173 DUM172 DUM171 DUM170 DUM169 DUM168 G1 G2 G599 G600 DUM167 DUM166 DUM165 DUM164 DUM163 DUM162 DUM161 DUM160 S800 S798 S4 S2 DUM159 DUM (0,0) X 101 Y P.16-

17 9.2 Alignment mark 30um Left 30um 30um Right 30um 90um 30um 30um 30um 30um -P.17-

18 9.3 Bump center coordinates No. Name X Y Bump size(µm) No. Name X Y Bump size(µm) 1 DUM X VGH X120 2 DUM X VGH X120 3 DUM X VSSA X120 4 DUM X VSSA X120 5 DUM X VSSA X120 6 DUM X VSSA X120 7 DUM X DUM X120 8 DUM X VNEG X120 9 DUM X VNEG X DUM X VNEG X DUM X VNEG X DUM X DUM X DUM X VPOS X DUM X VPOS X DUM X VPOS X DUM X VPOS X DUM X DUM X DUM X VSSD X DUM X VSSD X DUM X VSSD X DUM X VSSD X DUM X VDD X DUM X VDD X DUM X VDD X DUM X VDD X DUM X DUM X DUM X TEST X DUM X TEST X DUM X DUM X DUM X MODE X DUM X MODE X DUM X MODE X DUM X MODE X DUM X UD X DUM X UD X DUM X CPV X DUM X CPV X DUM X STV X DUM X STV X DUM X CPV X DUM X CPV X DUM X DUM X DUM X CLK X DUM X CLK X DUM X LE X DUM X LE X DUM X OE X DUM X OE X DUM X RL X DUM X RL X DUM X STH X DUM X STH X DUM X D X DUM X D X VGL X DUM X VGL X D X VGL X D X VGL X DUM X VGH X D X VGH X D X120 -P.18-

19 No. Name X Y Bump size(µm) No. Name X Y Bump size(µm) 121 DUM X VDD X D X VDD X D X VSSD X DUM X VSSD X D X VSSD X D X VSSD X DUM X DUM X D X VPOS X D X VPOS X DUM X VPOS X D X VPOS X D X DUM X DUM X VNEG X D X VNEG X D X VNEG X DUM X VNEG X CLK X DUM X CLK X VSSA X DUM X VSSA X STH X VSSA X STH X VSSA X DUM X VGH X LE X VGH X LE X VGH X DUM X VGH X OE X VGL X OE X VGL X DUM X VGL X RL X VGL X RL X DUM X DUM X DUM X DUM X DUM X DUM X DUM X DUM X DUM X DUM X DUM X DUM X DUM X DUM X DUM X DUM X DUM X DUM X DUM X DUM X DUM X DUM X DUM X DUM X DUM X DUM X DUM X DUM X DUM X DUM X DUM X DUM X DUM X DUM X DUM X DUM X DUM X DUM X DUM X DUM X DUM X DUM X DUM X DUM X DUM X DUM X DUM X DUM X DUM X DUM X DUM X DUM X DUM X DUM X DUM X DUM X DUM X VDD X DUM X VDD X DUM X120 -P.19-

20 No. Name X Y Bump size(µm) No. Name X Y Bump size(µm) 241 DUM X S X DUM X S X DUM X S X DUM X S X DUM X S X DUM X S X DUM X S X DUM X S X DUM X S X DUM X S X DUM X S X DUM X S X DUM X S X DUM X S X DUM X S X DUM X S X DUM X S X DUM X S X DUM X S X DUM X S X DUM X S X DUM X S X DUM X S X DUM X S X DUM X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X120 -P.20-

21 No. Name X Y Bump size(µm) No. Name X Y Bump size(µm) 361 S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X120 -P.21-

22 No. Name X Y Bump size(µm) No. Name X Y Bump size(µm) 481 S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X120 -P.22-

23 No. Name X Y Bump size(µm) No. Name X Y Bump size(µm) 601 S X S X S X S X S X S X S X S X S X S X S X DUM X S X DUM X S X DUM X S X DUM X S X DUM X S X DUM X S X DUM X S X DUM X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X120 -P.23-

24 No. Name X Y Bump size(µm) No. Name X Y Bump size(µm) 721 G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X120 -P.24-

25 No. Name X Y Bump size(µm) No. Name X Y Bump size(µm) 841 G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X120 -P.25-

26 No. Name X Y Bump size(µm) No. Name X Y Bump size(µm) 961 G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X120 -P.26-

27 No. Name X Y Bump size(µm) No. Name X Y Bump size(µm) 1081 G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X120 -P.27-

28 No. Name X Y Bump size(µm) No. Name X Y Bump size(µm) 1201 G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X G X DUM X G X DUM X G X DUM X G X DUM X G X DUM X G X DUM X G X DUM X G X DUM X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X G X S X120 -P.28-

29 No. Name X Y Bump size(µm) No. Name X Y Bump size(µm) 1321 S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X S X120 -P.29-

( DOC No. HX8678-B-DS )

( DOC No. HX8678-B-DS ) Preliminary version 01 1. General Description The HX8678-B is a 480-channel outputs gate driver, which is used for driving the gate line of TFT LCD panel. It is designed for 2-level