NC7SVL08 TinyLogic Low-I CCT Two-Input AND Gate

Transcription

1 NC7SL08 TinyLogic Low-I CCT Two-Input ND Gate Features 0.9 to 3.6 CC Supply Operation 3.6 Over-oltage Tolerant I/Os at CC from 0.9 to 3.6 Power-Off High-Impedance Inputs and Outputs Proprietary Quiet Series Noise / EMI Reduction Circuitry Ultra-Small MicroPak Packages Ultra-Low Dynamic Power Description December 2010 The NC7SL08 is a single two-input ND gate with a low-i CCT input design from Fairchild s Ultra-Low Power (ULP-) series of TinyLogic. The NC7SL08 features very low quiescent current, even when the input voltage is lower than the CC supply. This feature services mobile handset applications very well, allowing for direct interface with baseband processor general-purpose I/Os. Since mobile devices rely on a battery supply, the NC7SL08 facilitates lower power consumption in mixed-voltage rail environments. This product is designed on an advanced CMOS technology for a wide low-voltage operating range (0.9 to 3.6 CC), high drive needs (up to 24m), and speed (maximum propagation delay of 3.5ns, CC=3.3). It achieves this performance while maintaining low CMOS power dissipation. Ordering Information Part Number Top Mark Package Packing Method NC7SL08P5X L08 5-Lead SC70, EIJ SC-88a, 1.25mm Wide NC7SL08L CE 6-Lead MicroPak, 1.00mm Wide NC7SL08FHX CE 6-Lead, MicroPak2, 1x1mm Body,.35mm Pitch 3000 Units on Tape & Reel 5000 Units on Tape & Reel 5000 Units on Tape & Reel NC7SL08 Rev

2 Connection Diagrams IEEE/IEC Pin Configurations GND B CC 3 4 B & Y Figure 1. Logic Symbol B Y GND Figure 2. SC70 (Top iew) Figure 3. MicroPak (Top Through iew) CC NC Y Pin Definitions Pin # SC70 Pin # MicroPak Name Description 1 1 Input 2 2 B Input 3 3 GND Ground 4 4 Y Output 5 NC No Connect 5 6 CC Supply oltage Function Table Y = B Inputs Output B Y L L L L H L H L L H H H L = Low Logic Level H = High Logic Level NC7SL08 Rev

3 bsolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit CC Supply oltage IN DC Input oltage OUT DC Output oltage HIGH or LOW State (1) -0.5 CC to +0.5 CC= I IK DC Input Diode Current IN < 0-50 m I OK DC Output Diode Current OUT < 0-50 OUT > CC +50 I OH / I OL DC Output Source/Sink Current ±50 m I CC or I GND DC CC or Ground Current per Supply Pin ±50 m T STG Storage Temperature Range C T J Junction Temperature Under Bias +150 C T L Junction Lead Temperature (Soldering, 10 Seconds) +260 C P D ESD Power Dissipation at +85 C SC MicroPak MicroPak Human Body Model JEDEC: JESD Charged Device Model JEDEC: JESD22-C Note: 1. The I O maximum rating must be observed. m mw Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to bsolute Maximum Ratings. Symbol Parameter Conditions Min. Max. Unit CC Supply oltage IN Input oltage (2) OUT I OH / I OL Output oltage Output Current in I OH / I OL HIGH or LOW State 0 CC CC= CC=3.0 to 3.6 ±24.0 CC=2.3 to 2.7 ±18.0 CC=1.65 to 1.95 ±6.0 CC=1.40 to 1.60 ±4.0 CC=1.10 to 1.30 ±2.0 CC=0.9 ±0.1 µ T Free ir Operating Temperature C Δt / Δ Minimum Input Edge Rate IN=0.8 to 2.0, CC= ns/ SC θ J Thermal Resistance MicroPak MicroPak Note: 2. Unused inputs must be held HIGH or LOW. They may not float. m C/W NC7SL08 Rev

4 DC Electrical Characteristics Symbol Parameter CC Conditions IH IL OH OL I IN I OFF I CC I CCT HIGH Level Input oltage LOW Level Input oltage HIGH Level Output oltage LOW Level Output oltage Input Leakage Current Power Off Leakage Current Quiescent Supply Current Increase in I CC per Input T =25 C T =-40 to 85 C Min. Max. Min. Max x CC 0.65 x CC 1.10 CC x CC 0.65 x CC 1.40 CC x CC 0.65 x CC 1.65 CC CC CC x CC 0.25 x CC 1.10 CC x CC 0.25 x CC 1.40 CC x CC 0.25 x CC 1.65 CC x CC 0.25 x CC 2.30 CC CC CC CC CC 1.30 CC CC CC 1.60 CC CC I OH=-100µ 1.65 CC 1.95 CC CC CC 2.70 CC CC CC 3.60 CC CC CC 1.30 I OH=-2m 0.75 x CC 0.75 x CC 1.40 CC 1.60 I OH=-4m 0.75 x CC 0.75 x CC 1.65 CC I OH=-6m 2.30 CC CC I OH=-12m 2.70 CC CC I OH=-18m 2.70 CC CC 3.60 I OH=-24m CC CC I OL=100µ 1.65 CC CC CC CC 1.30 I OL=2m 0.25 x CC 0.25 x CC 1.40 CC 1.60 I OL=4m 0.25 x CC 0.25 x CC 1.65 CC 1.95 I OL=6m CC I OL=12m 2.70 CC CC I OL=18m 2.70 CC CC 3.60 I OL=24m Units 0.90 to IN 3.6 ±0.1 ±0.5 µ to ( IN, O) µ IN= CC or GND CC IN 3.6 ± IN= IN= µ µ NC7SL08 Rev

5 C Electrical Characteristics Symbol Parameter CC Conditions t PHL, t PLH Propagation Delay T =25 C T =-40 to 85 C Units Figure Min. Typ. Max. Min. Max C L=15pF, R L=1MΩ CC 1.30 C L=15pF, CC 1.60 R L=2kΩ CC CC 2.70 C L=30pF, R L=500Ω CC C IN Input Capacitance 0 3 pf C PD Power Dissipation Capacitance 0.90 to 3.60 IN=0 or CC, f=10mhz ns 5 pf Figure 4, Figure 5 Figure 4. C Test Circuit Figure 5. C Waveforms Symbol CC 3.3 ± ± ± ± ± mi 1.5 CC / 2 CC / 2 CC / 2 CC / 2 CC / 2 mo 1.5 CC / 2 CC / 2 CC / 2 CC / 2 CC / 2 NC7SL08 Rev

6 Physical Dimensions Figure 6. 5-Lead, SC70, EIJ SC-88a, 1.25mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. lways visit Fairchild Semiconductor s online packaging area for the most recent package drawings: Tape and Reel Specifications Please visit Fairchild Semiconductor s online packaging area for the most recent tape and reel specifications: Package Designator Tape Section Cavity Number Cavity Status Cover Type Status P5X Leader (Start End) 125 (Typical) Empty Sealed Carrier 3000 Filled Sealed Trailer (Hub End) 75 (Typical) Empty Sealed NC7SL08 Rev

7 Physical Dimensions 2X 1.45 (0.254) TOP IEW PIN 1 IDENTIFIER MX C DETIL 1.0 B 2X (0.49) 5X (0.52) 1X PIN C B (1) (0.30) RECOMMENED LND PTTERN (0.75) X (0.05) 0.5 BOTTOM IEW X 45 CHMFER Notes: 1. CONFORMS TO JEDEC STNDRD M0-252 RITION UD 2. DIMENSIONS RE IN MILLIMETERS 3. DRWING CONFORMS TO SME Y14.5M FILENME ND REISION: MC06RE4 5. PIN ONE IDENTIFIER IS 2X LENGTH OF NY OTHER LINE IN THE MRK CODE LYOUT. DETIL PIN 1 TERMINL Figure 7. 6-Lead, MicroPak, 1.0mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. NC7SL08 Rev X (0.13) 4X lways visit Fairchild Semiconductor s online packaging area for the most recent package drawings: Tape and Reel Specifications Please visit Fairchild Semiconductor s online packaging area for the most recent tape and reel specifications: Package Designator Tape Section Cavity Number Cavity Status Cover Type Status L Leader (Start End) 125 (Typical) Empty Sealed Carrier 5000 Filled Sealed Trailer (Hub End) 75 (Typical) Empty Sealed

8 Physical Dimensions 2X 1.00 PIN 1 MIN 250uM TOP IEW C SIDE IEW (0.08) 4X DETIL B 0.55MX X 5X X X RECOMMENDED LND PTTERN FOR SPCE CONSTRINED PCB X LTERNTIE LND PTTERN FOR UNIERSL PPLICTION (0.05) 5X (0.08) 4X BOTTOM IEW NOTES:. COMPLIES TO JEDEC MO-252 STNDRD B. DIMENSIONS RE IN MILLIMETERS. C. DIMENSIONS ND TOLERNCES PER SME Y14.5M, 1994 D. LNDPTTERN RECOMMENDTION IS BSED ON FSC DESIGN. E. DRWING FILENME ND REISION: MGF06RE C B.05 C 0.075X45 CHMFER DETIL PIN 1 LED SCLE: 2X Figure 8. 6-Lead, MicroPak 2, 1x1mm Body,.35mm Pitch Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. lways visit Fairchild Semiconductor s online packaging area for the most recent package drawings: Tape and Reel Specifications Please visit Fairchild Semiconductor s online packaging area for the most recent tape and reel specifications: Package Designator Tape Section Cavity Number Cavity Status Cover Type Status FHX Leader (Start End) 125 (Typical) Empty Sealed Carrier 5000 Filled Sealed Trailer (Hub End) 75 (Typical) Empty Sealed NC7SL08 Rev

9 NC7SL08 Rev