CS 250! VLSI System Design

Transcription

1 CS 250! VLSI System Design Lecture 3 Timing ! Professor Jonathan Bachrach! slides by John Lazzaro TA: Colin Schmidt www-insteecsberkeleyedu/~cs250/ UC Regents Fall 2013/1014 UCB

2 everything doesn t happen at once Timing, the 10,000 ft view Locally synchronous, globally asynchronous On the same page Minimal set of timing concepts you need for project Break RTL Examples Better timing through micro-architecture Electrical details Just so you know UC Regents Fall 2013 UCB

3 Google I/O, 2012 View from 10,000 Ft

4 26 Billion Moore s Law 1 Million 2 Thousand Synchronous logic on a single clock domain is not practical for a 26 billion transistor design

5 GALS: Globally Asynchronous, Locally Synchronous Synchronous modules typically 50K-1M gates, so that the synchronous logic approach works well without requiring heroics Examples

6 IBM Power 5 CPU - Dynamically Scheduled CP = group commit) Branch prediction Program Branch Return Target counter history stack stack cache tables Alternate Instruction buffer 0 0 Group formation Instruction Instruction decode cache Instruction Dispatch Instruction buffer 1 1 translation Thread priority Dynamic instruction selection Shared Shared execution issue issue units units queues LSU0 FXU0 LSU1 FXU1 FPU0 FPU1 BXU BXU Sharedregister mappers Read Read sharedregister files files CRL CRL Write Write shared- register files files Data Data Translation Data Data Cache Group Store Store completion queue Data Data Data Data translation cache L2 L2 cache Shared by by two two threads Thread 0 0 resources Thread 1 1 resources Stars denote FIFOs that create separate synchronous domains An example of how architecture and circuits work together Figure 4 Power5 instruction data flow (BXU = branch execution unit and CRL = condition register logical execution unit)

7 Rocket uses GALS for accelerator interface Your project interfaces with the RISC-V pipeline and the memory system using FIFOs Your timing closure is independent of the CPU logic domain

8 Today: Timing insights for your project What we re not doing If this class was EE 241 and your project was an SRAM: You could see through down to the layout Timing? Use SPICE on this hand-drawn schematic

9 Technology X: The CS 250 timing challenge What we are doing ---> If your accelerator is too slow two options: Top-down: Rework high-level micro-architecture Let Technology X keep its job Today Logic Synthesis Bottom-up: Take control away from logic synthesis Use HDL as textual schematic Also, use command-line tool flags Sometimes necessary Colin is the expert, ask in discussion

10 A Logic Circuit Primer Models should be as simple as possible, but no simpler Albert Einstein UC Regents Fall 2013/1014 UCB

11 Inverters: A simple transistor model In Inverter Out Out = In Correctly predicts logic output for simple static CMOS circuits In 0 1 Out Circuit In 1 0 Vdd PMOS Out NMOS Extensions to model subtler circuit families, or to predict timing, have not worked well pfet! A switch On if gate is grounded nfet! A switch On if gate is! at Vdd UC Regents Fall 2013 UCB

12 Transistors as water valves (Cartoon physics) If electrons are water molecules,! transistor strengths (W/L) are pipe diameters,! and capacitors are buckets Vdd 1 A on p-fet fills! up the capacitor with charge Open Charge 0 Water level Time A on n-fet! empties the bucket n Vdd Open Vdd Out Discharge 1 This model is often good enough 0 Water level Time UC Regents Fall 2013/2014 UCB

13 What is the bucket? A gate s fan-out Inverter: NAND gate: Fan-out : The number of gate inputs driven by a gate s output Driving other gates slows a gate down Driving wires slows a gate down Driving it s own parasitics slows a gate down UC Regents Fall 2013 UCB

14 Fanout UC Regents Fall 2013 UCB

15 A closer look at fan-out Driving more gates adds delay Linear model! works for! reasonable! fan-out 05ns Out: Low -> High Slope = 00021ns / ff FO4: Fanout of four delay Delay time of an inverter driving 4 inverters Cout UC Regents Fall 2013 UCB

16 Propagation delay graphs Cascaded gates: 1 ->0 1 ->0 0 ->1 0 ->1 inverter transfer function Vout Vin UC Regents Fall 2013/2014 UCB

17 Worst-case delay through combinational logic T2 might be the worst-case delay path (critical path) 0 ->1 T2 0 ->1 T1 0 ->1 x = g(a, b, c, d, e, f) If d going 0-to-1 switches x 0-to-1, delay is T1 If a going 0-to-1 switches x 0-to-1, delay is T2 It would be surprising if T1 > T2 UC Regents Fall 2013/2014 UCB

18 Why might? Wires have delay too Wires posses distributed resistance and capacitance v1 v2 v3 v4 Looks! benign,! but Time constant associated with distributed RC is proportional to the square of the length v1 v2 v3 v4 time signals are typically rebuffered to reduce delay: UC Regents Fall 2013/2014 UCB

19 Clocked Logic Circuits UC Regents Fall 2013/1014 UCB

20 From Delay Models to Timing Analysis clk Timing Analysis!! What is the smallest T that produces correct operation? f T 1 MHz 1 μs 10 MHz 100 ns 100 MHz 10 ns 1 GHz 1 ns UC Regents Fall 2013/2014 UCB

21 Timing Analysis and Logic Delay Register:!! An Array of Flip-Flops Combinational Logic If our clock period T > worst-case delay through CL, does this ensure correct operation? UC Regents Fall 2013/2014 UCB

22 Flip Flops have internal delays D Q Value of D is sampled on positive clock edge Q outputs sampled value for rest of cycle t_setup CLK D Q t_clk-to-q UC Regents Fall 2013/2014 UCB

23 Flip-Flop delays eat into time budget Combinational Logic ALU time budget T! # clk"q + # CL + # setup UC Regents Fall 2013/2014 UCB

24 Clock skew also eats into time budget CLKd CLK CLK CLK CLKd CLK CL As T 0, which circuit fails first? CL CLK CLK CLKd clock skew, delay in distribution T " T CL +T setup +T clk!q + worst case skew ost modern large high-performance chi UC Regents Fall 2013/2014 UCB

25 Delay Grid Tuned sector trees Delay Sector buffers x Clock Tree! Delays,! IBM Power! CPU y Buffer level 2 Buffer level 1 UC Regents Fall 2013 UCB

26 15 10 Delay Volts (V) 20 ps skew Time (ps) Multiplefingered transmissio line x Clock Tree Delays, IBM Power y UC Regents Fall 2013 UCB

27 Some Flip Flops have hold time t_setup t_inv t_hold CLK D Q D D must! stay stable here What is the intended function of this circuit? CLK Does flip-flop hold time affect operation of this circuit? Under what conditions? t_clk-to-q + t_inv > t_hold For correct operation UC Regents Fall 2013/2014 UCB

28 Searching for processor critical path? Timing Analysis!! What is the smallest T that produces correct operation?!! Must consider! all connected! register pairs Why might I suspect this one? UC Regents Fall 2013/2014 UCB

29 Combinational paths for IBM Power 4 CPU The critical path Most wires have hundreds of picoseconds to spare Late-mode timing checks (thousands) Timing slack (ps) From The circuit and physical design of the POWER4 microprocessor, IBM J Res and Dev, 46:1, Jan 2002, JD Warnock et al UC Regents Fall 2013/2014 UCB

30 How to retime logic Circles are combinational logic, labelled with delays Critical path is 5 We want to improve it without changing circuit semantics IN OUT Figure 1: A small graph before retiming The nodes represent logic delays, with the inputs and outputs passing through mandatory, fixed registers The critical path is 5 Add a register, move one circle Performance improves by 20% Post-Placement C-slow Retiming for the Xilinx Virtex FPGA IN Nicholas Weaver UC Berkeley Berkeley, CA Yury Markovskiy UC Berkeley Berkeley, CA Yatish Patel UC Berkeley Berkeley, CA OUT Figure 2: The example in Figure 2 after retiming The critical path is reduced from 5 to 4 Technology X can often do this John Wawrzynek UC Berkeley Berkeley, CA

31 Power 4: Timing Estimation, Closure Timing Estimation!! Predicting a processor s clock rate early in the project From The circuit and physical design of the POWER4 microprocessor, IBM J Res and Dev, 46:1, Jan 2002, JD Warnock et al UC Regents Fall 2013/2014 UCB

32 Power 4: Timing Estimation, Closure Timing Closure!! Meeting! (or exceeding!) the timing estimate From The circuit and physical design of the POWER4 microprocessor, IBM J Res and Dev, 46:1, Jan 2002, JD Warnock et al UC Regents Fall 2013/2014 UCB

33 Floorplaning: essential to meet timing (Intel XScale 80200) UC Regents Fall 2013/2014 UCB

34

35 Break UC Regents Fall 2013/1014 UCB

36 Simple exercises for gaining intuition about timing for your process + EDA tools Thanks to Bhupesh Dasila, Open-Silicon Bangalore

37 Synthesize gate chains using hand-specified library cells Exercises cell library and place and route tools! Lets you know how many levels of logic you can use in the best case weak NANDs Synthesis constrained to 2ns clock Delay of a chain of 3 inverters with strongest strength Guaranteed not to exceed speed Chain lengths 40 nm process 29 ps/gate av Helps you see through Technology X Bhupesh Dasila

38 Force P&L to drive a long wire with a known buffer cell Bhupesh Dasila Vary driver strength, wire length, metal layer! Shows the maximum distance two gates can be placed and still meet your clock period Distributed RC is the square of the length is clearly seen!

39 Driving Large Loads Large fanout nets: clocks, resets, memory bit lines, off-chip Relatively small driver results in long rise time (and thus large gate delay) Strategy: Staged Buffers Optimal trade-off between delay per stage and total number of stages fanout of 4-6 per stage Lecture 04, Timing 12 UC Regents CS250, Fall 2013/1014 UC Berkeley Fall UCB 12

40 Register file: Synthesize, or use SRAM? sel(ws) 5 WE D E M U X clk wd R0 - The constant 0 Q 32 D D D En En En R1 R2 R31 Q Q Q Speed will depend on how large it lays out two read ports sel(rs1) M U X M U X 5 32 rd1 sel(rs2) 5 32 rd2 UC Regents Fall 2013/2014 UCB

41 Synthesized, custom, and SRAM-based register files, 40nm For small register files, logic synthesis is competitive! Not clear if the SRAM data points include area for register control, etc Synthesis SRAMS Register file compiler Figure 3: Using the raw area data, the physical implementation team can get a more accurate area estimation early in the RTL development stage for floorplanning purposes This shows an example of this graph for a 1-port, 32-bit-wide SRAM Bhupesh Dasila

42 Techniques UC Regents Fall 2013/1014 UCB

43 Pipelining UC Regents Fall 2013 UCB

44 + Starting point: A single-cycle processor Challenge: Speed up clock while keeping CPI == 1 Seconds Program Instructions Program Cycles Instruction Seconds Cycle 0x4 CPI == 1 This is good Slow This is bad D PC Q Addr Instr Mem Data RegFile rs1 rs2 rd1 ws rd2 wd WE op A L U 32 Data Memory Addr Dout Din WE MemToReg Ext UC Regents Fall 2013/2014 UCB

45 Reminder: How data flows after posedge PC Instr! Mem 0x4 + D Q Addr Data rs1 rs2 ws wd RegFile WE rd1 rd op Logic A L U 32 UC Regents Fall 2013/2014 UCB

46 Next posedge: Update state and repeat PC D Q 5 rs1 5 rs2 5 ws 32 wd RegFile WE rd1 rd UC Regents Fall 2013/2014 UCB

47 Observation: Logic idle most of cycle For most of cycle, ALU is either waiting for its inputs, or holding its output Ideal: a CPU architecture where each part is always working 0x4 + D PC Q Addr Instr Mem Data RegFile rs1 rs2 rd1 ws rd2 wd WE op A L U 32 Data Memory Addr Dout Din WE MemToReg Ext UC Regents Fall 2013/2014 UCB

48 Inspiration: Automobile assembly line Assembly line moves on a steady clock! Each station does the same task on each car The clock Merge station Car body shell Bolting station Car chassis UC Regents Fall 2013/2014 UCB

49 Inspiration: Automobile assembly line Simpler station tasks more cars per hour Simple tasks take less time, clock is faster UC Regents Fall 2013 UCB

50 Inspiration: Automobile assembly line Line speed limited by slowest task Most efficient if all tasks take same time to do UC Regents Fall 2013 UCB

51 Inspiration: Automobile assembly line Simpler tasks, complex car long line! These lines go 24 x 7, and rarely shut down UC Regents Fall 2013 UCB

52 Lessons from car assembly lines Faster line movement yields more cars per hour off the line Faster line movement requires more stages, each doing simpler tasks To maximize efficiency, all stages should take same amount of time! (if not, workers in fast stages are idle) Filling, flushing, and stalling assembly line are all bad news UC Regents Fall 2013/2014 UCB

53 Key Analogy: The instruction is the car Pipeline Stage #1 Stage #2 Stage #3 Stage #4 Stage #5 Instruction Fetch IR IR IR IR + PC 0x4 Instr Mem Controls hardware in stage 2 Controls hardware in stage 3 Controls hardware in stage 4 Controls hardware in stage 5 D Q Addr Data Data-stationary control UC Regents Fall 2013/2014 UCB

54 + Example: Decode & Register Fetch Stage Pipeline Stage #1 Stage #2 Stage #3 Instr Fetch Decode & Reg Fetch SUB R10,R9,R8 IR OR R7,R6,R5 IR ADD R4,R3,R2 IR 0x4 A sample program D PC Q Addr Instr Mem Data RegFile rs1 rs2 rd1 ws rd2 wd WE Ext A M B ADD R4,R3,R2 OR R7,R6,R5 SUB R10,R9,R8 R s chosen so that instructions are independent - like cars on the line UC Regents Fall 2013/2014 UCB

55 Hazards: An instruction is not a car + Stage #1 Stage #2 Stage #3 Instr Fetch Decode & Reg Fetch D PC Q 0x4 Addr Instr Mem Data OR R5,R4,R2 IR IR IR wrong value of R4 fetched from RegFile, contract with programmer broken! Oops! rs1 rs2 ws wd RegFile WE rd1 rd2 Ext A M B ADD R4,R3,R2 R4 not written yet New sample program ADD R4,R3,R2 OR R5,R4,R2 An example of a hazard -- we must (1) detect and (2) resolve all hazards to make a CPU that matches ISA UC Regents Fall 2013/2014 UCB

56 Performance Equation and Hazards + Seconds Program Instructions Program Cycles Instruction Seconds Cycle D PC Q Instr Fetch Decode & Reg Fetch Stage #3 IR IR IR Some ways to cope with hazards! Added logic to makes CPI > 1! detect and resolve 0x4 stalling pipeline hazards increases A clock period Addr Instr Mem Data rs1 rs2 ws wd RegFile WE rd1 rd2 Ext M B Software slows the machine down! Seymour Cray UC Regents Fall 2013/2014 UCB

57 Superpipelining UC Regents Fall 2013 UCB

58 Superpipelining: Add more stages Seconds Program Instructions Program Cycles Instruction Seconds Cycle Goal: Reduce critical path by! adding more pipeline stages Example: 8-stage ARM XScale:! extra IF, ID, data cache stages Difficulties: Added penalties for load delays and branch misses Also, power! Ultimate Limiter: As logic delay goes to 0, FF clk-to-q and setup UC Regents Fall 2013/2014 UCB

59 Note: Some stages now overlap, some instructions take extra stages 5 Stage 8 Stage IF ID+RF EX MEM WB IR IR IR IR IM Reg DM Reg ALU IF now takes 2 stages (pipelined I-cache) ID and RF each get a stage ALU split over 3 stages MEM takes 2 stages (pipelined D-cache) UC Regents Fall 2013/1014 UCB

60 Superpipelining techniques Split ALU and decode logic over several pipeline stages Pipeline memory: Use more banks of smaller arrays, add pipeline stages between decoders, muxes Remove rarely-used forwarding networks that are on critical path Creates stalls, affects CPI Pipeline the wires of frequently used forwarding networks Also: Clocking tricks (example: use posedge and negedge registers) UC Regents Fall 2013 UCB

61 Hardware limits to superpipelining? FO4! Delays Historical limit: about 12 FO4s MIPS stages CPU Clock Periods! Pentium Pro 10 stages FO4: How many fanout-of-4 inverter delays in the clock period Pentium 4 20 stages Thanks to Francois Labonte, Stanford * intel 386 intel 486 intel pentium intel pentium 2 intel pentium 3 intel pentium 4 intel itanium Alpha Alpha Alpha Sparc SuperSparc Sparc64 Mips HP PA Power PC AMD K6 AMD K7 AMD x86-64 Power wall: Intel Core Duo has 14 stages UC Regents Fall 2013/2014 UCB

62 CPU DB: Recording Microprocessor History With this open database, you can mine microprocessor trends over the past 40 years Andrew Danowitz, Kyle Kelley, James Mao, John P Stevenson, Mark Horowitz, Stanford University F04 Delays Per Cycle for Processor Designs F04 / cycle FO4 delay per cycle is roughly proportional to the amount of computation completed per cycle

63 Multithreading UC Regents Fall 2013 UCB

64 Multithreading of Static Pipelines Interleave 4 threads, T1-T4, on non-bypassed 5-stage pipe T1: LW r1, 0(r2) T2: ADD r7, r1, r4 T3: XORI r5, r4, #12 T4: SW 0(r7), r5 T1: LW r5, 12(r1) t0 t1 t2 t3 t4 t5 t6 t7 t8 F D X M W F D X M W F D X M W F D X M W F D X M W t9 Last instruction in a thread always completes writeback before next instruction in same thread reads regfile 4 CPUs, each run at 1/4 clock PC PC PC 1 PC I$ IR GPR1 GPR1 GPR1 GPR1 X Y D$ +1 2 Thread 2 Many variants UC Regents Fall 2013/2014 UCB

65 At the logic level Synchronous logic we want to multithread Critical path is 5 2X multi-threading: double each register Modern synthesis will retime this as shown: critical path is now 2 IN OUT Figure 1: A small graph before retiming The nodes represent logic delays, with the inputs and outputs passing through mandatory, fixed registers The critical path is 5 IN OUT Figure 3: The example in Figure 2 2-slowed This design now operates on 2 independent data streams IN OUT Figure 4: The example in Figure 3 after retiming The combination of C-slowing and retiming reduced the critical path from 5 to 2 Post-Placement C-slow Retiming for the Xilinx Virtex FPGA Nicholas Weaver UC Berkeley Berkeley, CA Yury Markovskiy UC Berkeley Berkeley, CA Yatish Patel UC Berkeley Berkeley, CA John Wawrzynek UC Berkeley Berkeley, CA

66 Good fit for GALS Two input queues (red and green) The mux control logic implements turn-taking Outputs placed into two output queues

67 Electrical Details UC Regents Fall 2013/1014 UCB

68 Flip Flops Revisited UC Regents Fall 2013 UCB

69 Recall: Static RAM cell (6 Transistors) Gnd Vdd Vth Vth Vdd Gnd Crosscoupled inverters noise noise x x! UC Regents Fall 2013/2014 UCB

70 Recall: Positive edge-triggered flip-flop D Q A flip-flop samples right before the edge, and then holds value clk Sampling! circuit clk Holds! value clk clk clk clk clk Clock to Q delay results fr 16 Transistors: Makes an SRAM look compact! What do we get for the 10 extra transistors? Clocked logic semantics clk UC Regents Fall 2013/2014 UCB

71 Sensing: When clock is low D Q clk A flip-flop samples right before the edge, and then holds value Sampling! circuit clk Holds! value clk clk clk clk clk = 0 clk = 1 clk clk Clock to Q delay results fr clk clk clk clk clk clk Will capture clk new value on posedge Clock to Q delay results fr Outputs clk last value captured UC Regents Fall 2013/2014 UCB

72 Capture: When clock goes high D Q clk A flip-flop samples right before the edge, and then holds value Sampling! circuit clk Holds! value clk clk clk clk clk = 1 clk = 0 clk Clock to clk Q delay results fr clk clk clk clk clk clk Remembers value clk just captured Clock to Q delay results fr Outputs value clk just captured UC Regents Fall 2013/2014 UCB

73 Flip Flop delays: clk-to-q? setup? hold? clk clk D Q CLK clk clk clk clk CLK == 0 Sense D, but Q! outputs old value clk Clock to Q delay results fr setup clk CLK 0->1 Capture D, pass! value to Q hold clk-to-q UC Regents Fall 2013/2014 UCB

74 On Tuesday Power and Energy Heat Sink Heat Source