Drowsy Caches Simple Techniques for Reducing Leakage Power Krisztián Flautner Nam Sung Kim Steve Martin David Blaauw Trevor Mudge

Transcription

1 Drowsy Caches Simple Techniques for Reducing Leakage Power Krisztián Flautner Nam Sung Kim Steve Martin David Blaauw Trevor Mudge 1

2 Motivation! Ever increasing leakage power " as feature size shrinks ! V t scales down " exponential increase in leakage power Normalized leakage power º C 75 ºC 50 ºC 25 ºC! On-chip caches " responsible for 15%~20% of the total power " leakage power can exceed 50% of total cache power Minimum gate length (µm) according to our projection using Berkeley Predictive Models

3 Processor power trends Power Consumption (W) Leakage Power Dynamic Power Pentium II Pentium III Pentium 4 One Gen Two Gen Three Gen Processor Generation Based on ITRS roadmap and transistor count estimates. Total power in this projection cannot come true. 3

4 An observation about data caches! L1 data caches Working set: fraction of cache lines accessed in a time window. Window size = 2000 cycles. Only a small fraction of lines are accessed in a window. 50% 40% Working set of current + 1, 8, and 32 previous windows 30% Working set of current window 20% 10% 0% crafty vortex bzip vpr mcf parser gcc facerec equake mesa 4

5 The Drowsy Cache approach Instead of being sophisticated about predicting the working set, reduce the penalty for being wrong. Algorithm: Periodically put all lines in cache into drowsy mode. When accessed, wake up the line. Optimize across circuit-microarchitecture boundary: Use of the appropriate circuit technique enables simplified microarchitectural control. Requirement: state preservation in low leakage mode. 5

6 Access control flow Awake tags Awake tags Hit Awake tag match Line wake up Line access Miss Awake tag miss Line wake up Replacement Memory Drowsy hit / miss adds at most 1 cycle latency Access to awake line is not penalized 6

7 Access control flow Drowsy tags Drowsy tags Hit Awake tag match Tag wake up Line wake up Line access Miss Awake tag miss Tag wake up Line wake up Replacement Memory Unneeded tags and lines back to drowsy Drowsy tags implementation is more complicated Is the complexity worth it? Tags use about 7% of data bits (32 bit address) Only small incremental leakage reduction Worst case: 3 cycle extra latency 7

8 Low-leakage circuit techniques Circuit Pros Cons Gated-V DD Largest leakage reduction Fast mode switching Easy implementation Loses cell state ABB-MTCMOS Retains cell state Slow mode switching DVS Retains cell state Fase mode switching More power reduction than ABB More SEU noise susceptible 8

9 Drowsy memory using DVS Low supply voltage for inactive memory cells Low voltage reduces leakage current too! Quadratic reduction in leakage power P = I I V supply voltage for normal mode leakage path supply voltage for drowsy mode 9

10 Leakage reduction using DVS High-V t devices for access transistors! reduce leakage power! increase access time of cache 100% 0.2V! Right Trade-off point Performance 95% 90% 0.25V 0.3V " 91% leakage reduction " 6% cycle time increase 0.35V 85% Projections for 0.07µm process 76% 78% 80% 82% 84% 86% 88% 90% 92% 94% Leakage reduction 10

11 Drowsy cache line architecture drowsy bit voltage controller drowsy (set) drowsy power line row decoder word line driver VDD (1V) VDDLow (0.3V) drowsy SRAMs word line wake up (reset) drowsy signal word line word line gate 11

12 Energy reduction 100% 80% 60% Leakage 40% 20% Dynamic Drow sy Drowsy High leakage Dynamic 0% Regular Cache Drowsy Cache Projections for 0.07µm process High leakage: lines have to be powered up when accessed. Drowsy circuit Without high v t device (in SRAM): 6x leakage reduction, no access delay. With high v t device: 10x leakage reduction, 6% access time increase. 12

13 1 cycle vs. 2 cycle wake up 100% 95% 90% Drowsy fraction 85% 80% 75% 1 cycle vs. 2 cycle wakup simple policy, awake tags, 4000 cycle window ammp00 apsi00 bzip200 eon00 facerec00 galgel00 gcc00 lucas00 mesa00 parser00 swim00 vortex00 wupwise00 applu00 art00 crafty00 equake00 fma3d00 gap00 gzip00 mcf00 mgrid00 sixtrack00 twolf00 vpr00 70% 0.00% 0.20% 0.40% 0.60% 0.80% 1.00% 1.20% 1.40% 1.60% 1.80% 2.00% 2.20% Run-time increase Fast wakeup is important but easy to accomplish! Cache access time: 0.57ns (for 0.07µm from CACTI using 0.18µm baseline). Speed dependent on voltage controller size: 64 x L eff 0.28ns (half cycle at 4 GHz), 32 x L eff 0.42ns, 16 x L eff 0.77ns. Impact of drowsy tags are quite similar to double-cycle wake up. 13

14 Policy comparison 100% lucas 95% facerec gcc twolf gzip parser simple 2000 Drowsy fraction 90% 85% 80% 75% vortex gap sixtrack eon crafty galgel applu mgrid art 70% 0.00% 0.20% 0.40% 0.60% 0.80% 1.00% 1.20% 1.40% Run-time increase simple 4000 noaccess vs. simple policy noaccess cycle wakeup, awake tags, simple policy: 2000 and 4000 cycle window, noaccess policy: 2000 cycle window ammp00 apsi00 bzip200 eon00 facerec00 galgel00 gcc00 lucas00 mesa00 parser00 swim00 vortex00 wupwise00 applu00 art00 crafty00 equake00 fma3d00 gap00 gzip00 mcf00 mgrid00 sixtrack00 twolf00 vpr00 14

15 Energy reduction Normalized Total Energy DVS Theoretical min. Normalized Leakage Energy DVS Theoretical min. Run-time increase Awake tags % Drowsy tags % > 50% total energy reduction > 70% leakage energy reduction Theoretical minimum assumes zero leakage in drowsy mode Total energy reduction within 0.1 of theoretical minimum Diminishing returns for better leakage reduction techniques Above figures assume 6x leakage reduction, 10x possible with small additional run-time impact 15

16 Conclusions Simple circuit technique Need high-v t transistors, low V dd supply Simple architecture No need to keep counter/predictor state for each line Periodic global counter asserts drowsy signal Window size (for periodic drowsy transition) depends on core: ~4000 cycles has good E-delay trade-off Technique also works well on in-order procesors Memory subsystem is already latency tolerant Drowsy circuit is good enough Diminishing returns on further leakage reduction Focus is again on dynamic energy 16