High Performance Cache Replacement Using Re-Reference Interval Prediction (RRIP)

Transcription

1 High Performance Cache Replacement Using Re-Reference Interval Prediction (RRIP) 1 T H E A C M I E E E I N T E R N A T I O N A L S Y M P O S I U M O N C O M P U T E R A R C H I T E C T U R E ( I S C A ) C O N F E R E N C E, J U N E , , S A I N T - M A L O, F R A N C E. Chien-Chih(Paul) Chao Chih-Chiang(Michael) Chang Instructor: Dr. Ann Gordon-Ross

2 OUTLINE INTRODUCTION RELATED WORK RE-REFERENCE INTERVAL PREDICTION EXPERIMENTAL AND RESULT 2

3 INTRODUCTION Cache replacement policy can be viewed as basing their decision on a prediction LRU(Least Recently Used ) MRU position represent recently used cache block LRU position represent least used cache block It can be thought of as a Re-Reference Interval Prediction 3 Near-immediate re-reference interval Distant re-reference interval HEAD TAIL

4 RELATED WORK LRU provide good performance for workload with high data locality Whose data re-reference only occur in the distant future degrade performance DIP(Dynamic Insertion Policy) Dynamic change prediction policy(lru/bip) Make the same predictions for all reference workload Mix access pattern could not make accurate prediction 4

5 RELATED WORK For distant re-reference interval 5 Victim selection policy need to change From inserting blocks at the head to inserting blocks at the tail Preserve some working set in the cache BIP MISS MISS MISS MISS MISS a1 a6 a2 a7 a3 a1 a4 a2 a3 a5 a1 a2 a3 a4 a5 a6 a7 HIT HIT HIT MISS MISS a1 a2 a3 a7 a4 a5 a5 a6 a4 a1 a2 a3 a4 a5 a6 a7

6 RELATED WORK 6 Hybrid LRU/LFU Use set dueling to dynamic choose between multiple replacement(lru/lfu) Provide scan-resistant

7 RELATED WORK 7

8 RE-REFERENCE INTERVAL PREDICTION Not Recently Used (NRC) replacement policy Static RRIP SRRIP with Hit priority SRRIP with Frequency priority Dynamic RRIP Behavior for a Mixed Access Pattern 8

9 RE-REFERENCE INTERVAL PREDICTION Motivation LRU cannot perform to mixed access patterns 9 Chained-based LRU is impractical for highly associative caches The nru-bit Value of 0 implies was recently used and is predicted to be re-referenced in the near-immediate future Value of 1 implies was not recently used and is predicted to be re-referenced in the distant future

10 RE-REFERENCE INTERVAL PREDICTION Motivation One bit of information is not enough NRU cannot identify non-scan blocks in a mix access pattern M-bit Re-Reference Prediction Values (RRPV) 2 M possible RRPV enables intermediate re-reference intervals prediction Hit Priority (HP) Updates RRIP to be near-immediate on a hit Prioritize replacement of blocks with no hits Frequency Priority Decrementing the RRPV register on cache hits Prioritize replacement of blocks with infrequently re-ref 10

11 RE-REFERENCE INTERVAL PREDICTION 11 LRU Mixed Access Pattern a1, a2, a2, a1, b1, b2, b3, b4, a1, a2 Cache Hit: Move block to MRU Cache Miss: Replace LRU block Move block to MUR 11 / 20

12 RE-REFERENCE INTERVAL PREDICTION NRU Mixed Access Pattern a1, a2, a2, a1, b1, b2, b3, b4, a1, a2 Cache Hit: 1. Set nru-bit of block to 0 Cache Miss: 1. Search for first 1 from left 2. If 1 found go to step (5) 3. Set all nru-bits to 1 4. Go to step (1) 5. Replace block and set nrubit to 0 12

13 RE-REFERENCE INTERVAL PREDICTION SRRIP Mixed Access Pattern a1, a2, a2, a1, b1, b2, b3, b4, a1, a2 Cache Hit: 1. Set RRPV of block to 0 Cache Miss: 1. Search for first 3 from left 2. If 3 found go to step (5) 3. Increment all RRPVs 4. Go to step (1) 5. Replace block and set RRPV to 2 13

14 RE-REFERENCE INTERVAL PREDICTION Dynamic RRIP Motivation SRRIP does not thrash-resistant Bimodal RRIP (BRRIP) Similar to Bimodal Insertion Policy of DIP Insert majority of cache blocks with distant re-ref Insert infrequently with a long re-ref interval Set Dueling Choose between scan-resistant SRRIP and thrash-resistant BRRIP by using two Set Dueling Monitors Use a single policy selection counter 14

15 Simulator EXPERIMENTAL AND RESULT CMP$IM 4-way out-of-oreder 128-entry reorder buffer 3 level cache hierarchy Benchmarks 5 workloads from SPEC CPU real world workloads PC Games Multimedia Server 15

16 EXPERIMENTAL AND RESULT 16 Reduces MPKI by 5-18% Outpeform LRU by an average of 2.5%

17 EXPERIMENTAL AND RESULT 17 Reduces MPKI by 5-15% Outpeform LRU by an average of 5%

18 EXPERIMENTAL AND RESULT 18 SRRIP is insensitive when M>3 Wider RRPV retain blocks for longer periods 2-bit or 3-bit RRPV is sufficient to be scan-resistant

19 EXPERIMENTAL AND RESULT 19 Improve avg 5% above SRRIP

20 EXPERIMENTAL AND RESULT Base on single-core processor with 16-way 2MB LLC RRIP requires less hardware than LRU yet outperform LRU on average RRIP requires 2.5X less hardware than HYB 20

21 Conclusion RRIP predicts intermediate re-ref between nearimmediate and distant re-ref interval SRRIP needs only 2-bit for scan-resistant DRRIP for both scan-resistant and thrash-resistant 21 SRRIP and DRRIP outperform LRU by an average of 4% and 10% The End