INSTITUTO SUPERIOR TÉCNICO. Architectures for Embedded Computing

Transcription

1 UNIVERSIDADE TÉCNICA DE LISBOA INSTITUTO SUPERIOR TÉCNICO Departamento de Engenharia Informática Architectures for Embedded Computing MEIC-A, MEIC-T, MERC Lecture Slides Version English Lecture 02 Title: Performance Evaluation Summary: ; ; ; ; Design Principles. 2010/2011 Nuno.Roma@ist.utl.pt

2 Architectures for Embedded Computing Performance Evaluation Prof. Nuno Roma ACE 2010/11 - DEI-IST 1 / 29 Previous Class In the previous class... Teaching staff Course info Theoretical lectures Practice/Laboratory classes Office hours Grading rules Plan Bibliography and literature Second part: Motivation and Technology Challenges Prof. Nuno Roma ACE 2010/11 - DEI-IST 2 / 29

3 Road Map Prof. Nuno Roma ACE 2010/11 - DEI-IST 3 / 29 Summary Today: Design Principles Bibliography: Computer Architecture: a Approach, Ch. 1 Prof. Nuno Roma ACE 2010/11 - DEI-IST 4 / 29

4 Prof. Nuno Roma ACE 2010/11 - DEI-IST 5 / 29 Program / Application Code Generator Execution Code Execution Platform / OS Hardware Instruction Cycle Access Cycles Prof. Nuno Roma ACE 2010/11 - DEI-IST 6 / 29

5 Prof. Nuno Roma ACE 2010/11 - DEI-IST 7 / 29 Execution Time or Response Time: the time between the start and the completion of an event. Throughput: the total amount of work done in a given period of time. Performance: 1 Execution Time Performance Comparison: X is n times faster than Y if: n = t execution Y = performance X t execution X performance Y Prof. Nuno Roma ACE 2010/11 - DEI-IST 8 / 29

6 Speedup Speedup (S): measures the improvement that is achieved by optimizing the system X. t execution Xorig S = t execution X opt = performance X opt performance X orig Prof. Nuno Roma ACE 2010/11 - DEI-IST 9 / 29 Prof. Nuno Roma ACE 2010/11 - DEI-IST 10 / 29

7 Hardware Metrics Clock: f clk [MHz, GHz] Prof. Nuno Roma ACE 2010/11 - DEI-IST 11 / 29 Hardware Metrics Clock: f clk [MHz, GHz] Access Cycle: taccess [µs, ns] t 1 access [Kc/s, Mc/s] Prof. Nuno Roma ACE 2010/11 - DEI-IST 11 / 29

8 Hardware Metrics Clock: f clk Access Cycle: [MHz, GHz] taccess [µs, ns] t 1 access [Kc/s, Mc/s] Instruction Cycle: t instruction [µs, ns] CP I = t instruction T clk = t instruction f clk t 1 instruction [MIP S, MF LOP S] Prof. Nuno Roma ACE 2010/11 - DEI-IST 11 / 29 Application Metrics Program Cycle: tprogram [s, ms] Tprogram number of clock cycles operations/s [kop S, MOP S, MF LOP S] Relative Performance: Performance Performance of the Reference System For the reference performance it is usually selected the VAX 11/780 (1977) computer system [1 MIPS]. Prof. Nuno Roma ACE 2010/11 - DEI-IST 12 / 29

9 Application Metrics Response Time vs CPU time CPU Time: User time System time Prof. Nuno Roma ACE 2010/11 - DEI-IST 13 / 29 Metrics Close to the hardware: Simpler and more perceptible; Close to the application: Closer to the normal execution conditions; Complex evaluation environment. Prof. Nuno Roma ACE 2010/11 - DEI-IST 14 / 29

10 Performance Evaluation Example Consider the instruction set of a given processor, where: all instructions execute in 5 clock cycles; the 1 st and 4 th clock cycles imply an access to the external memory; f clk = 500MHz; t mem = 9ns. Prof. Nuno Roma ACE 2010/11 - DEI-IST 15 / 29 Performance Evaluation Example f clk = 500MHz T clk = 2ns taccess = t mem T clk T clk = 9ns 2ns T clk = 5T clk = 10ns t instruction = T 1 + T 2 + T 3 + T 4 + T 5 = taccess + T 2 + T 3 + taccess + T 5 = 13T clk = 26ns Prof. Nuno Roma ACE 2010/11 - DEI-IST 16 / 29

11 Performance Evaluation Example f clk = 500MHz T clk = 2ns taccess = t mem T clk T clk = 9ns 2ns T clk = 5T clk = 10ns t instruction = T 1 + T 2 + T 3 + T 4 + T 5 = taccess + T 2 + T 3 + taccess + T 5 = 13T clk = 26ns CPI=? Performance=? Prof. Nuno Roma ACE 2010/11 - DEI-IST 16 / 29 Performance Evaluation Example f clk = 500MHz T clk = 2ns taccess = t mem T clk T clk = 9ns 2ns T clk = 5T clk = 10ns t instruction = T 1 + T 2 + T 3 + T 4 + T 5 = taccess + T 2 + T 3 + taccess + T 5 = 13T clk = 26ns CPI=13 Performance = 1 t instruction = 38.5 MIPS Prof. Nuno Roma ACE 2010/11 - DEI-IST 16 / 29

12 Speedup Calculation Example New version of the same system using a two times faster memory: t mem = 4.5ns f clk = 500MHz T clk = 2ns t access = t mem T clk T clk = 4.5ns 2ns T clk = 3T clk = 6ns t instruction = T 1 + T 2 + T 3 + T 4 + T 5 = t access + T 2 + T 3 + t access + T 5 = 9T clk = 18ns CPI=9 Performance = 1 t instruction = 55.5 MIPS Speedup: S = t instruction t instruction = Performance Performance = 1.44 Prof. Nuno Roma ACE 2010/11 - DEI-IST 17 / 29 Performance Evaluation using Programs Real Applications: typical programs - eventual portability issues... Modified Applications: programs that were changed in order to emphasize a given aspect of the architecture; Application Kernels: excerpts of representative real programs (e.g., Livermore Loops, Linpack); Simple Programs: easy to install (e.g., Quicksort); Synthetical : fake programs invented to try to match the profile and behavior of real applications. Prof. Nuno Roma ACE 2010/11 - DEI-IST 18 / 29

13 Prof. Nuno Roma ACE 2010/11 - DEI-IST 19 / 29 Suites Desktops: Processing capacity: SPEC CPU2000, Winbench (PC) Graphics: SPECviewperf (OpenGL), SPECapc Generics: Business Winstone, CC Winstone Servers: Processing capacity: SPEC CPU2000 Transaction systems: TPC Embedded Systems: Emerging area; EEMBC - 5 application areas: industrial, consumer, networks, office and telecomunications. Prof. Nuno Roma ACE 2010/11 - DEI-IST 20 / 29

14 SPEC SPEC - Standard Performance Evaluation Corporation SPEC CPU2000 CINT integer programs written in C or C++: (compression, circuits design, GNU CC, chess, etc) CFP floating-point programs written in Fortran-77, Fortran-90 or C: (quantic cromodynamics, differential equations solving, fluids dynamics, image recognition, etc.) SPECviewperf (3D rendering 3D using the OpenGL library) SPECapc (solids modeling with 3D rendering, aeroplane design, etc.) Prof. Nuno Roma ACE 2010/11 - DEI-IST 21 / 29 SPEC Prof. Nuno Roma ACE 2010/11 - DEI-IST 22 / 29

15 Interpretation of Performance Metrics All performance metrics should be interpreted very carefully and the corresponding execution conditions should be thoroughly analyzed. The clock frequency does not properly characterizes many system characteristics (e.g.: execution structures - pipelining, memory, compilers); The access and instruction cycles do not define the processor organization (e.g., CISC vs RISC); The instruction execution cycle may even vary inversely with the system performance! The code generation of the benchmark programs may be tampered... Prof. Nuno Roma ACE 2010/11 - DEI-IST 23 / 29 Power Consumption as Performance Metric Prof. Nuno Roma ACE 2010/11 - DEI-IST 24 / 29

16 Next Class Computer Design Prof. Nuno Roma ACE 2010/11 - DEI-IST 25 / 29 Next Class General Rule: Focus on the common case. Mem ttotal ALU Desc FP t Mem talu tdesc tfp Optimized fraction: F Mem = t Mem t Total Speedup of the optimized version: S Mem = t Mem t Mem Prof. Nuno Roma ACE 2010/11 - DEI-IST 26 / 29

17 Next Class General Rule: Focus on the common case. Mem ttotal ALU Desc FP t Mem talu tdesc tfp Optimized fraction: F Mem = t Mem t Total Speedup of the optimized version: S Mem = t Mem t Mem Amdahl s Law: predicts the impact of the partial speedup S X, corresponding to a given operation module X, in the global system performance. S = 1 (1 F X )+ F X SX Prof. Nuno Roma ACE 2010/11 - DEI-IST 26 / 29 Application of Amdahl s Law Next Class T clk = 2ns taccess = 5T clk = 10ns t instruction = taccess + T 2 + T 3 + taccess + T 5 = 13T clk = 26ns Introduced optimization: t access = 3T clk = 6ns Prof. Nuno Roma ACE 2010/11 - DEI-IST 27 / 29

18 Application of Amdahl s Law Next Class T clk = 2ns taccess = 5T clk = 10ns t instruction = taccess + T 2 + T 3 + taccess + T 5 = 13T clk = 26ns Introduced optimization: t access = 3T clk = 6ns Optimized fraction: Faccess = t access t instruction = 20/26 = 0.77 Prof. Nuno Roma ACE 2010/11 - DEI-IST 27 / 29 Application of Amdahl s Law Next Class T clk = 2ns taccess = 5T clk = 10ns t instruction = taccess + T 2 + T 3 + taccess + T 5 = 13T clk = 26ns Introduced optimization: t access = 3T clk = 6ns Optimized fraction: Faccess = t access t instruction = 20/26 = 0.77 Speedup of the optimized mode: Saccess = t access t = 10/6 = 1.67 access Prof. Nuno Roma ACE 2010/11 - DEI-IST 27 / 29

19 Application of Amdahl s Law Next Class T clk = 2ns taccess = 5T clk = 10ns t instruction = taccess + T 2 + T 3 + taccess + T 5 = 13T clk = 26ns Introduced optimization: t access = 3T clk = 6ns Optimized fraction: Faccess = t access t instruction = 20/26 = 0.77 Speedup of the optimized mode: Saccess = t access t = 10/6 = 1.67 access Global Speedup: S = 1 1 (1 F X ) + F = X SX (1 0.77) = 1.44 Prof. Nuno Roma ACE 2010/11 - DEI-IST 27 / 29 Next Class Next Class Prof. Nuno Roma ACE 2010/11 - DEI-IST 28 / 29

20 Next Class Next Class Processor Logic Architecture: Logic Architecture Architectures Classification Assembly Instructions Addressing Modes Operands Prof. Nuno Roma ACE 2010/11 - DEI-IST 29 / 29