Chapter 3: Computer Organization Fundamentals. Oregon State University School of Electrical Engineering and Computer Science.

Transcription

1 Chapter 3: Computer Organization Fundamentals Prof. Ben Lee Oregon State University School of Electrical Engineering and Computer Science Chapter Goals Understand the organization of a computer system and its components. Understand how assembly instructions are eecuted on the processor. Ch. 3: Computer Organization Fundamentals 2 1

2 Computer Organization CPU - Decodes instructions - Provides - Buses - - Registers path Control Control Unit Control Control Holds instruction & data Input/Output Communicates with the outside world, e.g., display, disk, printer, etc. Ch. 3: Computer Organization Fundamentals 3 Random Access Holds instrutions (program) and data Unified Separate instruction and data memory Organized into consecutive able memory words. 1 memory word data size Size of the information accessed by the CPU (CPU register size) Manufacturer s definition Ch. 3: Computer Organization Fundamentals 4 2

3 Registers Some important registers: PC (Program Counter) holds the of the net inst. to be fetched from memory MAR ( Register) holds the of the net instruction or data to be fetched from memory. MDR ( Register) hold the information (word) to be sent to/from memory. (accumulator) a special register which holds the data to be manipulated by the. ( Register) holds the instruction to be decoded by the Control Unit (). Ch. 3: Computer Organization Fundamentals 5 A Pseudo-CPU Format +1 Eternal To/from memory and I/O devices Ch. 3: Computer Organization Fundamentals 6 3

4 Bus-Register Connections Enable Output Register CLK Input Enable Tri-State Buffer Enable Input Out 0 X Hi-Z Ch. 3: Computer Organization Fundamentals 7 Bus-Register Connections Enable Output Register Input MUX 0 1 CLK Enable Select Tri-State Buffer Enable Input Out 0 X Hi-Z To / From / Ch. 3: Computer Organization Fundamentals 8 4

5 Fetch and Eecute Cycle A series of steps (i.e., micro-operations) a computer takes to fetch and eecute one instruction. Each micro-operation requires a clock cycle. Fetch and eecute cycle => Cycle. Number of micro-operations required to fetch an instruction is usually the same. Number of micro-operations required to eecute each instruction differs depending on Compleity of the instruction e.g., Multiply takes longer than Add Available hardware e.g., Multiplier vs. no multiplier hardware Ch. 3: Computer Organization Fundamentals 9 Fetch Cycle Need to describe what has to happen in each cycle. Will use register transfer operations to describe the movement of data. Fetch Cycle Cycle 1: MAR PC Cycle 2: MDR M[MAR] ; Read the content of memory ; location pointed to by MAR Cycle 3: MDR(), MAR MDR() Cycle 4: PC PC + 1 Go to beginning of Eecute cycle Note: Cycles 2 and 4 can be performed at the same time. Ch. 3: Computer Organization Fundamentals 10 5

6 Fetch Cycle (Step 1) Format Cycle 1: MAR PC PC_OUT enable +1 PC PC MAR enable Eternal PC Ch. 3: Computer Organization Fundamentals 11 Fetch Cycle (Step 2) Format Cycle 2: MDR M[MAR], PC PC + 1 Eternal +1 PC+1 PC enable MDR enable Read PC PC Ch. 3: Computer Organization Fundamentals 12 6

7 Fetch Cycle (Step 3) Format Cycle 3: MDR(), MAR MDR() MDR_OUT enable enable +1 PC+1 PC MAR enable Eternal PC Ch. 3: Computer Organization Fundamentals 13 Eecute Cycle Eecute cycle depends on the instruction Will describe eecute cycle based on instruction in the pseudo-isa: transfer s LDA (Load Accumulator) STA (Store Accumulator) Arithmetic and Logical s ADD (Add to accumulator) SUB (Subtract from accumulator) NAND (Logical NAND to accumulator) SHFT (Shift accumulator) Control Transfer J (Jump to ) BNE (Branch conditionally to ) Ch. 3: Computer Organization Fundamentals 14 7

8 Eecute Cycle Eample: LDA (Load Accumulator) Eecute Cycle Cycle 1: MDR M[MAR] Cycle 2: MDR Return to the beginning of the instruction cycle PC LDA => Ch. 3: Computer Organization Fundamentals 15 Eecute Cycle (Step 1) Format Cycle 1: MDR M[MAR] LDA Eternal MDR enable LDA +1 PC+1 Read PC LDA Ch. 3: Computer Organization Fundamentals 16 8

9 Eecute Cycle (Step 2) Format Cycle 2: MDR LDA enable MDR_OUT enable LDA +1 PC+1 Eternal PC LDA Ch. 3: Computer Organization Fundamentals 17 Eecute Cycle Eample: STA (Store Accumulator) Eecute Cycle Cycle 1: MDR Cycle 2: M[MAR] MDR Return to the beginning of the instruction cycle PC STA <= Ch. 3: Computer Organization Fundamentals 18 9

10 Eecute Cycle (Step 1) Format Cycle 1: MDR STA _OUT enable MDR enable STA +1 PC+1 Eternal PC STA Ch. 3: Computer Organization Fundamentals 19 Eecute Cycle (Step 2) Format Cycle 2: M[MAR] MDR STA STA +1 PC+1 Eternal MDR enable Write PC STA Ch. 3: Computer Organization Fundamentals 20 10

11 Eecute Cycle Eample:ADD (Add to Accumulator) Eecute Cycle Cycle 1: MDR M[MAR] ; Read operand Cycle 2: + MDR ; Add and transfer result to Return to the beginning of the instruction cycle Effective - that points to the operand PC ADD Result Ch. 3: Computer Organization Fundamentals 21 Eecute Cycle (Step 1) Format 1 ADD Cycle 1: MDR M[MAR] MDR enable ADD +1 PC+1 2 Eternal Read PC ADD 2 Ch. 3: Computer Organization Fundamentals 22 11

12 Eecute Cycle (Step 2) Format ADD ADD Cycle 2: + MDR enable 2 Result MDR_OUT enable ADD +1 PC+1 2 Eternal PC ADD 2 Ch. 3: Computer Organization Fundamentals 23 Eecute Cycle Eample: J (Jump to ) Eecute Cycle Cycle 1: PC MDR() Return to the beginning of the instruction cycle Branch Target PC J Net Ch. 3: Computer Organization Fundamentals 24 12

13 Eecute Cycle (Step 1) Format Cycle 1: PC MDR() B MDR_OUT enable PC enable B +1 PC+1 Eternal PC B Net Ch. 3: Computer Organization Fundamentals 25 Eecute Cycle Eample: BNE (Branch Conditionally to ) Eecute Cycle Cycle 1: If (Z!= 1) then PC MDR() Return to the beginning of the instruction cycle Branch Target PC BNE Net Ch. 3: Computer Organization Fundamentals 26 13

14 Eecute Cycle (Step 1) Z=1 if last operation is zero Z Branch MDR_OUT enable PC enable BZ Format Cycle 1: If (Z!= 1) then PC MDR() MDR_OUT enable PC enable BZ +1 PC+1 Eternal PC BNE Net Ch. 3: Computer Organization Fundamentals 27 One More Eample Eample: LDA () (Load Accumulator Indirect) Eecute Cycle Cycle 1: MDR M[MAR] ; Read effective () Cycle 2: MAR MDR ; Move to MAR Cycle 3: MDR M[MAR] ; Read operand Cycle 4: MDR ; Move operand to Return to the beginning of the instruction cycle Useful for indeing arrays! PC LDA Effective - that points to the operand => Ch. 3: Computer Organization Fundamentals 28 14

15 Eecute Cycle (Step 1) Format Cycle 1: MDR M[MAR] LDA () MDR enable LDAI +1 PC+1 Eternal Read PC LDAI Ch. 3: Computer Organization Fundamentals 29 Eecute Cycle (Step 2) Format Cycle 2: MAR MDR LDA () MDR_OUT enable LDAI +1 PC+1 PC MAR enable Eternal PC LDAI Ch. 3: Computer Organization Fundamentals 30 15

16 Eecute Cycle (Step 3) Format LDA Cycle 3: MDR M[MAR] () LDAI Eternal +1 PC+1 PC Read PC LDAI MDR enable Ch. 3: Computer Organization Fundamentals 31 Eecute Cycle (Step 4) Format Cycle 4: MDR LDA () enable MDR_OUT enable LDAI +1 PC+1 Eternal PC LDAI Ch. 3: Computer Organization Fundamentals 32 16

17 Last Eample(I promise!) Eample: LDA -() (Load Accumulator Indirect with Pre-decrement) Useful for stepping through arrays Eecute Cycle +1 Cycle 1: MDR M[MAR] ; Read Cycle 2: MDR MDR - 1 ; Decrement Cycle 3: M[MAR] MDR ; Store it back in location (i.e., M[]) Cycle 4: MAR MDR ; Move to MAR Cycle 5: MDR M[MAR] ; Read operand Cycle 6: MDR ; Move operand to PC LDAI => -1 => Ch. 3: Computer Organization Fundamentals 33 Easiest Way Format ADD -() +1 PC -1 MDR MAR Eternal To/from memory and I/O devices Assume MDR can decrement itself Ch. 3: Computer Organization Fundamentals 34 17

18 Hard Way (1) MDR does not have the ADD capability to decrement itself Must use and! Format -() +1 Eternal To/from memory and I/O devices Ch. 3: Computer Organization Fundamentals 35 Hard Way (2) Eecute Cycle +1 Cycle 1: MDR M[MAR] Cycle 2: MDR +1 Cycle 3: - 1 Cycle 4: MDR Cycle 5: M[MAR] MDR Cycle 6: MAR MDR Cycle 7: MDR M[MAR] Cycle 8: MDR ; Read +1 ; Move +1 to ; Decrement +1 ; Move to MDR ; Store it back in location (i.e., M[]) ; Move MAR ; Read operand ; Move operand to Note: Cycles 5 and 6 can be performed at the same time. Ch. 3: Computer Organization Fundamentals 36 18

19 Pseudo-CPU with TEMP Register There may be times when the content of has to be preserved. TEMP increases the fleibility for implementing more complicated instructions, e.g., STA -(), LDA ()+, STA()+. TEMP +1 Eternal To/from memory and I/O devices Ch. 3: Computer Organization Fundamentals 37 What We Will See Later Z DEMUX MUXJ k16 PC+1+ se k PC+1 Fetch PMAR Program PC 1 0 MUXL Addr 16 + AVR Microler Used in low-end embedded systems Inst/ Out k16 PC+1 +SP, SP- AR, AR+, -AR, or AR+q PC MUXK Eecute MUXH 1 0 AR 8 8 MDR 8 Opcode MUXC A 6 Rd Rr 5 5 Register Addr. Logic 7 7 wa wb ra rb ina Register File inb outa outb Alignment Unit 7 7 K 8 zf q 6 16 se k 7 or 12 AR DMAR RARh RAR 1 0 MUXI RARl NPC PC+1 or k16 SP MUXA 1 0 MUXD In 1 0 MUXE Addr 1 0 MUXF MUXG 16 MUXB A Result B 8 Out B A Addess Adder Result AR, AR+,-AR, or AR+q PC+1+se k, k16, +SP, or SP- Ch. 3: Computer Organization Fundamentals 38 19

20 What You Will See in ECE stage pipeline Used in high-end embedded systems, e.g., Mobile devices. Ch. 3: Computer Organization Fundamentals 39 What You Will See in ECE 570 Branch Prediction Cache Fetch SuperScalar OoO (out-oforder eecution) Speculation Used in PCs and servers. Dispatch Queue Register File Reservation Stations Branch Integer Integer FP Load/ Store Reorder Buffer Forwarding Bypass Cache Commit Ch. 3: Computer Organization Fundamentals 40 20

21 Questions? Ch. 3: Computer Organization Fundamentals 41 21