Pipelined MIPS Datapath with Control Signals

Transcription

1 uction ess uction Rs [:26] (Opcode[5:]) [5:] ranch luor. Decoder Pipelined MIPS path with Signals luor Raddr at

2 Five instruction sequence to be processed by pipeline: op [:26] rs [25:2] rt [2:6] rd [5:] funct [5:] immed [5:] : lw r, 9(r) 5 n/a n/a 9 4: sub r, r2, r 2 4 n/a 8: and r2, r4, r n/a 2: or r, r6, r n/a 6: add r4, r8, r n/a decoding for each of these instructions: luctrl rctrl luor lw x sub x x and x x or x x add x x (N.., control for all R-type instructions is generated by the funct field, and luctrl in this case serves to allow local decoding of this field). ssume that, initially, r = 9, r2 = 4, r = 7, r4 = 6, r5 =, r6 =, r7 =, r8 =, and r9 =2. ory location 4 is assumed to contain the value 2.

3 uction ess uction ($8C29) Rs [:26] (Opcode[5:]) [5:] ranch luor. Decoder luor : lw r, 9(r). Fetch 4 4 Raddr at

4 4: sub r, r2, r. Fetch : lw r, 9(r). Decode 8 4 uction ess 8 uction ($45822) 4 [:26] = 5 (Opcode[5:]) Rs () (). Decoder [5:] (9) luor x Raddr 9 at () () 9 ranch luor

5 8: and r2, r4, r5. Fetch 4: sub r, r2, r. Decode : lw r, 9(r) Execute 2 8 uction ess 2 uction ($85624) 8 [:26] = (Opcode[5:]) Rs (2) (). Decoder [5:] ($5822) luor Raddr 4 at 7 x x () () x 9 () () (6) ranch luor

6 2: or r, r6, r7 8: and r2, r4, r5 4: sub r, r2, r : lw r, 9(r). Fetch. Decode Execute ory 6 2 uction ess 6 uction ($C7825) 2 [:26] = (Opcode[5:]) Rs (4) (5). Decoder [5:] luor Raddr 6 at x x (5) (2) x () () x 9 ranch 2 luor

7 6: addr4, r8, r9 2: or r, r6, r7 8: and r2, r4, r5 4: sub r, r2, r : lw.... Fetch. Decode Execute ory back 2 6 uction ess 2 uction ($972) 6 [:26] = (Opcode[5:]) Rs (6) (7) 2. Decoder luor [5:] x x Raddr at (7) () x (5) (2) x 7 ranch luor 4 2

8 6: add r4, r8, r9 2: or r, r6, r7 8: and r2, r4, r5 4: sub.... Decode Execute ory back 24 2 uction ess 24 uction 2 [:26] = (Opcode[5:]) Rs (8) (9) 7. Decoder [5:] luor Raddr at 2 x x (9) (4) x (7) () 6 6 x 2 ranch luor 7

9 6: add r4, r8, r9 Execute 2: or r, r6, r7 ory 8: and... back uction ess 28 uction 24 [:26] = (Opcode[5:]) Rs 2 6. Decoder luor Raddr at [5:] x (9) (4) x ranch luor 6 2

10 Raddr uction ess uction Rs [:26] = (Opcode[5:]) [5:] ranch luor. Decoder luor 6: add r4, r8, r ory x 4 2 back 2: or... at

11 Raddr uction ess uction Rs [:26] = (Opcode[5:]) [5:] ranch luor. Decoder luor 2 6? back 6: add... at

12 Important points about the pipeline operation: lthough the pipeline allows one instruction to complete in every clock cycle (when operating at maximum efficiency), each individual instruction still takes five clock cycles to complete. 2 It takes four clock cycles before the pipeline is operating a maximum efficiency (startup time). Register writeback data and controls (, and ) are provided by the W stage, not the ID stage. This can be a pitfall because the pipeline diagram shows the register file as being part of the ID stage. Don t forget the feedback. 4 Register reads from instruction i happen in parallel with register writes from instruction i -. 5 When a stage is inactive, any lines which control memory or register accesses are deasserted (in active high logic, set to ). 6 Notice that the sequencing of the pipeline is controlled by the instruction currently in the MEM stage of execution, i.e., the decision about whether to sequence or branch is made by the instruction which entered the pipeline three cycles ago.