High Perform ance Caches: The Q uiet Revolution
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1 High Perform ance Caches: The Q uiet Revolution David Chapm an M anager, pplications Engineering FSR M D ivision M em ory and M icroprocessor Technology Group M otorola Sem iconductor Products Sector ustin,texas David Chapm an,em ail:rxcg80@ em ail.sps.m ot.com 1
2 Intel Processor Core Clock Frequencies 1000 Core Clock Freq. (MHz) Source: Intel Microprocessor Quick Reference Guide Date David Chapm an,em em ail.sps.m ot.com 2
3 Processor Core Speed Trends The Long View 1000 High End Processors Core Clock Freq. (MHz) Volume Processors Source: Intel Microprocessor Quick Reference Guide Date David Chapm an,em ail:rxcg80@ em ail.sps.m ot.com 3
4 Processor Core Speed Trends 1000 High End Processors Core Clock Freq. (MHz) 100 Volume Processors Source: Intel Microprocessor Quick Reference Guide Date David Chapm an,em em ail.sps.m ot.com 4
5 Intel System Bus Speeds 100 Bus Freq. (MHz) Source: Intel Microprocessor Quick Reference Guide Year David Chapm an,em em ail.sps.m ot.com 5
6 Volume Processor Max. Bus Speed Trend Years Bus Freq. (MHz) Source: Intel Microprocessor Quick Reference Guide Year David Chapm an,em em ail.sps.m ot.com 6
7 High End Processor Cycle Time vs. DRM Latency Nanoseconds 10 Latency/Cycle Date DRM Latency Hi End up Cycle Latency/Cycle David Chapm an,em ail:rxcg80@ em ail.sps.m ot.com 7
8 Volume Processor Cycle Time vs. DRM Latency Nanoseconds 10 Latency/Cycle Date DRM Latency Hi End up Cycle Latency/Cycle David Chapm an,em ail:rxcg80@ em ail.sps.m ot.com 8
9 Processor Bus Frequency Processor Cycle Time RM ccess Time Requirement MHz ns ns David Chapm an,em ail:rxcg80@ em ail.sps.m ot.com 9
10 150 M Hz Barrier BG Conversion Cache SR M Breakthroughs 300 M Hz Barrier Echo Clock Conversion Sync Late W rite FSR M Double Data FSR M (Burst + Late W rite) 100 M Hz Barrier Revo Conversion sync FSR M Evolutionary sync FSR M 50 M Hz Barrier Sync Conversion Evolutionary Burst Sync FSR M Burst Sync FSR M David Chapm an,em ail:rxcg80@ em ail.sps.m ot.com 10
11 Evolutionary and rchitecture FSR M and rchitecture FSR M Note:Draw ings not to scale David Chapm an,em ail:rxcg80@ em ail.sps.m ot.com 11
12 synchronous Read-Write Sequence ddress Select Write Data 0 1 David Chapm an,em ail:rxcg80@ em ail.sps.m ot.com 12
13 150 M Hz Barrier BG Conversion Cache SR M Breakthroughs 300 M Hz Barrier Echo Clock Conversion Sync Late W rite FSR M Double Data FSR M (Burst + Late W rite) 100 M Hz Barrier Revo Conversion sync FSR M Evolutionary sync FSR M 50 M Hz Barrier Sync Conversion Evolutionary Burst Sync FSR M Burst Sync FSR M David Chapm an,em ail:rxcg80@ em ail.sps.m ot.com 13
14 Evolutionary and rchitecture Pipelined Burst SR M Burst Control& R/W Burst & R/W x16 PLCC x32 TQ FP Note:Draw ings not to scale David Chapm an,em ail:rxcg80@ em ail.sps.m ot.com 14
15 Pipelined Burst Synchronous Read-Write-Read Sequence T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 Clock ddress 0 n/a n/a 1 2 Control Data Read NoOp NoOp Write Read David Chapm an,em ail:rxcg80@ em ail.sps.m ot.com 15
16 Pipelined Synchronous BurstRM Burst Read Sequence T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 Clock ddress 0 n/a n/a n/a 1 Control Read Burst Burst Burst Read Data 0a 0b 0c 0d David Chapm an,em ail:rxcg80@ em ail.sps.m ot.com 16
17 150 M Hz Barrier BG Conversion Cache SR M Breakthroughs 300 M Hz Barrier Echo Clock Conversion Sync Late W rite FSR M Double Data FSR M (Burst + Late W rite) 100 M Hz Barrier Revo Conversion sync FSR M Evolutionary sync FSR M 50 M Hz Barrier Sync Conversion Evolutionary Burst Sync FSR M Burst Sync FSR M David Chapm an,em ail:rxcg80@ em ail.sps.m ot.com 17
18 Processor Core Frequency vs. Volume Bus Frequency 10 Core Freq. / Bus Freq Date Volume up High End up David Chapm an,em ail:rxcg80@ em ail.sps.m ot.com 18
19 Back Side L2 Port rchitecture Frees FSR M s to Run at Core Frequency CPU L2 Cache Chip Set The Traditional CPU/ L2 Cache rchitecture Processor Bus Speed constrained by load to MHz - 133MHz in Workstation Market - 50 MHz - 66MHz in the PC Market L2 Cache sits on the slow processor bus Traditional Standard Lookaside L2 L2 Cache CPU Chip Set The Emerging CPU/ L2 Cache rchitecture Processor Bus Speed constrained by load to MHz - 133MHz in Workstation Market - 50 MHz - 66MHz in the PC Market Cache Bus Speed MHz MHz in Workstation Market - 90 MHz MHz in the PC Market Emerging Back-Side L2 rchitecture David Chapm an,em ail:rxcg80@ em ail.sps.m ot.com 19
20 and rchitecture Late W rite SR M in Plastic BG Package Bottom V iew Top V iew Note:Draw ings not to scale David Chapm an,em ail:rxcg80@ em ail.sps.m ot.com 20
21 R/R Late Write Synchronous Read-Write-Read Sequence T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 Clock ddress 0 n/a Control Data Read NoOp Write Read Read David Chapm an,em ail:rxcg80@ em ail.sps.m ot.com 21
22 Processor Bus Frequency Processor Cycle Time RM ccess Time Requirment SRM Type By Speed Range MHz ns ns sync Revo sync BurstRM LW RM DDR RM David Chapm an,em ail:rxcg80@ em ail.sps.m ot.com 22
23 150 M Hz Barrier BG Conversion Cache SR M Breakthroughs 300 M Hz Barrier Echo Clock Conversion Sync Late W rite FSR M Double Data FSR M (Burst + Late W rite) 100 M Hz Barrier Revo Conversion sync FSR M Evolutionary sync FSR M 50 M Hz Barrier Sync Conversion Evolutionary Burst Sync FSR M Burst Sync FSR M David Chapm an,em ail:rxcg80@ em ail.sps.m ot.com 23
24 Double Data Rate Synchronous FSRM Item 773 1M thru 16M, x16/18/32/36 in 9x17 bump BG, 50mil Pitch Double Data Rate FSR M Fam ily 1M b thru 16M b x16,18,32,36 Burst Sync 1.27m m Pitch 14m m x22m m Body PBG Package HSTL I/O VSS VD S S ZQ S S VD VSS B * S VSS B1 VSS S * C VSS VD S,NC S G\ S S,NC VD VSS D * S,NC VSS VDD VSS S,NC * E VSS VD VSS VDD VREF VDD VSS VD VSS F * CQ * VDD VDD VDD CQ* G VSS VD VSS VSS CK VSS VSS VD VSS H *% VDD CK\ VDD * % * J VSS VD VSS VDD VDD VDD VSS VD VSS K * % * VSS B2 VSS *% L VSS VD VSS LBO B3 MODE VSS VD VSS M CQ\* VDD VDD VDD * CQ\ * N VSS VD VSS VDD VREF VDD VSS VD VSS P * S* VSS VDD VSS S * R VSS VD VDD S S1 S VDD VD VSS T * S VSS S0 VSS S * U VSS VD TDI TMS TCK TRST TDO VD VSS KEY * = NC for x16/18 version CQ* and CQ\* = NC on x16/18 version S* = NC for x32/36 version % and *% = NC for x16/x32 version Top View Rev /30/96 Density Upgrades x32/36 x16/18 3C 7C 7D 3D BG Package 1M 1M NC NC NC NC 14mmx22mm (MO-163) 2M 2M S NC NC NC 14mmx22mm (MO-163) 4M 4M S S NC NC 14mmx22mm (MO-163) 8M 8M S S S NC TBD 16M 16M S S S S TBD David Chapm an,em ail:rxcg80@ em ail.sps.m ot.com 24
25 Double Data Burst Synchronous Read-Write-Read Sequence T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 Clock ddress n/a Control Read NoOp Write Read Continue tkhch Data 0a 0b 2a 2b 3a 3b 3c 3d Echo Clock David Chapm an,em ail:rxcg80@ em ail.sps.m ot.com 25
26 M Hz L2 FSR M rchitecturalconvergence BG DDR R M x18/x36 BG DDR R M x32/x BG x18/x36 LW RM PLCC x18 Pipe Burst TQFP x36 Pipe Burst TQFP x32 Pipe Burst BG x32 Pipe Burst 66 PLCC x18 FT Burst TQFP x32 Pipe Burst Year David Chapm an,em ail:rxcg80@ em ail.sps.m ot.com 26
27 150 M Hz Barrier BG Conversion The Q uiet Revolution 300 M Hz Barrier Echo Clock Conversion Sync Late W rite FSR M Double Data FSR M (Burst + Late W rite) 100 M Hz Barrier Revo Conversion sync FSR M Evolutionary sync FSR M 50 M Hz Barrier Sync Conversion Evolutionary Burst Sync FSR M Burst Sync FSR M David Chapm an,em ail:rxcg80@ em ail.sps.m ot.com 27
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