Registers Shift Registers Accumulators Register Files Register Transfer Language. Chapter 8 Registers. SKEE2263 Digital Systems

Transcription

1 Chapter 8 Registers SKEE2263 igital Systems Mun im Zabidi {munim@utm.my} Ismahani Ismail {ismahani@fke.utm.my} Izam Kamisian {e-izam@utm.my} Faculty of Electrical Engineering, Universiti Teknologi Malaysia March 27, 28

2 Table of Contents Registers 2 Shift Registers 3 Accumulators 4 Register Files 5 Register Transfer Language

3 Basic Register 3 2 Clk 3 2 Clk Ignored [3:] [3:]

4 Resettable Register 3 2 CLR CLR CLR CLR Clk Clear 3 2 Clk [3:] Clear [3:] xxxx Cleared

5 Register with Load Enable 3 2 Load Clk 3 2 Clk [3:] Load [3:] xxxx

6 Basic Shift Register Input Clk 3 2

7 Shift Register Animation Initial condition CLK After first clock pulse After second clock pulse After third clock pulse After fourth clock pulse After fifth clock pulse CLK CLK CLK CLK CLK

8 Shift Register Timing iagram Clk Input 3 2

9 Enabled Shift Register Input Shift Clk 3 2 Clk Input Shift [3:]

10 Universal Shift Register 3 2 RSI S S LSI Clear Clk S S Function Hold Shift left Shift right Load new input 3 2 Can be used in either serial-to-serial, serial-to-parallel, parallel-to-serial, parallel-to-parallel, left shifting as well as right shifting. Useful in arithmetic operations to shift data left for multiplication or to shift data right for division.

11 Universal Shift Register Schematic 3 2 RSI LSI S: S: S: S : Clear Clk 3 2

12 Universal Shift Register Timing iagram Clk RSI LSI [3:] A C E 2 S[:] [3:] A 5 2 2

13 Accumulators Accumulator 6 + Acc Clock Accumulator: register that keeps results of arithmetic ops. Registers + Adders Accumulator-based counter. Any adder architecture may be used. Clk Acc E 3F Accumulator overflow

14 6-bit Accumulator-Based Counter HA HA HA HA HA HA Clk

15 Resettable Counter + Accumulator Acc Clear Function Run Clear Clear Clock Check your understanding. This is Milestone 2.

16 Multi-Function Counter No Accumulator Acc S S Function Clear Add Add 2 Subtract S S Clock

17 Multi-Function Counter No Adder Accumulator 4 4 Acc S S Function Hold Add Add 2 Subtract S S Clock

18 Prescaler.5s s - 25 Hz x7784 Preload (25,,) 5 MHz 25-bit accumulator

19 Timer sec Trig Out Timer Clock 5 MHz Clock Trig Out sec

20 Timer - x2faf bit accumulator Out Preload (5,,) Trig 5 MHz Trig

21 Register Files vs RAM Register Files RAM Capacity Small Large Speed Fast Slow Ease of esign Easy Harder

22 Minimal Register File atain WriteAddr WriteEn ReadAddr 4 x 8 register file ataout Four 8-bit registers 8 atain : n-bit input ataout : n-bit output WriteAddr: log 2 n-bit write address ReadAddr: log 2 n-bit read address WriteEn: write enable

23 Minimal Register File atain ReadAddr WriteAddr 2:4 decoder Register Ld Register Ld Register 2 Ld Register 3 Ld 4: MUX ataout WriteEn

24 Register File with 2 Read Ports atain WriteAddr WriteEn ReadAddrA ReadAddrB OutA OutB x 8 register file

25 Register File with 2 Read Ports ReadAddrA Register Register Register 2 Register 3 4: MUX OutA 4: MUX OutB ReadAddrB

26 Overview of RTL atapath: combination of registers and combinational circuits which manipulate data atapath design is derived from high-level algorithms RTL: high-level description of micro-operations happening in the datapath RTL allows designers to solve problems at high-level; and worry about details later

27 Elements of RTL Elements: Register set Operations performs on data in the registers The sequence of operations R2 Combinational logic Control circuit Load Ld R Clock RTL syntax:

28 RTL Instruction Set Notation Intended Operation X Y Transfer contents of reg. Y to reg. X R Clear contents of REG X all s Set all bits of reg. X X Set the LSB of X and reset all other bits X shl X -bit left-shift X shr X -bit right-shift X 3: X 3: X 3:4 4-bit end-around right-shift X M[x234] X content of memory address x234 X M[Y ] X content of memory pointed by Y X Y Z X Y OR Z (bitwise) X Y Z X Y AN Z (bitwise) X Y Z X Y XOR Z (bitwise) X Y X s complement of Y X Y X 2 s complement of Y X Y + Z X addition of Y and Z X Y Z X subtraction of Z from Y K + + Shorthand for K K + X Y, A B Parallel transfers (cond)/a B if (cond) is true, then transfer B to A S:A B when in state S, transfer B to A P:(x y)/a B when in state P, if x AN y is true, then transfer B to A

29 Simple atapath RTL emo ReadAddrA 4 x 8 reg file ReadAddrB WriteAddr WriteEn OutA + Inata atain OutB Mode Input Mode Mode R d R a R d R a + R b

30 Simple atapath RTL emo RTL ReadAddrA ReadAddrB WriteAddr Mode R R XX R R3 XX R3 R + R Mode Mode R d R a R d R a + R b

31 Simple atapath RTL emo uestion: What is the RTL sequence to exchange R with R (R R)? Assume R2 and R3 are available for temporary storage.