CS 6354: Tomasulo. 21 September 2016
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1 1 CS 6354: Tomasulo 21 September 2016
2 To read more 1 This day s paper: Tomasulo, An Efficient Algorithm for Exploiting Multiple Arithmetic Units Supplementary readings: Hennessy and Patterson, Computer Architecture: A Quantitative Approach, section Shin and Lipatsi, Modern Processor Design, section 5.2
3 Intel Skylake Image: Intel Optimization Reference Manual 2
4 Scheduling 3 How can we reorder instructions? Without changing the answer
5 Recall: Data hazards 4 Instructions had wrong data because they weren t executed one-at-a-time Example: reading old value of register
6 5 Recall: Read-after-Write r1 < r2 + r3 r5 < r1 r5 r1 r2 + r3 r4 r1 - r5 1 IF 2 ID: read r2, r3 IF 3 EX: temp1 r2 + r3 ID: read r1, r5 4 MEM EX: temp2 r1 - r5 5 WB: r1 temp MEM 6 WB: r4 temp2
7 5 Recall: Read-after-Write r1 < r2 + r3 r5 < r1 r5 r1 r2 + r3 r4 r1 - r5 1 IF 2 ID: read r2, r3 IF 3 EX: temp1 r2 + r3 ID: read r1, r5 4 MEM EX: temp2 r1 - r5 5 WB: r1 temp MEM 6 WB: r4 temp2
8 Write-after-Write 6 r1 r2 + r3 ; (1)... r1 r6 + r7 ; (2) r4 r2 + r1 ; (3) time r1 r2 + r3 r1 r6 + r7 r4 r2 + r1 1 read r6, r7 2 read r2, r3 compute 3 compute write r1 4 write r1 5 6 read r1, r2 7 compute
9 Write-after-Write 6 r1 r2 + r3 ; (1)... r1 r6 + r7 ; (2) r4 r2 + r1 ; (3) time r1 r2 + r3 r1 r6 + r7 r4 r2 + r1 1 read r6, r7 2 read r2, r3 compute 3 compute write r1 4 write r1 5 6 value read read r1, r2 7 compute desired value
10 Write-after-Read 7 r1 r2 + r3 ; (1) r3 r4 + r5 ; (2) time r1 r2 + r3 r3 r4 + r5 1 read r4, r5 2 compute 3 write r3 4 read r2, r3 5 compute 6 write r1
11 Types of Data Hazards 8 Read-after-Write (RAW) also called: true dependence Write-after-Write (WAW) also called: output dependence Write-after-Read (WAR) also called: anti-dependence
12 a problem with names 9 write-after-write r1 r2 + r3 ; (1) r1 r6 + r7 ; (2) r4 r2 + r1 ; (3) write-after-read r1 r2 + r3 ; (1) r3 r4 + r5 ; (2) problem if we used a different name each write
13 register renaming original code r1 r2 + r3 r7 r1 + r3 r1 r6 + r7 r4 r2 + r1 r2 r4 + r5 with renaming new1 r2 + r3 ;(1) new2 new1 + r3 ;(2) new3 r6 + r7 ;(3) new4 r2 + new3 ;(4) new5 r4 + r5 ;(5) new old from up to name name new1 r1 (1) (2) new2 r7 (2) new3 r1 (3) new4 r4 (4) new5 r2 (5) 10
14 scheduling with renaming 11 different architectual (external) and internal register names new internal name on each write
15 register renaming state original code r1 r2 + r3 r7 r1 + r3 r1 r6 + r7 r4 r2 + r1 r2 r4 + r5 with renaming x09 x02 + x03 x10 x09 + x03 x11 x06 + x10 x12 x02 + x11 x13 x12 + x05 external name r1 r2 r3 r4 r5 r6 r7 r8 internal name x01 x02 x03 x04 x05 x06 x07 x08 12
16 register renaming state original code r1 r2 + r3 r7 r1 + r3 r1 r6 + r7 r4 r2 + r1 r2 r4 + r5 with renaming x09 x02 + x03 x10 x09 + x03 x11 x06 + x10 x12 x02 + x11 x13 x12 + x05 external name r1 r2 r3 r4 r5 r6 r7 r8 internal name x01 x09 x02 x03 x04 x05 x06 x07 x08 12
17 register renaming state original code r1 r2 + r3 r7 r1 + r3 r1 r6 + r7 r4 r2 + r1 r2 r4 + r5 with renaming x09 x02 + x03 x10 x09 + x03 x11 x06 + x10 x12 x02 + x11 x13 x12 + x05 external name r1 r2 r3 r4 r5 r6 r7 r8 internal name x01 x09 x02 x03 x04 x05 x06 x07 x10 x08 12
18 register renaming state original code r1 r2 + r3 r7 r1 + r3 r1 r6 + r7 r4 r2 + r1 r2 r4 + r5 with renaming x09 x02 + x03 x10 x09 + x03 x11 x06 + x10 x12 x02 + x11 x13 x12 + x05 external name r1 r2 r3 r4 r5 r6 r7 r8 internal name x01 x09 x11 x02 x03 x04 x05 x06 x07 x10 x08 12
19 register renaming state original code r1 r2 + r3 r7 r1 + r3 r1 r6 + r7 r4 r2 + r1 r2 r4 + r5 with renaming x09 x02 + x03 x10 x09 + x03 x11 x06 + x10 x12 x02 + x11 x13 x12 + x05 external name r1 r2 r3 r4 r5 r6 r7 r8 internal name x01 x09 x11 x02 x03 x04 x05 x06 x07 x10 x08 12
20 register renaming state original code r1 r2 + r3 r7 r1 + r3 r1 r6 + r7 r4 r2 + r1 r2 r4 + r5 with renaming x09 x02 + x03 x10 x09 + x03 x11 x06 + x10 x12 x02 + x11 x13 x12 + x05 external name r1 r2 r3 r4 r5 r6 r7 r8 internal name x01 x09 x11 x02 x03 x04 x12 x05 x06 x07 x10 x08 12
21 register renaming state original code r1 r2 + r3 r7 r1 + r3 r1 r6 + r7 r4 r2 + r1 r2 r4 + r5 with renaming x09 x02 + x03 x10 x09 + x03 x11 x06 + x10 x12 x02 + x11 x13 x12 + x05 external name r1 r2 r3 r4 r5 r6 r7 r8 internal name x01 x09 x11 x02 x13 x03 x04 x12 x05 x06 x07 x10 x08 12
22 register renaming state original code r1 r2 + r3 r7 r1 + r3 r1 r6 + r7 r4 r2 + r1 r2 r4 + r5 with renaming x09 x02 + x03 x10 x09 + x03 x11 x06 + x10 x12 x02 + x11 x13 x12 + x05 external name r1 r2 r3 r4 r5 r6 r7 r8 internal name x01 x09 x11 x02 x13 x03 x04 x12 x05 x06 x07 x10 x08 12
23 Diversion: SSA 13 compiler technique: static single-assignment (SSA) form eewrite code as code with immutable variables only makes optimization easier if you kw it this will seem familiar
24 scheduling with renaming # (renamed) instructions run on done? (1) x05 Mem[x03] (2) x06 x01 + x02 (3) x07 x01 x02 (4) x08 x05 x04 (5) x09 x05 + x04 (6) x10 x07 + x06 time Add1 Add2 Mult Load 0 (2) start (3) start (1) start 1 (2) (3) (1) 2 (2) done (3) (1) 3 (3) (1) 4 (3) done (1) 5 (6) start (1) done 6 (6) (5) start (4) start 7 (6) done (5) (4) 8 (5) done (4) 9 (4) 10 (4) done int. name x01 x02 x03 x04 x05 x06 x07 x08 x09 x10 ready? 14
25 scheduling with renaming # (renamed) instructions run on done? (1) x05 Mem[x03] Load (2) x06 x01 + x02 Add1 (3) x07 x01 x02 Mult (4) x08 x05 x04 (5) x09 x05 + x04 (6) x10 x07 + x06 time Add1 Add2 Mult Load 0 (2) start (3) start (1) start 1 (2) (3) (1) 2 (2) done (3) (1) 3 (3) (1) 4 (3) done (1) 5 (6) start (1) done 6 (6) (5) start (4) start 7 (6) done (5) (4) 8 (5) done (4) 9 (4) 10 (4) done int. name x01 x02 x03 x04 x05 x06 x07 x08 x09 x10 ready? 14
26 scheduling with renaming # (renamed) instructions run on done? (1) x05 Mem[x03] Load (2) x06 x01 + x02 Add1 (3) x07 x01 x02 Mult (4) x08 x05 x04 (5) x09 x05 + x04 (6) x10 x07 + x06 int. name x01 x02 x03 x04 x05 x06 x07 x08 x09 x10 ready? Might have second adder, but x5 is t ready. time Add1 Add2 Mult Load 0 (2) start (3) start (1) start 1 (2) (3) (1) 2 (2) done (3) (1) 3 (3) (1) 4 (3) done (1) 5 (6) start (1) done 6 (6) (5) start (4) start 7 (6) done (5) (4) 8 (5) done (4) 9 (4) 10 (4) done 14
27 scheduling with renaming # (renamed) instructions run on done? (1) x05 Mem[x03] Load (2) x06 x01 + x02 Add1 (3) x07 x01 x02 Mult (4) x08 x05 x04 (5) x09 x05 + x04 (6) x10 x07 + x06 time Add1 Add2 Mult Load 0 (2) start (3) start (1) start 1 (2) (3) (1) 2 (2) done (3) (1) 3 (3) (1) 4 (3) done (1) 5 (6) start (1) done 6 (6) (5) start (4) start 7 (6) done (5) (4) 8 (5) done (4) 9 (4) 10 (4) done int. name x01 x02 x03 x04 x05 x06 x07 x08 x09 x10 ready? 14
28 scheduling with renaming # (renamed) instructions run on done? (1) x05 Mem[x03] Load (2) x06 x01 + x02 Add1 (3) x07 x01 x02 Mult (4) x08 x05 x04 (5) x09 x05 + x04 (6) x10 x07 + x06 time Add1 Add2 Mult Load 0 (2) start (3) start (1) start 1 (2) (3) (1) 2 (2) done (3) (1) 3 (3) (1) 4 (3) done (1) 5 (6) start (1) done 6 (6) (5) start (4) start 7 (6) done (5) (4) 8 (5) done (4) 9 (4) 10 (4) done int. name x01 x02 x03 x04 x05 x06 x07 x08 x09 x10 ready? 14
29 scheduling with renaming # (renamed) instructions run on done? (1) x05 Mem[x03] Load (2) x06 x01 + x02 Add1 (3) x07 x01 x02 Mult (4) x08 x05 x04 (5) x09 x05 + x04 (6) x10 x07 + x06 Add1 time Add1 Add2 Mult Load 0 (2) start (3) start (1) start 1 (2) (3) (1) 2 (2) done (3) (1) 3 (3) (1) 4 (3) done (1) 5 (6) start (1) done 6 (6) (5) start (4) start 7 (6) done (5) (4) 8 (5) done (4) 9 (4) 10 (4) done int. name x01 x02 x03 x04 x05 x06 x07 x08 x09 x10 ready? 14
30 scheduling with renaming # (renamed) instructions run on done? (1) x05 Mem[x03] Load (2) x06 x01 + x02 Add1 (3) x07 x01 x02 Mult (4) x08 x05 x04 Mult (5) x09 x05 + x04 Add2 (6) x10 x07 + x06 Add1 time Add1 Add2 Mult Load 0 (2) start (3) start (1) start 1 (2) (3) (1) 2 (2) done (3) (1) 3 (3) (1) 4 (3) done (1) 5 (6) start (1) done 6 (6) (5) start (4) start 7 (6) done (5) (4) 8 (5) done (4) 9 (4) 10 (4) done int. name x01 x02 x03 x04 x05 x06 x07 x08 x09 x10 ready? 14
31 scheduling with renaming # (renamed) instructions run on done? (1) x05 Mem[x03] Load (2) x06 x01 + x02 Add1 (3) x07 x01 x02 Mult (4) x08 x05 x04 Mult (5) x09 x05 + x04 Add2 (6) x10 x07 + x06 Add1 time Add1 Add2 Mult Load 0 (2) start (3) start (1) start 1 (2) (3) (1) 2 (2) done (3) (1) 3 (3) (1) 4 (3) done (1) 5 (6) start (1) done 6 (6) (5) start (4) start 7 (6) done (5) (4) 8 (5) done (4) 9 (4) 10 (4) done int. name x01 x02 x03 x04 x05 x06 x07 x08 x09 x10 ready? 14
32 scheduling with renaming # (renamed) instructions run on done? (1) x05 Mem[x03] Load (2) x06 x01 + x02 Add1 (3) x07 x01 x02 Mult (4) x08 x05 x04 Mult (5) x09 x05 + x04 Add2 (6) x10 x07 + x06 Add1 time Add1 Add2 Mult Load 0 (2) start (3) start (1) start 1 (2) (3) (1) 2 (2) done (3) (1) 3 (3) (1) 4 (3) done (1) 5 (6) start (1) done 6 (6) (5) start (4) start 7 (6) done (5) (4) 8 (5) done (4) 9 (4) 10 (4) done int. name x01 x02 x03 x04 x05 x06 x07 x08 x09 x10 ready? 14
33 scheduling with renaming # (renamed) instructions run on done? (1) x05 Mem[x03] Load (2) x06 x01 + x02 Add1 (3) x07 x01 x02 Mult (4) x08 x05 x04 Mult (5) x09 x05 + x04 Add2 (6) x10 x07 + x06 Add1 time Add1 Add2 Mult Load 0 (2) start (3) start (1) start 1 (2) (3) (1) 2 (2) done (3) (1) 3 (3) (1) 4 (3) done (1) 5 (6) start (1) done 6 (6) (5) start (4) start 7 (6) done (5) (4) 8 (5) done (4) 9 (4) 10 (4) done int. name x01 x02 x03 x04 x05 x06 x07 x08 x09 x10 ready? 14
34 handling variable times 15 scheduling is reactive Load took longer? Doesn t matter. Don t try to start things until ready.
35 Running out of register names? 16 recycle names with operations, external name still out of names? don t issue more instructions
36 reservation stations vs registers 17 Tomasulo paper doesn t seem to have extra registers But has reservation stations with tags these are extra registers and their names
37 pieces in Tomasulo 18 ready bits internal external name mapping extra registers
38 scheduling with reservation buffers 19 # (renamed) instructions run on done? (1) x05 Mem[x03] (2) x06 x01 + x02 (3) x07 x01 x02 (4) x08 x05 x04 (5) x09 x05 + x04 (6) x10 x07 + x06 source 1 tag source 1 ready? source 2 tag source 2 ready? sink tag Add1 Add2 Mult Load
39 scheduling with reservation buffers 19 # (renamed) instructions run on done? (1) x05 Mem[x03] Load (2) x06 x01 + x02 Add1 (3) x07 x01 x02 Mult (4) x08 x05 x04 (5) x09 x05 + x04 Add2 (6) x10 x07 + x06 Add1 Add2 Mult Load source 1 tag x01 x05 x01 x03 source 1 ready? source 2 tag x02 x04 x02 source 2 ready? sink tag x06 x09 x07 x05
40 scheduling with reservation buffers 19 # (renamed) instructions run on done? (1) x05 Mem[x03] Load (2) x06 x01 + x02 Add1 (3) x07 x01 x02 Mult (4) x08 x05 x04 (5) x09 x05 + x04 Add2 (6) x10 x07 + x06 dispatching transmits register values Add1 Add2 Mult Load source 1 tag x01 x05 x01 x03 source 1 ready? source 2 tag x02 x04 x02 source 2 ready? sink tag x06 x09 x07 x05
41 scheduling with reservation buffers 19 # (renamed) instructions run on done? (1) x05 Mem[x03] Load (2) x06 x01 + x02 Add1 (3) x07 x01 x02 Mult (4) x08 x05 x04 (5) x09 x05 + x04 Add2 (6) x10 x07 + x06 Add1 Add2 Mult Load source 1 tag x01 x05 x01 x03 source 1 ready? source 2 tag x02 x04 x02 source 2 ready? sink tag x06 x09 x07 x05
42 scheduling with reservation buffers 19 # (renamed) instructions run on done? (1) x05 Mem[x03] Load (2) x06 x01 + x02 Add1 (3) x07 x01 x02 Mult (4) x08 x05 x04 (5) x09 x05 + x04 Add2 (6) x10 x07 + x06 Add1 Add1 Add2 Mult Load source 1 tag x07 x05 x01 x03 source 1 ready? source 2 tag x06 x04 x02 source 2 ready? sink tag x10 x09 x07 x05
43 scheduling with reservation buffers 19 # (renamed) instructions run on done? (1) x05 Mem[x03] Load (2) x06 x01 + x02 Add1 (3) x07 x01 x02 Mult (4) x08 x05 x04 (5) x09 x05 + x04 Add2 (6) x10 x07 + x06 Add1 Add1 Add2 Mult Load source 1 tag x07 x05 x01 x03 source 1 ready? source 2 tag x06 x04 x02 source 2 ready? sink tag x10 x09 x07 x05
44 scheduling with reservation buffers 19 # (renamed) instructions run on done? (1) x05 Mem[x03] Load (2) x06 x01 + x02 Add1 (3) x07 x01 x02 Mult (4) x08 x05 x04 Mult (5) x09 x05 + x04 Add2 (6) x10 x07 + x06 Add1 Add1 Add2 Mult Load source 1 tag x07 x05 x05 x03 source 1 ready? source 2 tag x06 x04 x04 source 2 ready? sink tag x10 x09 x08 x05
45 scheduling with reservation buffers 19 # (renamed) instructions run on done? (1) x05 Mem[x03] Load (2) x06 x01 + x02 Add1 (3) x07 x01 x02 Mult (4) x08 x05 x04 Mult (5) x09 x05 + x04 Add2 (6) x10 x07 + x06 Add1 Add1 Add2 Mult Load source 1 tag x07 x05 x05 x03 source 1 ready? source 2 tag x06 x04 x04 source 2 ready? sink tag x10 x09 x08 x05
46 common data bus 20 results are broadcast here tag internal register name reservation stations listen for operands register file listens for register values keeps register file from being bottleneck fancy buses: mutliple value+tags per clock cycle
47 issuing instructions 21 assign tags for operands instruction will execute when operands are ready handles variable length operations (e.g. loads)
48 integrating with reorder buffer Hennessy & Patterson Figure
49 integrating with reorder buffer (2) 23 reorder buffer just ather thing listening on bus
50 multiple entries in reservation stations 24 instead of dispathcing one instruction, issue a list reservation station starts whichever one gets operands first
51 variations on reservation stations 25 Intel P6: shared reservation station for all types of operations MIPS R10000 (next Monday s paper): read from shared register file (with renaming)
52 Intel P6 execution unit datapaths Image: Shen and Lipatsi, Figure
53 summary 27 register renaming to avoid data hazards otherwise even write-after-write, write-after-read a problem shared bus to communicate results register file, reservation buffers listen on bus can dispatch to buffer before value ready
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