Direct-Mapped Cache Terminology. Caching Terminology. TIO Dan s great cache mnemonic. UCB CS61C : Machine Structures

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1 Lecturer SOE Dan Garcia inst.eecs.berkeley.edu/~cs61c UCB CS61C : Machine Structures Lecture 31 Caches II HP has begun testing research prototypes of a novel non-volatile memory element, the memristor. They have double the storage density of flash, and has 10x more read-write cycles than flash (10 6 vs 10 5 ). Memristors described in Nature are also capable of being memory and logic, how cool is that? Direct-Mapped Cache Terminology All fields are read as unsigned integers. Index specifies the cache index (or row /block) Tag distinguishes betw the addresses that map to the same location Offset specifies which byte within the block we want ttttttttttttttttt iiiiiiiiii oooo tag index byte to check to offset if have select within correct block block block CS61C L31 Caches II (2) TIO Dan s great cache mnemonic AREA (cache size, B) 2 = HEIGHT (# of blocks) (H+W) = 2 H * 2 W * WIDTH (size of one block, B/block) WIDTH Tag Index Offset (size of one block, B/block) Addr size (usu 32 bits) HEIGHT (# of blocks) AREA (cache size, B) Caching Terminology When reading memory, 3 things can happen: cache hit: cache block is valid and contains proper address, so read desired word cache miss: nothing in cache in appropriate block, so fetch from memory cache miss, block replacement: wrong data is in cache at appropriate block, so discard it and fetch desired data from memory (cache always copy) CS61C L31 Caches II (3) CS61C L31 Caches II (4) Accessing data in a direct mapped cache Ex.: 16KB of data, Memory Address (hex) Value of Word direct-mapped, a# 4 word blocks b# Can you work out c# height, width, area? C d# Read 4 addresses e# 1. 0x f# 2. 0x C g# 3. 0x C h# 4. 0x i# Memory vals here: j# k# C l# CS61C L31 Caches II (5) Accessing data in a direct mapped cache 4 Addresses: 0x , 0x C, 0x , 0x Addresses divided (for convenience) into Tag, Index, Byte Offset fields Tag Index Offset CS61C L31 Caches II (6)

2 CS61C L31 Caches II (7) 16 KB Direct Mapped Cache, 16B blocks bit: determines whether anything is stored in that row (when computer initially turned on, all entries invalid) Read 0x CS61C L31 Caches II (8) So we read block 1 ( ) No valid data CS61C L31 Caches II (9) CS61C L31 Caches II (10) So load that data into cache, setting tag, valid Read from cache at offset, return word b CS61C L31 Caches II (11) CS61C L31 Caches II (12)

3 CS61C L31 Caches II (13) 2. Read 0x C = Index is CS61C L31 Caches II (14) Index valid, Tag Matches Index, Tag Matches, return d CS61C L31 Caches II (15) CS61C L31 Caches II (16) 3. Read 0x = So read block CS61C L31 Caches II (17) CS61C L31 Caches II (18)

4 CS61C L31 Caches II (19) No valid data Load that cache block, return word f CS61C L31 Caches II (20) 4. Read 0x = So read Cache Block 1, Data is CS61C L31 Caches II (21) CS61C L31 Caches II (22) Cache Block 1 Tag does not match (0!= 2) Miss, so replace block 1 with new data & tag CS61C L31 Caches II (23) CS61C L31 Caches II (24)

5 CS61C L31 Caches II (25) And return word J Do an example yourself. What happens? Chose from: Cache: Hit, Miss, Miss w. replace Values returned: a,b, c, d, e,, k, l Read address 0x ? Read address 0x c? Cache# CS61C L31 Caches II (26) Answers Peer Instruction 0x a hit Index = 3, Tag matches, Offset = 0, value = e 0x c a miss Index = 1, Tag mismatch, so replace from memory, Offset = 0xc, value = d Since reads, values must = memory values whether or not cached: 0x = e 0x c = d CS61C L31 Caches II (27) Memory Address (hex) Value of Word a# b# c# C d# C C e# f# g# h# i# j# k# l# 1) Mem hierarchies were invented before (UNIVAC I wasn t delivered til 1951) 2) If you know your computer s cache size, you can often make your code run faster. CS61C L31 Caches II (29) 12 a) FF b) FT c) TF d) TT Peer Instruction And in Conclusion 1. All caches take advantage of spatial locality. 2. All caches take advantage of temporal locality. CS61C L31 Caches II (31) 12 a) FF b) FT c) TF d) TT Mechanism for transparent movement of data among levels of a storage hierarchy set of address/value bindings address index to set of candidates compare desired address with tag service hit or miss load new block and binding on miss address: tag index offset # Tag 0xc-f 0x8-b 0x4-7 0x0-3 1# 0# d# c# b# a# CS61C L31 Caches II (33)