CS 152 Computer Architecture and Engineering. Lecture 15 - Advanced Superscalars

Transcription

1 CS 152 Comuter Architecture and Engineering Lecture 15 - Advanced Suerscalars Krste Asanovic Electrical Engineering and Comuter Sciences University of California at Berkeley htt:// htt://inst.eecs.berkeley.edu/~cs152 Last time in Lecture 14 Control hazards are serious imediment to suerscalar erformance Dynamic branch redictors can be quite accurate (>95%) and avoid most control hazards Branch History s (BHTs) just redict direction (later in ieline) Just need a few bits er entry (2 bits gives hysteresis) Need to decode instruction bits to determine whether this is a branch and what the target address is Branch Target Buffer (BTB) redicts whether a branch, and target address Needs PC tag, redicted Next-PC, and direction Just needs PC of instruction to redict target of branch (if any) Return address stack: secial form of BTB used to redict subroutine return addresses 4/1/2008 CS152-Sring!08 2

2 in Design (HP PA8000, Pentium Pro, Core2Duo) Reorder buffer Register File holds only committed state Ins# use exec o 1 src1 2 src2 d dest data t 1 t 2.. t n Load Unit FU FU FU Store Unit Commit < t, result > On disatch into, ready sources can be in regfile or in dest (coied into src1/src2 if ready before disatch) On comletion, write to dest field and broadcast to src fields. On issue, read from src fields 4/1/2008 CS152-Sring!08 3 Unified Physical Register File (MIPS 0K, Alha 21264, Pentium 4) r 1 r 2 t i t j Snashots for misredict recovery t 1 t 2. t n Reg File Load Unit FU FU FU Store Unit ( not shown) < t, result > One regfile for both committed and seculative values (no data in ) During decode, instruction result allocated new hysical register, source regs translated to hysical regs through rename table Instruction reads data from regfile at start of execute (not in decode) Write-back udates reg. busy bits on instructions in (assoc. search) Snashots of rename table taken at every branch to recover misredicts On excetion, renaming undone in reverse order of issue (MIPS 0000) 4/1/2008 CS152-Sring!08 4

3 Pieline Design with Physical Regfile Branch Prediction Branch Resolution Out-of-Order Udate redictors In-Order PC Fetch Decode & Reorder Buffer Commit In-Order Physical Reg. File Branch Unit Execute ALU MEM Store Buffer 4/1/2008 CS152-Sring!08 5 D$ Lifetime of Physical Registers Physical regfile holds committed and seculative values Physical registers decouled from entries (no data in ) ld r1, (r3) sub r6, r7, r9 ld r6, (r1) add r6, r6, r3 st r6, (r1) ld r6, (r11) ld, (Px) add,, #4 sub, Py, Pz add,, ld, () add,, st, () ld, (Pw) When can we reuse a hysical register? When next write of same architectural register commits 4/1/2008 CS152-Sring!08 6

4 Physical Register Management <> <> <> <> use ex o 1 P 2 P Rd LPRd PRd (LPRd requires third read ort on for each instruction) 4/1/2008 CS152-Sring!08 7 Physical Register Management <> <> <> <> use ex o 1 P 2 P Rd LPRd PRd x ld r1 4/1/2008 CS152-Sring!08 8

5 Physical Register Management <> <> <> <> use ex x o ld 1 P 2 P Rd r1 LPRd PRd x add r3 4/1/2008 CS152-Sring!08 9 Physical Register Management <> <> <> <> use ex x o ld 1 P 2 P Rd r1 LPRd PRd x add r3 x sub r6 4/1/2008 CS152-Sring!08 10

6 Physical Register Management <> <> <> <> use ex o 1 P 2 P Rd LPRd PRd x ld r1 x add r3 x sub r6 x add r3 4/1/2008 CS152-Sring!08 11 Physical Register Management <> <> <> <> use ex x o ld 1 P 2 P Rd r1 LPRd PRd x add r3 x sub r6 x add r3 x ld r6 4/1/2008 CS152-Sring!08 12

7 Physical Register Management <> <> <> <> <> use ex o 1 P 2 P Rd LPRd PRd x x ld r1 x add r3 x sub r6 x add r3 x ld r6 Execute & Commit 4/1/2008 CS152-Sring!08 13 Physical Register Management <> <> <> <> <> use ex o 1 P 2 P Rd LPRd PRd x x ld r1 x x add r3 x sub r6 x add r3 x ld r6 Execute & Commit 4/1/2008 CS152-Sring!08 14

8 CS152 Administrivia New shifted schedule - see website for details Lab 4, PS 4, due Tuesday Aril 8 PRIZE (TBD) for winners in both unlimited and realistic categories of branch redictor contest Quiz 4, Thursday Aril 10 Quiz 5, Thursday Aril 24 Quiz 6, Thursday May 8 (last day of class) 4/1/2008 CS152-Sring! /1/2008 CS152-Sring!08 16

9 4/1/2008 CS152-Sring!08 17 Reorder Buffer Holds Active Instruction Window (Older instructions) ld r1, (r3) add r3, r1, r2 sub r6, r7, r9 ld r6, (r1) add r6, r6, r3 st r6, (r1) ld r6, (r1) (Newer instructions) Commit Execute Fetch ld r1, (r3) add r3, r1, r2 sub r6, r7, r9 ld r6, (r1) add r6, r6, r3 st r6, (r1) ld r6, (r1) Cycle t Cycle t + 1 4/1/2008 CS152-Sring!08 18

10 Suerscalar Register Renaming During decode, instructions allocated new hysical destination register Source oerands renamed to hysical register with newest value Execution unit only sees hysical register numbers Inst 1 O Dest Src1 Src2 O Dest Src1 Src2 Inst 2 Udate Maing Write Ports Read Addresses Read Register O PDest PSrc1 PSrc2 O PDest PSrc1 PSrc2 Does this work? 4/1/2008 CS152-Sring!08 19 Suerscalar Register Renaming Inst 1 O Dest Src1 Src2 O Dest Src1 Src2 Inst 2 Udate Maing Must check for RAW hazards between instructions issuing in same cycle. Can be done in arallel with rename looku. O Write Ports Read Addresses Read PDest PSrc1 PSrc2 O =? =? PDest PSrc1 PSrc2 Register MIPS 0K renames 4 serially-raw-deendent insts/cycle 4/1/2008 CS152-Sring!08 20

11 Memory Deendencies st r1, (r2) ld r3, (r4) When can we execute the load? 4/1/2008 CS152-Sring!08 21 In-Order Memory Queue Execute all loads and stores in rogram order => Load and store cannot leave for execution until all revious loads and stores have comleted execution Can still execute loads and stores seculatively, and out-of-order with resect to other instructions 4/1/2008 CS152-Sring!08 22

12 Conservative O-o-O Load Execution st r1, (r2) ld r3, (r4) Slit execution of store instruction into two hases: address calculation and data write Can execute load before store, if addresses known and r4!= r2 Each load address comared with addresses of all revious uncommitted stores (can use artial conservative check i.e., bottom 12 bits of address) Don t execute load if any revious store address not known (MIPS 0K, 16 entry address queue) 4/1/2008 CS152-Sring!08 23 Address Seculation Guess that r4!= r2 st r1, (r2) ld r3, (r4) Execute load before store address known Need to hold all comleted but uncommitted load/store addresses in rogram order If subsequently find r4==r2, squash load and all following instructions => Large enalty for inaccurate address seculation 4/1/2008 CS152-Sring!08 24

13 Memory Deendence Prediction (Alha 21264) st r1, (r2) ld r3, (r4) Guess that r4!= r2 and execute load before store If later find r4==r2, squash load and all following instructions, but mark load instruction as store-wait Subsequent executions of the same load instruction will wait for all revious stores to comlete Periodically clear store-wait bits 4/1/2008 CS152-Sring!08 25 Seculative Loads / Stores Just like register udates, stores should not modify the memory until after the instruction is committed - A seculative store buffer is a structure introduced to hold seculative store data. 4/1/2008 CS152-Sring!08 26

14 Seculative Store Buffer Seculative Store Buffer Load Address s Store Commit Path L1 Cache Load On store execute: mark entry valid and seculative, and save data and tag of instruction. On store commit: clear seculative bit and eventually move data to cache On store abort: clear valid bit 4/1/2008 CS152-Sring!08 27 Seculative Store Buffer Seculative Store Buffer Load Address s Store Commit Path L1 Cache Load If data in both store buffer and cache, which should we use? Seculative store buffer If same address in store buffer twice, which should we use? Youngest store older than load 4/1/2008 CS152-Sring!08 28

15 ath: Branch Prediction and Seculative Execution PC Branch Prediction Fetch Decode & Branch Resolution Reorder Buffer Udate redictors Commit Reg. File Branch Unit Execute ALU MEM Store Buffer 4/1/2008 CS152-Sring!08 29 D$ Acknowledgements These slides contain material develoed and coyright by: Arvind (MIT) Krste Asanovic (MIT/UCB) Joel Emer (Intel/MIT) James Hoe (CMU) John Kubiatowicz (UCB) David Patterson (UCB) MIT material derived from course UCB material derived from course CS252 4/1/2008 CS152-Sring!08 30