EECS 583 Class 9 Classic Optimization

Size: px
Start display at page:

Download "EECS 583 Class 9 Classic Optimization"

Transcription

1 EECS 583 Class 9 Classic Optimization University of Michigan September 28, 2016

2 Generalizing Dataflow Analysis Transfer function» How information is changed by something (BB)» OUT = GEN + (IN KILL) /* forward analysis */» IN = GEN + (OUT KILL) /* backward analysis */ Meet function» How information from multiple paths is combined» IN = Union(OUT(predecessors)) /* forward analysis */» OUT = Union(IN(successors)) /* backward analysis */ Generalized dataflow algorithm» while (change) Ÿ change = false Ÿ for each BB apply meet function apply transfer functions if any changes à change = true - 1 -

3 What About All Path Problems? Up to this point» Any path problems (maybe relations) Ÿ Definition reaches along some path Ÿ Some sequence of branches in which def reaches Ÿ Lots of defs of the same variable may reach a point» Use of Union operator in meet function All-path: Definition guaranteed to reach» Regardless of sequence of branches taken, def reaches» Can always count on this» Only 1 def can be guaranteed to reach» Availability (as opposed to reaching) Ÿ Available definitions Ÿ Available expressions (could also have reaching expressions, but not that useful) - 2 -

4 Reaching vs Available Definitions 1:r1 = r2 + r3 2:r6 = r4 r5 1,2 reach 1,2 available 1,2 reach 1,2 available 3:r4 = 4 4:r6 = 8 5:r6 = r2 + r3 6:r7 = r4 r5 1,2,3,4 reach 1 available 1,3,4 reach 1,3,4 available - 3 -

5 Available Definition Analysis (Adefs) A definition d is available at a point p if along all paths from d to p, d is not killed Remember, a definition of a variable is killed between 2 points when there is another definition of that variable along the path» r1 = r2 + r3 kills previous definitions of r1 Algorithm» Forward dataflow analysis as propagation occurs from defs downwards» Use the Intersect function as the meet operator to guarantee the all-path requirement» GEN/KILL/IN/OUT similar to reaching defs Ÿ Initialization of IN/OUT is the tricky part - 4 -

6 Compute GEN/KILL Sets for each BB (Adefs) Exactly the same as reaching defs!!! for each basic block in the procedure, X, do GEN(X) = 0 KILL(X) = 0 for each operation in sequential order in X, op, do for each destination operand of op, dest, do G = op K = {all ops which define dest op} GEN(X) = G + (GEN(X) K) KILL(X) = K + (KILL(X) G) endfor endfor endfor - 5 -

7 Compute IN/OUT Sets for all BBs (Adefs) U = universal set of all operations in the Procedure IN(0) = 0 OUT(0) = GEN(0) for each basic block in procedure, W, (W!= 0), do IN(W) = 0 OUT(W) = U KILL(W) change = 1 while (change) do change = 0 for each basic block in procedure, X, do old_out = OUT(X) IN(X) = Intersect(OUT(Y)) for all predecessors Y of X OUT(X) = GEN(X) + (IN(X) KILL(X)) if (old_out!= OUT(X)) then change = 1 endif endfor endfor - 6 -

8 Available Expression Analysis (Aexprs) An expression is a RHS of an operation» r2 = r3 + r4, r3+r4 is an expression An expression e is available at a point p if along all paths from e to p, e is not killed An expression is killed between 2 points when one of its source operands are redefined» r1 = r2 + r3 kills all expressions involving r1 Algorithm» Forward dataflow analysis as propagation occurs from defs downwards» Use the Intersect function as the meet operator to guarantee the all-path requirement» Looks exactly like adefs, except GEN/KILL/IN/OUT are the RHS s of operations rather than the LHS s - 7 -

9 Computation of Aexpr GEN/KILL Sets We can also formulate the GEN/KILL slightly differently so you do not need to break up instructions like r2 = r for each basic block in the procedure, X, do GEN(X) = 0 KILL(X) = 0 for each operation in sequential order in X, op, do K = 0 for each destination operand of op, dest, do K += {all ops which use dest} endfor if (op not in K) G = op else G = 0 GEN(X) = G + (GEN(X) K) KILL(X) = K + (KILL(X) G) endfor endfor - 8 -

10 Class Problem - Aexprs Calculation 1: r1 = r6 * r9 2: r2 = r : r5 = r3 * r4 4: r1 = r : r3 = r3 * r4 6: r8 = r3 * 2 7: r7 = r3 * r4 8: r1 = r : r7 = r1-6 10: r8 = r : r1 = r3 * r4 12: r3 = r6 * r9-9 -

11 Dataflow Analyses in 1 Slide Liveness OUT = Union(IN(succs)) IN = GEN + (OUT KILL) Reaching Definitions/DU/UD IN = Union(OUT(preds)) OUT = GEN + (IN KILL) Bottom-up dataflow Any path Keep track of variables/registers Uses of variables à GEN Defs of variables à KILL Available Expressions Top-down dataflow Any path Keep track of instruction IDs Defs of variables à GEN Defs of variables à KILL Available Definitions IN = Intersect(OUT(preds)) OUT = GEN + (IN KILL) Top-down dataflow All path Keep track of instruction IDs Expressions of variables à GEN Defs of variables à KILL IN = Intersect(OUT(preds)) OUT = GEN + (IN KILL) Top-down dataflow All path Keep track of instruction IDs Defs of variables à GEN Defs of variables à KILL

12 Some Things to Think About Liveness and rdefs are basically the same thing» All dataflow is basically the same with a few parameters Ÿ Meaning of gen/kill src vs dest, variable vs operation Ÿ Backward / Forward Ÿ All paths / some paths (must/may) Ÿ What other dataflow analysis problems can be formulated? Dataflow can be slow» How to implement it efficiently? Ÿ Forward analysis DFS order Ÿ Backward analysis PostDFS order» How to represent the info? Predicates» Throw a monkey wrench into this stuff» So, how are predicates handled?

13 Code Optimization

14 Code Optimization Make the code run faster on the target processor» Other objectives: Power, code size Classes of optimization» 1. Classical (machine independent) Ÿ Reducing operation count (redundancy elimination) Ÿ Simplifying operations Ÿ Generally good for any kind of machine» 2. Machine specific Ÿ Peephole optimizations Ÿ Take advantage of specialized hardware features» 3. Parallelism enhancing Ÿ Increasing parallelism (ILP or TLP) Ÿ Possibly increase instructions

15 A Tour Through the Classical Optimizations For this class Go over concepts of a small subset of the optimizations» What it is, why its useful» When can it be applied (set of conditions that must be satisfied)» How it works» Give you the flavor but don t want to beat you over the head Challenges» Register pressure?» Parallelism verses operation count

16 Dead Code Elimination Remove any operation whose result is never consumed Rules» X can be deleted Ÿ no stores or branches» DU chain empty or dest register not live This misses some dead code» Especially in loops» Critical operation Ÿ store or branch operation» Any operation that does not directly or indirectly feed a critical operation is dead» Trace UD chains backwards from critical operations» Any op not visited is dead r1 = 3 r2 = 10 r4 = r4 + 1 r7 = r1 * r4 r2 = 0 r3 = r3 + 1 r3 = r2 + r1 store (r1, r3)

17 Local Constant Propagation Forward propagation of moves of the form» rx = L (where L is a literal)» Maximally propagate Consider 2 ops, X and Y in a BB, X is before Y» 1. X is a move» 2. src1(x) is a literal» 3. Y consumes dest(x)» 4. There is no definition of dest(x) between X and Y» 5. No danger betw X and Y Ÿ When dest(x) is a Macro reg, BRL destroys the value r1 = 5 r2 = _x r3 = 7 r4 = r4 + r1 r1 = r1 + r2 r1 = r1 + 1 r3 = 12 r8 = r1 - r2 r9 = r3 + r5 r3 = r2 + 1 r10 = r3 r1 Note, ignore operation format issues, so all operations can have literals in either operand position

18 Global Constant Propagation Consider 2 ops, X and Y in different BBs» 1. X is a move» 2. src1(x) is a literal» 3. Y consumes dest(x)» 4. X is in a_in(bb(y))» 5. Dest(x) is not modified between the top of BB(Y) and Y» 6. No danger betw X and Y Ÿ When dest(x) is a Macro reg, BRL destroys the value r1 = r1 + r2 r1 = 5 r2 = _x r8 = r1 * r2 r7 = r1 r2 r9 = r1 + r2-17 -

19 Constant Folding Simplify 1 operation based on values of src operands» Constant propagation creates opportunities for this All constant operands» Evaluate the op, replace with a move Ÿ r1 = 3 * 4 à r1 = 12 Ÿ r1 = 3 / 0 à??? Don t evaluate excepting ops!, what about floating-point?» Evaluate conditional branch, replace with BRU or noop Ÿ if (1 < 2) goto BB2 à BRU BB2 Ÿ if (1 > 2) goto BB2 à convert to a noop Algebraic identities» r1 = r2 + 0, r2 0, r2 0, r2 ^ 0, r2 << 0, r2 >> 0 Ÿ r1 = r2» r1 = 0 * r2, 0 / r2, 0 & r2 Ÿ r1 = 0» r1 = r2 * 1, r2 / 1 Ÿ r1 = r2-18 -

20 Class Problem r1 = 0 r2 = 10 r3 = 0 Optimize this applying 1. constant propagation 2. constant folding r4 = 1 r7 = r1 * 4 r6 = 8 if (r3 > 0) r2 = 0 r6 = r6 * r7 r3 = r2 / r6 r3 = r4 r3 = r3 + r2 r1 = r6 r2 = r2 + 1 r1 = r1 + 1 if (r1 < 100) store (r1, r3)

21 Forward Copy Propagation Forward propagation of the RHS of moves» r1 = r2»» r4 = r1 + 1 à r4 = r2 + 1 Benefits» Reduce chain of dependences» Eliminate the move Rules (ops X and Y)» X is a move» src1(x) is a register» Y consumes dest(x)» X.dest is an available def at Y» X.src1 is an available expr at Y r1 = r2 r3 = r4 r2 = 0 r6 = r3 + 1 r5 = r2 + r3-20 -

22 CSE Common Subexpression Elimination Eliminate recomputation of an expression by reusing the previous result» r1 = r2 * r3» à r100 = r1»» r4 = r2 * r3 à r4 = r100 Benefits» Reduce work» Moves can get copy propagated Rules (ops X and Y)» X and Y have the same opcode» src(x) = src(y), for all srcs» expr(x) is available at Y» if X is a load, then there is no store that may write to address(x) along any path between X and Y r1 = r2 * r6 r3 = r4 / r7 r2 = r2 + 1 r6 = r3 * 7 r5 = r2 * r6 r8 = r4 / r7 r9 = r3 * 7 if op is a load, call it redundant load elimination rather than CSE

23 Class Problem r4 = r1 r6 = r15 r2 = r3 * r4 r8 = r2 + r5 r9 = r3 r7 = load(r2) if (r2 > r8) Optimize this applying 1. dead code elimination 2. forward copy propagation 3. CSE r5 = r9 * r4 r11 = r2 r12 = load(r11) if (r12!= 0) r3 = load(r2) r10 = r3 / r6 r11 = r8 store (r11, r7) store (r12, r3)

24 Loop Invariant Code Motion (LICM) Move operations whose source operands do not change within the loop to the loop preheader» Execute them only 1x per invocation of the loop» Be careful with memory operations!» Be careful with ops not executed every iteration r8 = r2 + 1 r7 = r8 * r4 r1 = 3 r5 = &A r4 = load(r5) r7 = r4 * 3 r3 = r2 + 1 r1 = r1 + r7 store (r1, r3)

25 LICM (2) Rules» X can be moved» src(x) not modified in loop body» X is the only op to modify dest(x)» for all uses of dest(x), X is in the available defs set» for all exit BB, if dest(x) is live on the exit edge, X is in the available defs set on the edge» if X not executed on every iteration, then X must provably not cause exceptions» if X is a load or store, then there are no writes to address(x) in loop r8 = r2 + 1 r7 = r8 * r4 r1 = 3 r5 = &A r4 = load(r5) r7 = r4 * 3 r3 = r2 + 1 r1 = r1 + r7 Homework 2 eliminates the last rule. You can also ignore the executed on every iteration rule for SpecLICM. store (r1, r3)

26 Global Variable Migration Assign a global variable temporarily to a register for the duration of the loop» Load in preheader» Store at exit points Rules» X is a load or store» address(x) not modified in the loop» if X not executed on every iteration, then X must provably not cause an exception» All memory ops in loop whose address can equal address(x) must always have the same address as X r8 = load(r5) r7 = r8 * r4 r4 = load(r5) r4 = r4 + 1 store(r5,r7) store(r5, r4)

27 Induction Variable Strength Reduction Create basic induction variables from derived induction variables Induction variable» BIV (i++) Ÿ 0,1,2,3,4,...» DIV (j = i * 4) Ÿ 0, 4, 8, 12, 16,...» DIV can be converted into a BIV that is incremented by 4 Issues» Initial and increment vals» Where to place increments r5 = r4-3 r4 = r4 + 1 r6 = r4 << 2 r7 = r4 * r9-26 -

28 Induction Variable Strength Reduction (2) Rules» X is a *, <<, + or operation» src1(x) is a basic ind var» src2(x) is invariant» No other ops modify dest(x)» dest(x)!= src(x) for all srcs» dest(x) is a register Transformation» Insert the following into the preheader Ÿ new_reg = RHS(X)» If opcode(x) is not add/sub, insert to the bottom of the preheader Ÿ new_inc = inc(src1(x)) opcode(x) src2(x)» else Ÿ new_inc = inc(src1(x))» Insert the following at each update of src1(x) Ÿ new_reg += new_inc» Change X à dest(x) = new_reg r5 = r4-3 r4 = r4 + 1 r6 = r4 << 2 r7 = r4 * r9-27 -

29 Class Problem r1 = 0 r2 = 0 Optimize this applying induction var str reduction r5 = r5 + 1 r11 = r5 * 2 r10 = r r12 = load (r10+0) r9 = r1 << 1 r4 = r9-10 r3 = load(r4+4) r3 = r3 + 1 store(r4+0, r3) r7 = r3 << 2 r6 = load(r7+0) r13 = r2-1 r1 = r1 + 1 r2 = r2 + 1 r13, r12, r6, r10 liveout

30 ILP Optimization Traditional optimizations» Redundancy elimination» Reducing operation count ILP (instruction-level parallelism) optimizations» Increase the amount of parallelism and the ability to overlap operations» Operation count is secondary, often trade parallelism for extra instructions (avoid code explosion) ILP increased by breaking dependences» True or flow = read after write dependence» False or (anti/output) = write after read, write after write

31 Back Substitution Generation of expressions by compiler frontends is very sequential» Account for operator precedence» Apply left-to-right within same precedence Back substitution» Create larger expressions Ÿ Iteratively substitute RHS expression for LHS variable» Note may correspond to multiple source statements» Enable subsequent optis Optimization» Re-compute expression in a more favorable manner y = a + b + c d + e f; r9 = r1 + r2 r10 = r9 + r3 r11 = r10 - r4 r12 = r11 + r5 r13 = r12 r6 Subs r12: r13 = r11 + r5 r6 Subs r11: r13 = r10 r4 + r5 r6 Subs r10 r13 = r9 + r3 r4 + r5 r6 Subs r9 r13 = r1 + r2 + r3 r4 + r5 r6

32 Tree Height Reduction Re-compute expression as a balanced binary tree» Obey precedence rules» Essentially re-parenthesize» Combine literals if possible Effects» Height reduced (n terms) Ÿ n-1 (assuming unit latency) Ÿ ceil(log2(n))» Number of operations remains constant» Cost Ÿ Temporary registers live longer» Watch out for Ÿ Always ok for integer arithmetic Ÿ Floating-point may not be!! original: r9 = r1 + r2 r10 = r9 + r3 r11 = r10 - r4 r12 = r11 + r5 r13 = r12 r6 after back subs: r13 = r1 + r2 + r3 r4 + r5 r6 r1 + r2 r3 r4 r5 r6 + + r13 final code: t1 = r1 + r2 t2 = r3 r4 t3 = r5 r6 t4 = t1 + t2 r13 = t4 + t3-31 -

33 Class Problem Assume: + = 1, * = 3 operand arrival times 0 r1 0 r2 0 r3 1 r4 2 r5 0 r6 r10 = r1 * r2 r11 = r10 + r3 r12 = r11 + r4 r13 = r12 r5 r14 = r13 + r6 Back susbstitute Re-express in tree-height reduced form Account for latency and arrival times

34 Optimizing Unrolled Loops loop: r1 = load(r2) r3 = load(r4) r5 = r1 * r3 r6 = r6 + r5 r2 = r2 + 4 r4 = r4 + 4 if (r4 < 400) goto loop Unroll = replicate loop body n-1 times. Hope to enable overlap of operation execution from different iterations Not possible! unroll 3 times loop: iter1 iter2 iter3 r1 = load(r2) r3 = load(r4) r5 = r1 * r3 r6 = r6 + r5 r2 = r2 + 4 r4 = r4 + 4 r1 = load(r2) r3 = load(r4) r5 = r1 * r3 r6 = r6 + r5 r2 = r2 + 4 r4 = r4 + 4 r1 = load(r2) r3 = load(r4) r5 = r1 * r3 r6 = r6 + r5 r2 = r2 + 4 r4 = r4 + 4 if (r4 < 400) goto loop

35 Register Renaming on Unrolled Loop loop: iter1 r1 = load(r2) r3 = load(r4) r5 = r1 * r3 r6 = r6 + r5 r2 = r2 + 4 r4 = r4 + 4 loop: iter1 r1 = load(r2) r3 = load(r4) r5 = r1 * r3 r6 = r6 + r5 r2 = r2 + 4 r4 = r4 + 4 iter2 r1 = load(r2) r3 = load(r4) r5 = r1 * r3 r6 = r6 + r5 r2 = r2 + 4 r4 = r4 + 4 iter2 r11 = load(r2) r13 = load(r4) r15 = r11 * r13 r6 = r6 + r15 r2 = r2 + 4 r4 = r4 + 4 iter3 r1 = load(r2) r3 = load(r4) r5 = r1 * r3 r6 = r6 + r5 r2 = r2 + 4 r4 = r4 + 4 if (r4 < 400) goto loop iter3 r21 = load(r2) r23 = load(r4) r25 = r21 * r23 r6 = r6 + r25 r2 = r2 + 4 r4 = r4 + 4 if (r4 < 400) goto loop

36 Register Renaming is Not Enough! loop: iter1 iter2 iter3 r1 = load(r2) r3 = load(r4) r5 = r1 * r3 r6 = r6 + r5 r2 = r2 + 4 r4 = r4 + 4 r11 = load(r2) r13 = load(r4) r15 = r11 * r13 r6 = r6 + r15 r2 = r2 + 4 r4 = r4 + 4 r21 = load(r2) r23 = load(r4) r25 = r21 * r23 r6 = r6 + r25 r2 = r2 + 4 r4 = r4 + 4 if (r4 < 400) goto loop Still not much overlap possible Problems» r2, r4, r6 sequentialize the iterations» Need to rename these 2 specialized renaming optis» Accumulator variable expansion (r6)» Induction variable expansion (r2, r4)

37 Accumulator Variable Expansion loop: iter1 iter2 iter3 r16 = r26 = 0 r1 = load(r2) r3 = load(r4) r5 = r1 * r3 r6 = r6 + r5 r2 = r2 + 4 r4 = r4 + 4 r11 = load(r2) r13 = load(r4) r15 = r11 * r13 r16 = r16 + r15 r2 = r2 + 4 r4 = r4 + 4 r21 = load(r2) r23 = load(r4) r25 = r21 * r23 r26 = r26 + r25 r2 = r2 + 4 r4 = r4 + 4 if (r4 < 400) goto loop r6 = r6 + r16 + r Accumulator variable» x = x + y or x = x y» where y is loop variant!! Create n-1 temporary accumulators Each iteration targets a different accumulator Sum up the accumulator variables at the end May not be safe for floatingpoint values

38 Induction Variable Expansion loop: iter1 iter2 iter3 r12 = r2 + 4, r22 = r2 + 8 r14 = r4 + 4, r24 = r4 + 8 r16 = r26 = 0 r1 = load(r2) r3 = load(r4) r5 = r1 * r3 r6 = r6 + r5 r2 = r r4 = r r11 = load(r12) r13 = load(r14) r15 = r11 * r13 r16 = r16 + r15 r12 = r r14 = r r21 = load(r22) r23 = load(r24) r25 = r21 * r23 r26 = r26 + r25 r22 = r r24 = r if (r4 < 400) goto loop r6 = r6 + r16 + r Induction variable» x = x + y or x = x y» where y is loop invariant!! Create n-1 additional induction variables Each iteration uses and modifies a different induction variable Initialize induction variables to init, init+step, init+2*step, etc. Step increased to n*original step Now iterations are completely independent!!

39 Better Induction Variable Expansion loop: iter1 iter2 r16 = r26 = 0 r1 = load(r2) r3 = load(r4) r5 = r1 * r3 r6 = r6 + r5 r11 = load(r2+4) r13 = load(r4+4) r15 = r11 * r13 r16 = r16 + r15 With base+displacement addressing, often don t need additional induction variables» Just change offsets in each iterations to reflect step» Change final increments to n * original step iter3 r21 = load(r2+8) r23 = load(r4+8) r25 = r21 * r23 r26 = r26 + r25 r2 = r r4 = r if (r4 < 400) goto loop r6 = r6 + r16 + r

40 Homework Problem loop: r1 = load(r2) r5 = r6 + 3 r6 = r5 + r1 r2 = r2 + 4 if (r2 < 400) goto loop Optimize the unrolled loop Renaming Tree height reduction Ind/Acc expansion loop: r1 = load(r2) r5 = r6 + 3 r6 = r5 + r1 r2 = r2 + 4 r1 = load(r2) r5 = r6 + 3 r6 = r5 + r1 r2 = r2 + 4 r1 = load(r2) r5 = r6 + 3 r6 = r5 + r1 r2 = r2 + 4 if (r2 < 400) goto loop

Code Generation Part III

Code Generation Part III 1 Code Generation Part III Chapters 8 and 9.1 (1 st ed. Ch.9) COP5621 Compiler Construction Copyright Robert van Engelen, Florida State University, 2007-2013 2 Classic Examples of Local and Global Code

More information

Lecture 14: Instruction Level Parallelism

Lecture 14: Instruction Level Parallelism Lecture 14: Instruction Level Parallelism Last time Pipelining in the real world Today Control hazards Other pipelines Take QUIZ 10 over P&H 4.10-15, before 11:59pm today Homework 5 due Thursday March

More information

Advanced Superscalar Architectures. Speculative and Out-of-Order Execution

Advanced Superscalar Architectures. Speculative and Out-of-Order Execution 6.823, L16--1 Advanced Superscalar Architectures Asanovic Laboratory for Computer Science M.I.T. http://www.csg.lcs.mit.edu/6.823 Speculative and Out-of-Order Execution Branch Prediction kill kill Branch

More information

Parallelism I: Inside the Core

Parallelism I: Inside the Core Parallelism I: Inside the Core 1 The final Comprehensive Same general format as the Midterm. Review the homeworks, the slides, and the quizzes. 2 Key Points What is wide issue mean? How does does it affect

More information

Computer Architecture 计算机体系结构. Lecture 3. Instruction-Level Parallelism I 第三讲 指令级并行 I. Chao Li, PhD. 李超博士

Computer Architecture 计算机体系结构. Lecture 3. Instruction-Level Parallelism I 第三讲 指令级并行 I. Chao Li, PhD. 李超博士 Computer Architecture 计算机体系结构 Lecture 3. Instruction-Level Parallelism I 第三讲 指令级并行 I Chao Li, PhD. 李超博士 SJTU-SE346, Spring 2018 Review ISA, micro-architecture, physical design Evolution of ISA CISC vs

More information

COSC 6385 Computer Architecture. - Tomasulos Algorithm

COSC 6385 Computer Architecture. - Tomasulos Algorithm COSC 6385 Computer Architecture - Tomasulos Algorithm Fall 2008 Analyzing a short code-sequence DIV.D F0, F2, F4 ADD.D F6, F0, F8 S.D F6, 0(R1) SUB.D F8, F10, F14 MUL.D F6, F10, F8 1 Analyzing a short

More information

Programming Languages (CS 550)

Programming Languages (CS 550) Programming Languages (CS 550) Mini Language Compiler Jeremy R. Johnson 1 Introduction Objective: To illustrate how to map Mini Language instructions to RAL instructions. To do this in a systematic way

More information

Computer Architecture: Out-of-Order Execution. Prof. Onur Mutlu (editted by Seth) Carnegie Mellon University

Computer Architecture: Out-of-Order Execution. Prof. Onur Mutlu (editted by Seth) Carnegie Mellon University Computer Architecture: Out-of-Order Execution Prof. Onur Mutlu (editted by Seth) Carnegie Mellon University Reading for Today Smith and Sohi, The Microarchitecture of Superscalar Processors, Proceedings

More information

Pipelining A B C D. Readings: Example: Doing the laundry. Ann, Brian, Cathy, & Dave. each have one load of clothes to wash, dry, and fold

Pipelining A B C D. Readings: Example: Doing the laundry. Ann, Brian, Cathy, & Dave. each have one load of clothes to wash, dry, and fold Pipelining Readings: 4.5-4.8 Example: Doing the laundry Ann, Brian, Cathy, & Dave A B C D each have one load of clothes to wash, dry, and fold Washer takes 30 minutes Dryer takes 40 minutes Folder takes

More information

Anne Bracy CS 3410 Computer Science Cornell University. [K. Bala, A. Bracy, S. McKee, E. Sirer, H. Weatherspoon]

Anne Bracy CS 3410 Computer Science Cornell University. [K. Bala, A. Bracy, S. McKee, E. Sirer, H. Weatherspoon] Anne Bracy CS 3410 Computer Science Cornell University [K. Bala, A. Bracy, S. McKee, E. Sirer, H. Weatherspoon] Prog. Mem PC +4 inst Reg. File 5 5 5 control ALU Data Mem Fetch Decode Execute Memory WB

More information

DAT105: Computer Architecture Study Period 2, 2009 Exercise 2 Chapter 2: Instruction-Level Parallelism and Its Exploitation

DAT105: Computer Architecture Study Period 2, 2009 Exercise 2 Chapter 2: Instruction-Level Parallelism and Its Exploitation Study Period 2, 29 Exercise 2 Chapter 2: Instruction-Level Parallelism and Its Exploitation Mafijul Islam Department of Computer Science and Engineering November 12, 29 Study Period 2, 29 Goals: To understand

More information

Out-of-order Pipeline. Register Read. OOO execution (2-wide) OOO execution (2-wide) OOO execution (2-wide) OOO execution (2-wide)

Out-of-order Pipeline. Register Read. OOO execution (2-wide) OOO execution (2-wide) OOO execution (2-wide) OOO execution (2-wide) Out-of-order Pipeline Register Read When do instructions read the register file? Fetch Decode Rename Dispatch Buffer of instructions Issue Reg-read Execute Writeback Commit Option #: after select, right

More information

Code Scheduling & Limitations

Code Scheduling & Limitations This Unit: Static & Dynamic Scheduling CIS 371 Computer Organization and Design Unit 11: Static and Dynamic Scheduling App App App System software Mem CPU I/O Code scheduling To reduce pipeline stalls

More information

ECE 550D Fundamentals of Computer Systems and Engineering. Fall 2017

ECE 550D Fundamentals of Computer Systems and Engineering. Fall 2017 ECE 550D Fundamentals of Computer Systems and Engineering Fall 2017 Digital Arithmetic Prof. John Board Duke University Slides are derived from work by Profs. Tyler Bletch and Andrew Hilton (Duke) Last

More information

VHDL (and verilog) allow complex hardware to be described in either single-segment style to two-segment style

VHDL (and verilog) allow complex hardware to be described in either single-segment style to two-segment style FFs and Registers In this lecture, we show how the process block is used to create FFs and registers Flip-flops (FFs) and registers are both derived using our standard data types, std_logic, std_logic_vector,

More information

Using Advanced Limit Line Features

Using Advanced Limit Line Features Application Note Using Advanced Limit Line Features MS2717B, MS2718B, MS2719B, MS2723B, MS2724B, MS2034A, MS2036A, and MT8222A Economy Microwave Spectrum Analyzer, Spectrum Master, and BTS Master The limit

More information

Optimality of Tomasulo s Algorithm Luna, Dong Gang, Zhao

Optimality of Tomasulo s Algorithm Luna, Dong Gang, Zhao Optimality of Tomasulo s Algorithm Luna, Dong Gang, Zhao Feb 28th, 2002 Our Questions about Tomasulo Questions about Tomasulo s Algorithm Is it optimal (can always produce the wisest instruction execution

More information

CIS 371 Computer Organization and Design

CIS 371 Computer Organization and Design CIS 371 Computer Organization and Design Unit 10: Static & Dynamic Scheduling Slides developed by Milo Martin & Amir Roth at the University of Pennsylvania with sources that included University of Wisconsin

More information

CIS 371 Computer Organization and Design

CIS 371 Computer Organization and Design CIS 371 Computer Organization and Design Unit 10: Static & Dynamic Scheduling Slides developed by M. Martin, A.Roth, C.J. Taylor and Benedict Brown at the University of Pennsylvania with sources that included

More information

Rule-based Integration of Multiple Neural Networks Evolved Based on Cellular Automata

Rule-based Integration of Multiple Neural Networks Evolved Based on Cellular Automata 1 Robotics Rule-based Integration of Multiple Neural Networks Evolved Based on Cellular Automata 2 Motivation Construction of mobile robot controller Evolving neural networks using genetic algorithm (Floreano,

More information

Advanced Superscalar Architectures

Advanced Superscalar Architectures Advanced Suerscalar Architectures Krste Asanovic Laboratory for Comuter Science Massachusetts Institute of Technology Physical Register Renaming (single hysical register file: MIPS R10K, Alha 21264, Pentium-4)

More information

Unit 9: Static & Dynamic Scheduling

Unit 9: Static & Dynamic Scheduling CIS 501: Computer Architecture Unit 9: Static & Dynamic Scheduling Slides originally developed by Drew Hilton, Amir Roth and Milo Mar;n at University of Pennsylvania CIS 501: Comp. Arch. Prof. Milo Martin

More information

Announcements. Programming assignment #2 due Monday 9/24. Talk: Architectural Acceleration of Real Time Physics Glenn Reinman, UCLA CS

Announcements. Programming assignment #2 due Monday 9/24. Talk: Architectural Acceleration of Real Time Physics Glenn Reinman, UCLA CS Lipasti, artin, Roth, Shen, Smith, Sohi, Tyson, Vijaykumar GAS STATION Pipelining II Fall 2007 Prof. Thomas Wenisch http://www.eecs.umich.edu/courses/eecs470 Slides developed in part by Profs. Austin,

More information

index changing a variable s value, Chime My Block, clearing the screen. See Display block CoastBack program, 54 44

index changing a variable s value, Chime My Block, clearing the screen. See Display block CoastBack program, 54 44 index A absolute value, 103, 159 adding labels to a displayed value, 108 109 adding a Sequence Beam to a Loop of Switch block, 223 228 algorithm, defined, 86 ambient light, measuring, 63 analyzing data,

More information

FabComp: Hardware specication

FabComp: Hardware specication Sol Boucher and Evan Klei CSCI-453-01 04/28/14 FabComp: Hardware specication 1 Hardware The computer is composed of a largely isolated data unit and control unit, which are only connected by a couple of

More information

Automatic Electronic Sectionalizing

Automatic Electronic Sectionalizing 2.1 Electronic Sectionalizing OPTIMAL ELECTRONIC PROTECTION - NO REPLACEABLE ELEMENTS. FULLY COMPATIBLE WITH CERAMIC AND POLIMERIC BASES BY ANY MANUFACTURER. SINGLE-POLE AND ELECTRONIC THREE-POLE VERSIONS

More information

HARDWIRE VS. WIRELESS FAILSAFE CONTROL SYSTEM. The answer is No.

HARDWIRE VS. WIRELESS FAILSAFE CONTROL SYSTEM. The answer is No. HARDWIRE VS. WIRELESS FAILSAFE CONTROL SYSTEM In today s industrial automation world, the debate continues Is wire more reliable then wireless? The answer is No. In any industrial control environment,

More information

Warped-Compression: Enabling Power Efficient GPUs through Register Compression

Warped-Compression: Enabling Power Efficient GPUs through Register Compression WarpedCompression: Enabling Power Efficient GPUs through Register Compression Sangpil Lee, Keunsoo Kim, Won Woo Ro (Yonsei University*) Gunjae Koo, Hyeran Jeon, Murali Annavaram (USC) (*Work done while

More information

Lecture 20: Parallelism ILP to Multicores. James C. Hoe Department of ECE Carnegie Mellon University

Lecture 20: Parallelism ILP to Multicores. James C. Hoe Department of ECE Carnegie Mellon University 18 447 Lecture 20: Parallelism ILP to Multicores James C. Hoe Department of ECE Carnegie Mellon University 18 447 S18 L20 S1, James C. Hoe, CMU/ECE/CALCM, 2018 18 447 S18 L20 S2, James C. Hoe, CMU/ECE/CALCM,

More information

Freescale Cup Competition. Abdulahi Abu Amber Baruffa Mike Diep Xinya Zhao. Author: Amber Baruffa

Freescale Cup Competition. Abdulahi Abu Amber Baruffa Mike Diep Xinya Zhao. Author: Amber Baruffa Freescale Cup Competition The Freescale Cup is a global competition where student teams build, program, and race a model car around a track for speed. Abdulahi Abu Amber Baruffa Mike Diep Xinya Zhao The

More information

Pipelined MIPS Datapath with Control Signals

Pipelined MIPS Datapath with Control Signals uction ess uction Rs [:26] (Opcode[5:]) [5:] ranch luor. Decoder Pipelined MIPS path with Signals luor Raddr at Five instruction sequence to be processed by pipeline: op [:26] rs [25:2] rt [2:6] rd [5:]

More information

ME 455 Lecture Ideas, Fall 2010

ME 455 Lecture Ideas, Fall 2010 ME 455 Lecture Ideas, Fall 2010 COURSE INTRODUCTION Course goal, design a vehicle (SAE Baja and Formula) Half lecture half project work Group and individual work, integrated Design - optimal solution subject

More information

FUELTRAX SET THE STANDARD. March 2018

FUELTRAX SET THE STANDARD. March 2018 FUELTRAX SET THE STANDARD March 2018 MARITIME ECONOMIC CHALLENGES Increasingly challenging times for maritime industries Marine vessel stakeholders (operators, managers, owners, charterers, et al.) are

More information

Isaac Newton vs. Red Light Cameras

Isaac Newton vs. Red Light Cameras 2012 Isaac Newton vs. Red Light Cameras Approach Speed vs. Speed Limit Brian Cecvehicleelli redlightrobber.com 3/1/2012 Table of Contents Approach Speed vs. Speed Limit... 3 Definition of Speed Limit...

More information

PCT200 Powercast High-Function RFID Sensor Datalogger

PCT200 Powercast High-Function RFID Sensor Datalogger DESCRIPTION The PCT200 SuperTag is a high-functioning, datalogging RFID tag capable of measuring temperature, humidity, and light level with high accuracy. It contains a wirelessly rechargeable battery

More information

The electrohydraulic brake

The electrohydraulic brake The electrohydraulic brake The electrohydraulic brake corresponds to an architecture for which: Brake control is ensured in a purely electric way Actuation energy (providing brake force or ensuring brake

More information

RR Concepts. The StationMaster can control DC trains or DCC equipped trains set to linear mode.

RR Concepts. The StationMaster can control DC trains or DCC equipped trains set to linear mode. Jan, 0 S RR Concepts M tation aster - 5 Train Controller - V software This manual contains detailed hookup and programming instructions for the StationMaster train controller available in a AMP or 0AMP

More information

EECS 461 Final Project: Adaptive Cruise Control

EECS 461 Final Project: Adaptive Cruise Control EECS 461 Final Project: Adaptive Cruise Control 1 Overview Many automobiles manufactured today include a cruise control feature that commands the car to travel at a desired speed set by the driver. In

More information

Bringing ARB_gpu_shader_fp64 to Intel GPUs

Bringing ARB_gpu_shader_fp64 to Intel GPUs Bringing ARB_gpu_shader_fp64 to Intel GPUs Iago Toral Quiroga XDC 2016 Helsinki, Finland ARB_gpu_shader_fp64 Overview Scope Intel implementation NIR i965 Current status Contents ARB_gpu_shader_fp64

More information

INSTRUCTIONS FOR TRI-METRIC BATTERY MONITOR May 8, 1996

INSTRUCTIONS FOR TRI-METRIC BATTERY MONITOR May 8, 1996 INSTRUCTIONS FOR TRI-METRIC BATTERY MONITOR May 8, 1996 PART 2: SUPPLEMENTARY INSTRUCTIONS FOR SEVEN TriMetric DATA MONITORING FUNCTIONS. A: Introduction B: Summary Description of the seven data monitoring

More information

Coleman Air C440-HVM 440 Amp Diversion Controller Version 3.2

Coleman Air C440-HVM 440 Amp Diversion Controller Version 3.2 Coleman Air C440-HVM 440 Amp Diversion Controller Version 3.2 With Extended Diversion Mode Page 1 Page 2 Introduction This diversion controller is the result of our many attempts to use the controllers

More information

TECHNICAL REPORTS from the ELECTRONICS GROUP at the UNIVERSITY of OTAGO. Table of Multiple Feedback Shift Registers

TECHNICAL REPORTS from the ELECTRONICS GROUP at the UNIVERSITY of OTAGO. Table of Multiple Feedback Shift Registers ISSN 1172-496X ISSN 1172-4234 (Print) (Online) TECHNICAL REPORTS from the ELECTRONICS GROUP at the UNIVERSITY of OTAGO Table of Multiple Feedback Shift Registers by R. W. Ward, T.C.A. Molteno ELECTRONICS

More information

A Chemical Batch Reactor Schedule Optimizer

A Chemical Batch Reactor Schedule Optimizer A Chemical Batch Reactor Schedule Optimizer By Steve Morrison, Ph.D. 1997 Info@MethodicalMiracles.com 214-769-9081 Many chemical plants have a very similar configuration to pulp batch digesters; two examples

More information

CSCI 510: Computer Architecture Written Assignment 2 Solutions

CSCI 510: Computer Architecture Written Assignment 2 Solutions CSCI 510: Computer Architecture Written Assignment 2 Solutions The following code does compution over two vectors. Consider different execution scenarios and provide the average number of cycles per iterion

More information

Computer Architecture ELE 475 / COS 475 Slide Deck 6: Superscalar 3. David Wentzlaff Department of Electrical Engineering Princeton University

Computer Architecture ELE 475 / COS 475 Slide Deck 6: Superscalar 3. David Wentzlaff Department of Electrical Engineering Princeton University Computer Architecture ELE 475 / COS 475 Slide Deck 6: Superscalar 3 David Wentzlaff Department of Electrical Engineering Princeton University 1 Agenda SpeculaJon and Branches Register Renaming Memory DisambiguaJon

More information

Bimotion Advanced Port & Pipe Case study A step by step guide about how to calculate a 2-stroke engine.

Bimotion Advanced Port & Pipe Case study A step by step guide about how to calculate a 2-stroke engine. Bimotion Advanced Port & Pipe Case study A step by step guide about how to calculate a 2-stroke engine. 2009/aug/21. Bimotion. This paper is free for distribution and may be revised, for further references

More information

11.1 CURRENT ELECTRICITY. Electrochemical Cells (the energy source) pg Wet Cell. Dry Cell. Positive. Terminal. Negative.

11.1 CURRENT ELECTRICITY. Electrochemical Cells (the energy source) pg Wet Cell. Dry Cell. Positive. Terminal. Negative. Date: SNC1D: Electricity 11.1 CURRENT ELECTRICITY Define: CIRCUIT: path that electrons follow. CURRENT ELECTRICITY: continuous flow of electrons in a circuit LOAD: device that converts electrical energy

More information

ECE 740. Optimal Power Flow

ECE 740. Optimal Power Flow ECE 740 Optimal Power Flow 1 ED vs OPF Economic Dispatch (ED) ignores the effect the dispatch has on the loading on transmission lines and on bus voltages. OPF couples the ED calculation with power flow

More information

PRSalpha Air Drill (Double Valve)

PRSalpha Air Drill (Double Valve) 888-680-4466 ShopBotTools.com PRSalpha Air Drill (Double Valve) Copyright 2016 ShopBot Tools, Inc. page 1 Copyright 2016 ShopBot Tools, Inc. page 2 Table of Contents Overview...5 Spindle Mounting Plate...6

More information

Electronics Technology and Robotics I Week 2 Basic Electrical Meters and Ohm s Law

Electronics Technology and Robotics I Week 2 Basic Electrical Meters and Ohm s Law Electronics Technology and Robotics I Week 2 Basic Electrical Meters and Ohm s Law Administration: o Prayer o Bible Verse o Turn in quiz Meters: o Terms and Definitions: Analog vs. Digital Displays: Analog

More information

Roehrig Engineering, Inc.

Roehrig Engineering, Inc. Roehrig Engineering, Inc. Home Contact Us Roehrig News New Products Products Software Downloads Technical Info Forums What Is a Shock Dynamometer? by Paul Haney, Sept. 9, 2004 Racers are beginning to realize

More information

Improving Performance: Pipelining!

Improving Performance: Pipelining! Iproving Perforance: Pipelining! Meory General registers Meory ID EXE MEM WB Instruction Fetch (includes PC increent) ID Instruction Decode + fetching values fro general purpose registers EXE EXEcute arithetic/logic

More information

Part 1. The three levels to understanding how to achieve maximize traction.

Part 1. The three levels to understanding how to achieve maximize traction. Notes for the 2017 Prepare to Win Seminar Part 1. The three levels to understanding how to achieve maximize traction. Level 1 Understanding Weight Transfer and Tire Efficiency Principle #1 Total weight

More information

Economic Impact of Derated Climb on Large Commercial Engines

Economic Impact of Derated Climb on Large Commercial Engines Economic Impact of Derated Climb on Large Commercial Engines Article 8 Rick Donaldson, Dan Fischer, John Gough, Mike Rysz GE This article is presented as part of the 2007 Boeing Performance and Flight

More information

V 2.0. Version 9 PC. Setup Guide. Revised:

V 2.0. Version 9 PC. Setup Guide. Revised: V 2.0 Version 9 PC Setup Guide Revised: 06-12-00 Digital 328 v2 and Cakewalk Version 9 PC Contents 1 Introduction 2 2 Configuring Cakewalk 4 3 328 Instrument Definition 6 4 328 Automation Setup 8 5 Automation

More information

Discovery of Design Methodologies. Integration. Multi-disciplinary Design Problems

Discovery of Design Methodologies. Integration. Multi-disciplinary Design Problems Discovery of Design Methodologies for the Integration of Multi-disciplinary Design Problems Cirrus Shakeri Worcester Polytechnic Institute November 4, 1998 Worcester Polytechnic Institute Contents The

More information

To read more. CS 6354: Tomasulo. Intel Skylake. Scheduling. How can we reorder instructions? Without changing the answer.

To read more. CS 6354: Tomasulo. Intel Skylake. Scheduling. How can we reorder instructions? Without changing the answer. To read more CS 6354: Tomasulo 21 September 2016 This day s paper: Tomasulo, An Efficient Algorithm for Exploiting Multiple Arithmetic Units Supplementary readings: Hennessy and Patterson, Computer Architecture:

More information

CS 6354: Tomasulo. 21 September 2016

CS 6354: Tomasulo. 21 September 2016 1 CS 6354: Tomasulo 21 September 2016 To read more 1 This day s paper: Tomasulo, An Efficient Algorithm for Exploiting Multiple Arithmetic Units Supplementary readings: Hennessy and Patterson, Computer

More information

Steady-State Power System Security Analysis with PowerWorld Simulator

Steady-State Power System Security Analysis with PowerWorld Simulator Steady-State Power System Security Analysis with PowerWorld Simulator S3: Techniques for Conditioning Hard-to-Solve Cases 2001 South First Street Champaign, Illinois 61820 +1 (217) 384.6330 support@powerworld.com

More information

CHAPTER 19 DC Circuits Units

CHAPTER 19 DC Circuits Units CHAPTER 19 DC Circuits Units EMF and Terminal Voltage Resistors in Series and in Parallel Kirchhoff s Rules EMFs in Series and in Parallel; Charging a Battery Circuits Containing Capacitors in Series and

More information

Cruise Control 1993 Jeep Cherokee

Cruise Control 1993 Jeep Cherokee Cruise Control 1993 Jeep Cherokee Design Examples 1 Owner s Manual System Description: Cruise Control System Interface When engaged, the electronic cruise control device takes over the accelerator operations

More information

6 Things to Consider when Selecting a Weigh Station Bypass System

6 Things to Consider when Selecting a Weigh Station Bypass System 6 Things to Consider when Selecting a Weigh Station Bypass System Moving truck freight from one point to another often comes with delays; including weather, road conditions, accidents, and potential enforcement

More information

Battery Buggy. Division B

Battery Buggy. Division B Battery Buggy Division B http://api-static.ctlglobalsolutions.com/science/so_b_2018final.pdf Objective: To build a battery powered vehicle travels a specific distance as quickly as possible and stop as

More information

TECHNICAL REFERENCE CLEANING POWER GUIDELINES TANKJET TANK CLEANER OVERVIEW BY TANK DIAMETER OPTIMIZING TANK CLEANING OPERATIONS

TECHNICAL REFERENCE CLEANING POWER GUIDELINES TANKJET TANK CLEANER OVERVIEW BY TANK DIAMETER OPTIMIZING TANK CLEANING OPERATIONS OPTIMIZING TANK CLEANING OPERATIONS CLEANING POWER GUIDELINES Choosing a tank cleaner is based primarily on tank size and level of cleaning required. Understanding the definitions that follow will help

More information

How to generate the Sbox of Luffa

How to generate the Sbox of Luffa How to generate the Sbox of Luffa ESC2010@Remich (Jan.11.2010) Dai Watanabe SDL, Hitachi Luffa is a registered trademark of Hitachi, Ltd. 1 Outline Topic How to find an 4-bit sbox optimized for bit slice

More information

Steady-State Power System Security Analysis with PowerWorld Simulator

Steady-State Power System Security Analysis with PowerWorld Simulator Steady-State Power System Security Analysis with PowerWorld Simulator using PowerWorld Simulator 2001 South First Street Champaign, Illinois 61820 +1 (217) 384.6330 support@powerworld.com http://www.powerworld.com

More information

Simple Gears and Transmission

Simple Gears and Transmission Simple Gears and Transmission Simple Gears and Transmission page: of 4 How can transmissions be designed so that they provide the force, speed and direction required and how efficient will the design be?

More information

PQube 3 Modbus Interface

PQube 3 Modbus Interface PQube 3 Modbus Interface Reference manual Revision 1.9 Modbus Interface Reference Manual 1.9- Page 1 Table of Contents 1. Background... 3 2. Basics... 3 2.1 Registers and Coils... 3 2.2 Address Space...

More information

HIGH VOLTAGE vs. LOW VOLTAGE: POTENTIAL IN MILITARY SYSTEMS

HIGH VOLTAGE vs. LOW VOLTAGE: POTENTIAL IN MILITARY SYSTEMS 2013 NDIA GROUND VEHICLE SYSTEMS ENGINEERING AND TECHNOLOGY SYMPOSIUM POWER AND MOBILITY (P&M) MINI-SYMPOSIUM AUGUST 21-22, 2013 TROY, MICHIGAN HIGH VOLTAGE vs. LOW VOLTAGE: POTENTIAL IN MILITARY SYSTEMS

More information

Your web browser (Safari 7) is out of date. For more security, comfort and. the best experience on this site: Update your browser Ignore

Your web browser (Safari 7) is out of date. For more security, comfort and. the best experience on this site: Update your browser Ignore Your web browser (Safari 7) is out of date. For more security, comfort and Activitydevelop the best experience on this site: Update your browser Ignore Circuits with Friends What is a circuit, and what

More information

CS 152 Computer Architecture and Engineering

CS 152 Computer Architecture and Engineering CS 152 Computer Architecture and Engineering Lecture 23 Synchronization 2006-11-16 John Lazzaro (www.cs.berkeley.edu/~lazzaro) TAs: Udam Saini and Jue Sun www-inst.eecs.berkeley.edu/~cs152/ 1 Last Time:

More information

Installation and Construction Notes for EVSE4

Installation and Construction Notes for EVSE4 Installation and Construction Notes for EVSE4 You need to read and understand this if you want to build an EVSE that will be safe and need to pass a building inspectors review. Before beginning this process

More information

The purpose of this lab is to explore the timing and termination of a phase for the cross street approach of an isolated intersection.

The purpose of this lab is to explore the timing and termination of a phase for the cross street approach of an isolated intersection. 1 The purpose of this lab is to explore the timing and termination of a phase for the cross street approach of an isolated intersection. Two learning objectives for this lab. We will proceed over the remainder

More information

Chapter 3: Computer Organization Fundamentals. Oregon State University School of Electrical Engineering and Computer Science.

Chapter 3: Computer Organization Fundamentals. Oregon State University School of Electrical Engineering and Computer Science. Chapter 3: Computer Organization Fundamentals Prof. Ben Lee Oregon State University School of Electrical Engineering and Computer Science Chapter Goals Understand the organization of a computer system

More information

Contents: Page # Judge s Responsibilities. 5. Workmanship vs. Authenticity What is it? 7

Contents: Page # Judge s Responsibilities. 5. Workmanship vs. Authenticity What is it? 7 C.T.C.I. CONCOURS & TOURING JUDGES TRAINING HANDOUTS FILE Contents: Page # Owner s Briefing 2 Team Captain s Responsibilities 4 Judge s Responsibilities. 5 Award Standards 6 Workmanship vs. Authenticity

More information

Chapter Assessment Use with Chapter 22.

Chapter Assessment Use with Chapter 22. Date Period 22 Use with Chapter 22. Current Electricity Understanding Concepts Part A Use each of the following terms once to complete the statements below. ampere electric current potential difference

More information

Inventory systems for dependent demand

Inventory systems for dependent demand Roberto Cigolini roberto.cigolini@polimi.it Department of Management, Economics and Industrial Engineering Politecnico di Milano 1 Overall view (taxonomy) Planning systems Push systems (needs based) (requirements

More information

Power Consumption Reduction: Hot Spare

Power Consumption Reduction: Hot Spare Power Consumption Reduction: Hot Spare A Dell technical white paper Mark Muccini Wayne Cook Contents Executive summary... 3 Introduction... 3 Traditional power solutions... 3 Hot spare... 5 Hot spare solution...

More information

Safe Braking on the School Bus Advanced BrakingTechniques and Practices. Reference Guide and Test by Video Communications

Safe Braking on the School Bus Advanced BrakingTechniques and Practices. Reference Guide and Test by Video Communications Safe Braking on the School Bus Advanced BrakingTechniques and Practices Reference Guide and Test by Video Communications Introduction Brakes are considered one of the most important items for school bus

More information

SMARTSTRINGSTM. Owner's Manual

SMARTSTRINGSTM. Owner's Manual SMARTSTRINGSTM Owner's Manual Welcome! Thank you for purchasing our SmartStrings alignment kit. You are now the owner of what we believe to be the best and most universal way to quickly perform accurate

More information

Chapter 2 & 3: Interdependence and the Gains from Trade

Chapter 2 & 3: Interdependence and the Gains from Trade Econ 123 Principles of Economics: Micro Chapter 2 & 3: Interdependence and the Gains from rade Instructor: Hiroki Watanabe Fall 212 Watanabe Econ 123 2 & 3: Gains from rade 1 / 119 1 Introduction 2 Productivity

More information

Welcome to ABB machinery drives training. This training module will introduce you to the ACS850-04, the ABB machinery drive module.

Welcome to ABB machinery drives training. This training module will introduce you to the ACS850-04, the ABB machinery drive module. Welcome to ABB machinery drives training. This training module will introduce you to the ACS850-04, the ABB machinery drive module. 1 Upon the completion of this module, you will be able to describe the

More information

EE 330 Integrated Circuit. Sequential Airbag Controller

EE 330 Integrated Circuit. Sequential Airbag Controller EE 330 Integrated Circuit Sequential Airbag Controller Chongli Cai Ailing Mei 04/2012 Content...page Introduction...3 Design strategy...3 Input, Output and Registers in the System...4 Initialization Block...5

More information

1 Configuration Space Path Planning

1 Configuration Space Path Planning CS 4733, Class Notes 1 Configuration Space Path Planning Reference: 1) A Simple Motion Planning Algorithm for General Purpose Manipulators by T. Lozano-Perez, 2) Siegwart, section 6.2.1 Fast, simple to

More information

Reliable Reach. Robotics Unit Lesson 4. Overview

Reliable Reach. Robotics Unit Lesson 4. Overview Robotics Unit Lesson 4 Reliable Reach Overview Robots are used not only to transport things across the ground, but also as automatic lifting devices. In the mountain rescue scenario, the mountaineers are

More information

Southern California Edison Rule 21 Storage Charging Interconnection Load Process Guide. Version 1.1

Southern California Edison Rule 21 Storage Charging Interconnection Load Process Guide. Version 1.1 Southern California Edison Rule 21 Storage Charging Interconnection Load Process Guide Version 1.1 October 21, 2016 1 Table of Contents: A. Application Processing Pages 3-4 B. Operational Modes Associated

More information

Product Manual. 42BYGH40(M)-160-4A NEMA 17 Bipolar 5.18:1. Planetary Gearbox Stepper

Product Manual. 42BYGH40(M)-160-4A NEMA 17 Bipolar 5.18:1. Planetary Gearbox Stepper Product Manual 42BYGH40(M)-160-4A NEMA 17 Bipolar 5.18:1 Planetary Gearbox Stepper Phidgets - Product Manual 42BYGH40(M)-160-4A NEMA 17 Bipolar 5.18:1 Planetary Gearbox Stepper Phidgets Inc. 2011 Contents

More information

Pre-lab Questions: Please review chapters 19 and 20 of your textbook

Pre-lab Questions: Please review chapters 19 and 20 of your textbook Introduction Magnetism and electricity are closely related. Moving charges make magnetic fields. Wires carrying electrical current in a part of space where there is a magnetic field experience a force.

More information

6.823 Computer System Architecture Prerequisite Self-Assessment Test Assigned Feb. 6, 2019 Due Feb 11, 2019

6.823 Computer System Architecture Prerequisite Self-Assessment Test Assigned Feb. 6, 2019 Due Feb 11, 2019 6.823 Computer System Architecture Prerequisite Self-Assessment Test Assigned Feb. 6, 2019 Due Feb 11, 2019 http://csg.csail.mit.edu/6.823/ This self-assessment test is intended to help you determine your

More information

Cannondale Diagnostic Tool Manual

Cannondale Diagnostic Tool Manual Cannondale Diagnostic Tool Manual For vehicles (ATV & Motorcycles) equipped with the MC1000 Engine Management System Software CD P/N 971-5001983 Data Cable P/N 971-5001984 POTENTIAL HAZARD Running the

More information

Power Solutions Manager Generac Power Systems, Inc.

Power Solutions Manager Generac Power Systems, Inc. Engine Generator Paralleling Concepts Gen. #1 Gen. #2 Gen. #3 Gen. #4 Gen. #5 Presenter: Daniel Barbersek Power Solutions Manager Generac Power Systems, Inc. RUNNING HEADLINE What Topics Will Be Covered

More information

APPLICATION NOTES VALVE CHECKER M

APPLICATION NOTES VALVE CHECKER M APPLICATION NOTES VALVE CHECKER M040-120-001 1 of 16 CONTENTS Chapter Title Page 1. Description 3 2. Specification 7 3. Connecting to valve and plant 8 4. Plant mode operation (in line) 9 5. Checker mode

More information

Planning Advisory Notice

Planning Advisory Notice Capstan hoists, often referred to as catheads, make back-breaking work faster, easier and more productive. They are used for many applications in multiple industries including telecommunications, electric

More information

ABB June 19, Slide 1

ABB June 19, Slide 1 Dr Simon Round, Head of Technology Management, MATLAB Conference 2015, Bern Switzerland, 9 June 2015 A Decade of Efficiency Gains Leveraging modern development methods and the rising computational performance-price

More information

BMW E61 Hydraulic Pump replacement instructions

BMW E61 Hydraulic Pump replacement instructions BMW E61 Hydraulic Pump replacement instructions This DIY will guide you through the tasks needed to successfully replace your defective tailgate hydraulic pump Difficulty 3 of 10. The most difficult part

More information

BIG BAR SOFT SPRING SET UP SECRETS

BIG BAR SOFT SPRING SET UP SECRETS BIG BAR SOFT SPRING SET UP SECRETS Should you be jumping into the latest soft set up craze for late model asphalt cars? Maybe you will find more speed or maybe you won t, but either way understanding the

More information

Introduction to PowerWorld Simulator: Interface and Common Tools

Introduction to PowerWorld Simulator: Interface and Common Tools Introduction to PowerWorld Simulator: Interface and Common Tools I10: Introduction to Contingency Analysis 2001 South First Street Champaign, Illinois 61820 +1 (217) 384.6330 support@powerworld.com http://www.powerworld.com

More information

PRESEASON CHASSIS SETUP TIPS

PRESEASON CHASSIS SETUP TIPS PRESEASON CHASSIS SETUP TIPS A Setup To-Do List to Get You Started By Bob Bolles, Circle Track Magazine When we recently set up our Project Modified for our first race, we followed a simple list of to-do

More information

PIPELINING: BRANCH AND MULTICYCLE INSTRUCTIONS

PIPELINING: BRANCH AND MULTICYCLE INSTRUCTIONS PIPELINING: BRANCH AND MULTICYCLE INSTRUCTIONS Mahdi Nazm Bojnordi Assistant Professor School of Computing University of Utah CS/ECE 6810: Computer Architecture Overview Announcement Homework 1 submission

More information

FRONTAL OFF SET COLLISION

FRONTAL OFF SET COLLISION FRONTAL OFF SET COLLISION MARC1 SOLUTIONS Rudy Limpert Short Paper PCB2 2014 www.pcbrakeinc.com 1 1.0. Introduction A crash-test-on- paper is an analysis using the forward method where impact conditions

More information