Chapter 2 ( ) -Revisit ReOrder Buffer -Exception handling and. (parallelism in HW)

Transcription

1 Comuter Architecture A Quantitative Aroach, Fifth Edition Chater 2 ( ) -Revisit ReOrder Buffer -Excetion handling and (seculation in hardware) -VLIW and EPIC (seculation in SW, arallelism in SW) -Multile Issue rocessors (arallelism in HW) Coyright 2012, Elsevier Inc. All rights reserved. 1

2 Comuter Architecture A Quantitative Aroach, Fifth Edition Review -What are the three tyes of hazards? -Which hazards does register renaming remove? -What are the advantages of hardware based scheduling (OoO)? Disadvantages? -What are the advantages of SW based scheduling? Disadvantages? Coyright 2012, Elsevier Inc. All rights reserved. 2

3 Multile Issue and Static Scheduling To achieve CPI < 1, need to comlete multile instructions er clock Solutions: Statically scheduled suerscalar rocessors VLIW (very long instruction ti word) rocessors (done in SW) dynamically scheduled suerscalar rocessors (done in HW) Multile Issue an nd Static Schedul ling Coyright 2012, Elsevier Inc. All rights reserved. 3

4 Seculation Control Seculation Move instructions ti across a branch boundary Data seculation Execute load/stores OoO. Multile Issue an nd Static Coyright 2012, Elsevier Inc. All rights reserved. 4Scheduling

5 Seculation How to design an OoO rocessor that: Uses register renaming to remove WAW and WAR deendencies Can handle instruction excetions Can execute across branch boundaries Can reorder load/store instructions Multile Issue an nd Static Coyright 2012, Elsevier Inc. All rights reserved. 5Scheduling

6 L11-6 Dataflow execution Ins# use exec o 1 src1 2 src2 tr 2 next to deallocate t 1 t 2... rt 1 next available Reorder buffer t n Instruction slot is candidate for execution when: October 19, 2011 It holds a valid instruction ( use bit is set) It has not already started execution ( exec bit is clear) Both oerands are available (1 and 2 are set) htt://

7 Renaming & Out-of-order Issue An examle Renaming table data F1 F2 v1 t1 F3 F4 t2 t5 F5 F6 t3 F7 F8 v4 t4 Reorder buffer Ins# use exec o 1 src1 2 src LD LD MUL 10 v2 t2 1 v SUB 1 v1 1 v DIV 1 v1 01 t4 v4 t 1 t 2 t 3 t 4 t 5.. L11-7 data / t i 1 LD F2, 34(R2) 2 LD F4, 45(R3) When are names in sources 3 MULTD F6, F4, F2 relaced by data? 4 SUBD F8, F2, F2 Whenever an FU roduces data 5 DIVD F4, F2, F8 When can a name be reused? 6 ADDD F10, F6, F4 Whenever an instruction comletes October 19, 2011 htt://

8 L11-8 Data-Driven Driven Execution Renaming table & reg file Reorder buffer Ins# use exec o 1 src1 2 src2 t 1 t2.. t n Relacing the tag by its value is an exensive oeration Load Unit FU FU Store Unit < t, result > Instruction temlate (i.e., tag t) is allocated by the Decode stage, which also stores the tag in the reg file When an instruction comletes, its tag is deallocated October 19, 2011 htt://

9 L11-9 Simlifying Allocation/Deallocation Ins# use exec o 1 src1 2 src2 tr 2 next to deallocate t 1 t 2... rt 1 next available Reorder buffer t n Instruction buffer is managed circularly October 19, 2011 exec bit is set when instruction begins execution When an instruction comletes its use bit is marked free tr 2 is incremented only if the use bit is marked free htt://

10 L11-10 Effectiveness? Renaming and Out-of-order execution was first imlemented in 1969 in IBM 360/91 but did not show u in the subsequent models until mid- Nineties. Why? 1. Effective on a very small class of rograms 2. Did not address the memory latency roblem which turned out be a much bigger issue than FU latency 3. Made excetions imrecise One more roblem needed to be solved Control transfers October 19, 2011 htt:// More on this in the next lecture

11 L11-11 Precise Excetions Excetions are relatively l unlikely l events that t need secial rocessing, but where adding exlicit control flow instructions is not desired, e.g., divide by 0, age fault Excetions can be viewed as an imlicit conditional subroutine call that is inserted between two instructions. Therefore, it must aear as if the excetion is taken between two instructions (say I i and I i+1 ) the effect of all instructions u to and including I i is comlete no effect of any instruction after I i has taken lace The handler either aborts the rogram or restarts it at I i+1. October 19, 2011 htt://

12 Effect on Excetions Out-of-order Comletion L11-12 I 1 DIVD f6, f6, f4 I 2 LD f2, 45(r3) I 3 MULTD f0, f2, f4 I 4 DIVD f8, f6, f2 I 5 SUBD f10, f0, f6 I 6 ADDD f6, f8, f2 out-of-order of order com Consider excetions restore f2 restore f10 October 19, 2011 Precise excetions are difficult to imlement at high seed - want to start execution of later instructions before excetion checks finished on earlier instructions htt://

13 L11-13 Excetions Excetions create a deendence on the value of the next PC Otions for handling this deendence: Stall No Byass: No Find something else to do No Change the architecture Sometimes: Alha, Multiflow Seculate! Most common aroach! How can we handle rollback on mis-seculation Delay state udate until commit on seculated instructions Note: earlier excetions must override later ones October 19, 2011 htt://

14 L11-14 Phases of Instruction Execution October 19, 2011 PC I-cache Fetch Buffer Issue Buffer Func. Units Result Buffer Arch. State Fetch: Instruction bits retrieved from cache. Decode: Instructions laced in aroriate issue (aka disatch ) stage buffer Execute: Instructions and oerands sent to execution units. When execution comletes, all results and excetion flags are available. Commit: Instruction irrevocably udates architectural state (aka graduation or comletion ). htt://

15 Excetion Handling (In-Order Five-Stage Pieline) Commit Point L11-15 PC Inst. Mem D Data Decode E + M Mem W PC Address Illegal l Overflow Data Addr Kill Excetions Ocode Excet Writeback Exc Exc Exc Cause D E M Select Handler PC Kill F Stage PC D Kill D Stage Hold excetion flags in ieline until commit oint (M stage) If excetion at commit: udate Cause/EPC registers kill all stages fetch at handler PC Inject external interruts at commit oint October 19, 2011 PC E Kill E Stage htt:// PC M Asynchronous Interruts EPC

16 In-Order Commit for Precise Excetions L11-16 In-order Out-of-order In-order Fetch Decode Reorder Buffer Commit Kill Kill Inject handler PC Execute Kill Excetion? Instructions fetched and decoded into instruction reorder buffer in-order Execution is out-of-order ( out-of-order comletion) Commit (write-back to architectural state, i.e., regfile & memory, is in-order Temorary storage needed to hold results before e commit (shadow registers and store buffers) October 19, 2011 htt://

17 L11-17 Extensions for Precise Excetions Inst# use exec o 1 src1 2 src2 d dest data cause tr 2 next to commit tr 1 next available Reorder buffer add <d, dest, data, cause> fields in the instruction temlate commit instructions to reg file and memory in rogram order buffers can be maintained circularly on excetion, clear reorder buffer by resetting tr 1 =tr 2 (stores must wait for commit before udating memory) October 19, 2011 htt://

18 L11-18 Renaming Table Rename Table r 1 t v tag valid bit r 2 Register File Reorder buffer Ins# use exec o 1 src1 2 src2 d dest data t 1 t 2.. t n Load Unit FU FU FU Store Unit Commit < t, result > Renaming table is a cache to seed u register name look u. It needs to be cleared after each excetion taken. When else are valid bits cleared? Control transfers October 19, 2011 htt://

19 L11-19 Physical Register files Reorder buffers are sace inefficient a data value may be stored in multile laces in the reorder buffer idea kee all data values in a hysical register file Tag reresents the name of the data value and name of the hysical register that holds it Reorder buffer contains only tags Thus, 64 data values may be relaced by 8-bit tags for a 256 element hysical register file More on this in later lectures October 19, 2011 htt://

20 L13-20 Recovering ROB/Renaming Table Rename Table r 1 r 2 t t vv t v Rename t v Snashots Registe r File Ptr 2 next to commit rollback next available Ptr 1 next available Ins# use exec o 1 src1 2 src2 d dest data t 1 t 2.. t n Reorder buffer Load Unit FU FU FU Store Unit Commit < t, result > Take snashot of register rename table at each redicted branch, recover earlier snashot if branch misredicted October 26, 2011 htt://

21 L13-21 Ma Table Recovery - Snashots Seculative value management of microarchitectural state Reg Ma V Sna Ma V Sna Ma V R0 T20 X T20 X T20 X R1 T73 T08 X T73 X T08 R2 T45 X T45 X T45 X R3 T128 X T128 T128 X R30 T54 T54 T54 R31 T88 X T88 X T88 X What kind of value management is this? Greedy!! October 26, 2011 htt://

22 L13-22 O-o-O O Execution with ROB Rename Table Next to commit Next available Reorder buffer R1 R2 R3 R4 t i 0 t j 0 t 2 1 t 1 1 : : tag Register valid bit File R1 1 R2 2 R3 3 : Ins# use exec o 1 src1 2 src2 d dest data 0 X X add X 1 X 2 X R4 4 8 X ld X 256 R3 t 1 t 2.. t n Load Unit FU FU FU Store Commit Unit < t, result > Basic Oeration: Enter o and tag or data (if known) for each source Relace tag with data as it becomes available Issue instruction when all sources are available Save dest data when oeration finishes Commit saved dest data when instruction commits October 26, 2011 htt://

23 L13-23 Lifetime of Physical Registers Physical regfile holds committed and seculative values Physical registers decouled d from ROB entries (no data in ROB) a) ld r1, (r3) ld P1, (Px) b) add r3, r1, #4 add P2, P1, #4 c) sub r1, r3, r9 sub P3, P2, Py d) add r3, r1, r7 Rename add P4, P3, Pz e) ld r6,,(r1) ld P5,,(P3) f) add r8, r6, r3 add P6, P5, P4 g) st r8, (r1) st P6, (P3) h) ld r3, (r11) ld P7, (Pw) When can we reuse a hysical register? When next write of same architectural register commits October 26, 2011 htt://

24 L13-24 Physical Register Management R0 R1 R2 R3 R4 R5 R6 R7 Rename Table P8 P7 P5 P6 ROB P0 P1 P2 P3 P4 P5 P6 P7 P8 Pn Physical Regs <R6> <R7> <R3> <R1> Free List P0 P1 P3 P2 P4 use ex o 1 PR1 2 PR2 Rd LPRd PRd ld r1, 0(r3) add r3, r1, #4 sub r6, r7, r6 add r3, r3, r6 ld r6, 0(r1) (LPRd requires third read ort on Rename Table for each instruction) i October 26, 2011 htt://

25 L13-25 Physical Register Management R0 R1 R2 R3 R4 R5 R6 R7 Rename Table P8 P7 P5 P6 ROB P0 P0 P1 P2 P3 P4 P5 P6 P7 P8 Pn Physical Regs <R6> <R7> <R3> <R1> Free List P0 P1 P3 P2 P4 use ex o 1 PR1 2 PR2 Rd LPRd PRd x ld P7 r1 P8 P0 ld r1, 0(r3) add r3, r1, #4 sub r6, r7, r6 add r3, r3, r6 ld r6, 0(r1) October 26, 2011 htt://

26 L13-26 Physical Register Management R0 R1 R2 R3 R4 R5 R6 R7 Rename Table P8 P7 P5 P6 ROB P0 P1 P0 P1 P2 P3 P4 P5 P6 P7 P8 Pn Physical Regs <R6> <R7> <R3> <R1> Free List P0 P1 P3 P2 P4 use ex o 1 PR1 2 PR2 Rd LPRd PRd x ld P7 r1 P8 P0 x add P0 r3 P7 P1 ld r1, 0(r3) add r3, r1, #4 sub r6, r7, r6 add r3, r3, r6 ld r6, 0(r1) October 26, 2011 htt://

27 L13-27 Physical Register Management R0 R1 R2 R3 R4 R5 R6 R7 Rename Table P8 P7 P5 P6 ROB P0 P1 P3 P0 P1 P2 P3 P4 P5 P6 P7 P8 Pn Physical Regs <R6> <R7> <R3> <R1> Free List P0 P1 P3 P2 P4 use ex o 1 PR1 2 PR2 Rd LPRd PRd x ld P7 r1 P8 P0 x add P0 r3 P7 P1 x sub P6 P5 r6 P5 P3 ld r1, 0(r3) add r3, r1, #4 sub r6, r7, r6 add r3, r3, r6 ld r6, 0(r1) October 26, 2011 htt://

28 L13-28 Physical Register Management R0 R1 R2 R3 R4 R5 R6 R7 Rename Table P8 P7 P5 P6 ROB P0 P1 P3 P2 P0 P1 P2 P3 P4 P5 P6 P7 P8 Pn Physical Regs <R6> <R7> <R3> <R1> Free List P0 P1 P3 P2 P4 use ex o 1 PR1 2 PR2 Rd LPRd PRd x ld P7 r1 P8 P0 x add P0 r3 P7 P1 x sub P6 P5 r6 P5 P3 x add P1 P3 r3 P1 P2 ld r1, 0(r3) add r3, r1, #4 sub r6, r7, r6 add r3, r3, r6 ld r6, 0(r1) October 26, 2011 htt://

29 L13-29 Physical Register Management R0 R1 R2 R3 R4 R5 R6 R7 Rename Table P8 P7 P5 P6 ROB P0 P1 P3 P2 P4 P0 P1 P2 P3 P4 P5 P6 P7 P8 Pn Physical Regs <R6> <R7> <R3> <R1> Free List P0 P1 P3 P2 P4 use ex o 1 PR1 2 PR2 Rd LPRd PRd x ld P7 r1 P8 P0 x add P0 r3 P7 P1 x sub P6 P5 r6 P5 P3 x add P1 P3 r3 P1 P2 x ld P0 r6 P3 P4 ld r1, 0(r3) add r3, r1, #4 sub r6, r7, r6 add r3, r3, r6 ld r6, 0(r1) October 26, 2011 htt://

30 L13-30 Physical Register Management R0 R1 R2 R3 R4 R5 R6 R7 Rename Table P8 P7 P5 P6 ROB P0 P1 P3 P2 P4 P0 P1 P2 P3 P4 P5 P6 P7 P8 Pn Physical Regs <R1> <R6> <R7> <R3> <R1> Free List P0 P1 P3 P2 P4 P8 use ex o 1 PR1 2 PR2 Rd LPRd PRd x x ld P7 r1 P8 P0 x add P0 r3 P7 P1 x sub P6 P5 r6 P5 P3 x add P1 P3 r3 P1 P2 x ld P0 r6 P3 P4 ld r1, 0(r3) add r3, r1, #4 sub r6, r7, r6 add r3, r3, r6 ld r6, 0(r1) Execute & Commit October 26, 2011 htt://

31 L13-31 Physical Register Management R0 R1 R2 R3 R4 R5 R6 R7 Rename Table P8 P7 P5 P6 ROB P0 P1 P3 P2 P4 P0 P1 P2 P3 P4 P5 P6 P7 P8 Pn Physical Regs <R1> <R3> <R6> <R7> <R3> Free List P0 P1 P3 P2 P4 P8 P7 use ex o 1 PR1 2 PR2 Rd LPRd PRd x x ld P7 r1 P8 P0 x x add P0 r3 P7 P1 x sub P6 P5 r6 P5 P3 x add P1 P3 r3 P1 P2 x ld P0 r6 P3 P4 ld r1, 0(r3) add r3, r1, #4 sub r6, r7, r6 add r3, r3, r6 ld r6, 0(r1) Execute & Commit October 26, 2011 htt://

32 Unified Physical Register File (MIPS R10K, Alha 21264, Pentium 4) L13-32 r 1 r 2 t i t j Snashots for misredict recovery t 1 t 2. t n Reg File Rename Load Table FU FU FU (ROB not shown) Unit Store Unit < t, result > One regfile for both committed and seculative values (no data in ROB) During decode, instruction result allocated new hysical register, source regs translated to hysical regs through rename table Instruction reads data from regfile at start of execute (not in decode) Write-back udates reg. busy bits on instructions in ROB (assoc. search) Snashots of rename table taken at every branch to recover misredicts On excetion, renaming undone in reverse order of issue (MIPS R10000) October 26, 2011 htt://

33 L13-33 Seculative & Out-of-Order Execution Branch Prediction kill kill Branch Resolution kill kill Out-of-Order Udate redictors In-Order PC Fetch Decode & Rename Reorder Buffer Commit In-Order Physical Reg. File Branch Unit Execute ALU MEM Store Buffer D$ October 26, 2011 htt://

34 Reorder Buffer Holds Active Instruction Window L13-34 (Older instructions) i Commit ld r1, (r3) ld r1, (r3) add r3, r1, r2 add r3, r1, r2 sub r6, r7, r9 Execute sub r6, r7, r9 add r3, r3, r6 add r3, r3, r6 ld r6, (r1) ld r6, (r1) add r6, r6, r3 st r6, (r1) add r6, r6, r3 Fetch ld r6, (r1) st r6, (r1) ld r6,,(r1) (Newer instructions) Cycle t + 1 Cycle t October 26, 2011 htt://

35 L11-35 Branch Penalty Next fetch started PC I-cache Fetch How many instructions Fetch need to be killed on a Buffer misrediction? Issue Modern rocessors may Buffer have > 10 ieline stages between next c calculation and branch resolution! Func. Units Decode Execute Branch executed Result Buffer Commit October 19, 2011 htt:// Arch. State

36 Getting CPI below 1 CPI 1 if issue only 1 instruction ti every clock cycle Multile-issue rocessors come in 3 flavors: 1. Statically-scheduled l d suerscalar rocessors In-order execution Varying number of instructions i issued (comiler) 2. Dynamically-scheduled suerscalar rocessors Out-of-order execution Varying number of instructions issued (CPU) 3. VLIW (very long instruction i word) rocessors In-order execution Fixed number of instructions ti issued

37 VLIW: Very Large Instruction Word (1/2) Each VLIW has exlicit coding for multile oerations Several instructions combined into ackets Possibly with arallelism indicated Tradeoff instruction sace for simle decoding Room for many oerations Indeendent oerations => execute in arallel E.g., 2 integer oerations, 2 FP os, 2 Memory refs, 1 branch

38 VLIW: Very Large Instruction Word (2/2) Assume 2 load/store, 2 f, 1 int/branch VLIW with 0-5 oerations. Why 0? Imortant to avoid emty instruction slots Loo unrolling Local scheduling Global scheduling Scheduling across branches Difficult to find all deendencies in advance Solution1: Block on memory accesses Solution2: CPU detects some deendencies

39 Recall: Unrolled Loo that minimizes stalls for Scalar Source code: for (i = 1000; i >0; i=i-1) x[i] = x[i] + s; Loo: LD L.D F0,0(R1) 0(R1) L.D F6,-8(R1) L.D F10,-16(R1) L.D F14,-24(R1) ADD.D F4,F0,F2 ADD.DD F8,F6,F2F6 F ADD.D F12,F10,F2 ADD.DD F16,F14,F2F14 F2 S.D F4,0(R1) S.D F8,-8(R1) DADDUI R1,R1,#-32 S.D F12,-16(R1) SD F6 (R ) BNE R1,R2,Loo Register maing: S.D F16,-24(R1) s F2 i R1

40 Loo Unrolling in VLIW Memory Memory FP FP Int. o/ Clock reference 1 reference 2 oeration 1 o. 2 branch L.D F0,0(R1) L.D F6,-8(R1) 1 L.D F10,-16(R1) L.D F14,-24(R1) 2 L.D F18,-32(R1) L.D F22,-40(R1) ADD.D F4,F0,F2 ADD.D F8,F6,F2 3 L.D F26,-48(R1) ADD.D F12,F10,F2 ADD.D F16,F14,F2 4 ADD.D F20,F18,F2 ADD.D F24,F22,F2 5 S.D 0(R1),F4 S.D -8(R1),F8 ADD.D F28,F26,F2 6 S.D -16(R1),F12 S.D -24(R1),F16 7 SD S.D -32(R1),F20 SD S.D -40(R1),F24 DSUBUI R1,R1,#48R 8 S.D -0(R1),F28 BNEZ R1,LOOP 9 Unrolled 7 iterations to avoid delays 7 results in 9 clocks, or 1.3 clocks er iteration (1.8X) Average: 2.5 os er clock, 50% efficiency Note: Need more registers s in VLIW (15 vs. 6 in SS)

41 Problems with 1st Generation VLIW Increase in code size Loo unrolling Partially emty VLIW Oerated in lock-ste; no hazard detection HW A stall in any functional unit ieline causes entire rocessor to stall, since all functional units must be ket synchronized Comiler might redict function units, but caches hard to redict Moder VLIWs are interlocked (identify deendences between bundles and stall). Binary code comatibility Strict VLIW => different numbers of functional units and unit latencies require different versions of the code

42 VLIW Tradeoffs Advantages Simler hardware because the HW does not have to identify indeendent instructions. Disadvantages Relies on smart comiler Code incomatibility between generations There are limits to what the comiler can do (can t move loads above branches, can t move loads above stores) Common uses Embedded market where hardware simlicity is imortant, alications exhibit lenty of ILP, and binary comatibility is a non-issue.

43 IA-64 and EPIC 64 bit instruction set architecture Not a CPU, but an architecture Itanium and Itanium 2 are CPUs based on IA-64 Made by Intel and Hewlett-Packard (itanium 2 and 3 designed in Colorado) Uses EPIC: Exlicitly Parallel Instruction Comuting Dearture from the x86 architecture Meant to achieve out-of-order of order erformance with inorder HW + comiler-smarts Sto bits to hel with code density Suort for control seculation (moving loads above branches) Suort for data seculation (moving loads above stores) Details in Aendix G.6

44 Control Seculation Can the comiler schedule an indeendent load above a branch? Bne R1, R2, TARGET Ld R3, R4(0) What are the roblems? EPIC rovides seculative loads Ld.s R3, R4(0) Bne R1, R2, TARGET Check R4(0)

45 Data Seculation Can the comiler schedule an indeendent load above a store? St R5, R6(0) Ld R3, R4(0) What are the roblems? EPIC rovides advanced loads and an ALAT (Advanced Load Address Table) Ld.a R3, R4(0) creates entry in ALAT St R5, R6(0) looks k u ALAT, if match, jum to fixu code

46 EPIC Conclusions Goal of EPIC was to maintain advantages of VLIW, but achieve erformance of out-of-order. Results: Comlicated bundling rules saves some sace, but makes the hardware more comlicated Add secial hardware and instructions for scheduling loads above stores and branches (new comlicated hardware) Add secial hardware to remove branch enalties (redication) End result is a machine as comlicated as an out-oforder, but now also requiring a suer-sohisticated comiler.

47 Multile Issue and Static Scheduling Multile Issue Coyright 2012, Elsevier Inc. All rights reserved. 47

48 Dynamic Scheduling, Multile Issue, and Seculation Modern microarchitectures: Dynamic scheduling + multile l issue + seculation Two aroaches: Assign reservation stations and udate ieline control table in half clock cycles Only suorts 2 instructions/clock Design logic to handle any ossible deendencies between the instructions Hybrid aroaches Issue logic can become bottleneck Dynamic Schedu uling, Mu ultile Iss sue, and Seculat tion Coyright 2012, Elsevier Inc. All rights reserved. 48

49 Dynamic Scheduling, Multile Issue, and Seculation Overview of Design Coyright 2012, Elsevier Inc. All rights reserved. 49

50 Multile Issue Limit the number of instructions of a given class that can be issued in a bundle I.e. on FP, one integer, one load, one store Examine all the deendencies amoung the instructions in the bundle If deendencies d exist in bundle, encode them in reservation stations Also need multile comletion/commit Dynamic Schedu uling, Mu ultile Iss sue, and Seculat tion Coyright 2012, Elsevier Inc. All rights reserved. 50

51 Examle Loo: LD R2,0(R1) ;R2=array element DADDIU R2,R2,#1 ;increment R2 SD R2,0(R1) ;store result DADDIU R1,R1,#8 ;increment ointer BNE R2,R3,LOOP ;branch if not last element Dynamic Schedu uling, Mu ultile Issue, and Seculation Coyright 2012, Elsevier Inc. All rights reserved. 51

52 Dynamic Scheduling, Multile Issue, and Seculation Examle (No Seculation) Coyright 2012, Elsevier Inc. All rights reserved. 52

53 Dynamic Scheduling, Multile Issue, and Seculation Examle Coyright 2012, Elsevier Inc. All rights reserved. 53

54 Branch-Target Buffer Need high instruction bandwidth! Branch-Target buffers Next PC rediction buffer, indexed by current PC Adv. Tec chniques for Instruction Delivery and Seculation Coyright 2012, Elsevier Inc. All rights reserved. 54

55 Branch Folding Otimization: Larger branch-target buffer Add target instruction into buffer to deal with longer decoding di time required by larger buffer Branch folding Adv. Tec chniques for Instr ruction Delivery and Seculation Coyright 2012, Elsevier Inc. All rights reserved. 55

56 Return Address Predictor Most unconditional branches come from function returns The same rocedure can be called from multile sites Causes the buffer to otentially forget about the return address from revious calls Create return address buffer organized as a stack Adv. Tec chniques for Instr ruction D elivery a nd Seculation Coyright 2012, Elsevier Inc. All rights reserved. 56

57 Integrated Instruction Fetch Unit Design monolithic unit that erforms: Branch rediction Instruction refetch Fetch ahead Instruction memory access and buffering Deal with crossing cache lines Adv. Tec chniques for Instr ruction D elivery and Seculation Coyright 2012, Elsevier Inc. All rights reserved. 57

58 How Much? How much to seculate Mis-seculation degrades erformance and ower relative to no seculation May cause additional misses (cache, TLB) Prevent seculative code from causing higher costing misses (e.g. L2) Seculating through multile branches Comlicates seculation recovery No rocessor can resolve multile l branches er cycle Adv. Tec chniques for Instr ruction D elivery a nd Secu ulation Coyright 2012, Elsevier Inc. All rights reserved. 58

59 Review What is Control Seculation? What is Data Seculation? What are the advantages of a suerscalar vs a VLIW? What are the disadvantages of a suerscalar vs a VLIW? When is a VLIW aroriate? When is a suerscalar aroriate? Multile Issue an nd Static Schedul ling Coyright 2012, Elsevier Inc. All rights reserved. 59