512MB 64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package

Transcription

1 52MB 64M x 72 DDR2 SDRAM 28 PBGA Muli-Chip Package FEATURES Daa rae = 667, 533, 4 Mb/s Package: 28 Plasic Ball Grid Array (PBGA), 6 x 22mm.mm pich Single Supply Volage =.8V Differenial daa srobe (DQS, DQS#) per bye Inernal, pipelined, double daa rae archiecure 4-bi prefech archiecure DLL for alignmen of DQ and DQS ransiions wih clock signal Eigh inernal banks for concurren operaion (Per DDR2 SDRAM Die) Programmable Burs lenghs: 4 or 8 Auo Refresh and Self Refresh Modes On Die Terminaion (ODT) Adjusable daa oupu drive srengh Programmable CAS laency: 3, 4 or 5 Posed CAS addiive laency:,, 2, 3 or 4 Wrie laency = Read laency - * CK Commercial, Indusrial and Miliary Temperaure Rang es Organized as 64M x 72 Weigh: W3H64M72E-XSBX grams ypical BENEFITS 3% Space saving vs. FBGA Re duced par coun 5% I/O reducion vs FBGA Re duced race lenghs for low er par a si ic ca pac i ance Sui able for hi-re li abil i y ap pli ca ions Upgradable o 28M x 72 den si y (con ac fac o ry for informaion) Lead free - available (Pb free - componen and maerial are lead free in accordance wih IPC-752) * This produc is subjec o change wihou noice. Hos FPGA/ Processor TYPICAL APPLICATION RAM DDR2/DDR3 W3X28M72-XBI SSD (SLC) MSM32/MSM64 (SATA BGA) W7N6GVHxxBI (PATA BGA) M4/M/M5 (SATA, 2.5in) FIGURE DENSITY COMPARISONS FBGA CSP Approach (mm) FBGA FBGA FBGA FBGA W3H64M72E-XSBX 22 W3H64M72E-XSBX 6 S A V I N G S Area 5 x mm 2 = 5mm 2 352mm 2 3% I/O Coun 5 x 84 balls = 42 balls 28 Balls 5% Augus 2 2 Microsemi Corporaion. All righs reserved. Microsemi Corporaion (62) Rev. 2

2 FIGURE 2 FUTIONAL BLOCK DIAGRAM CS# WE# RAS# CAS# CKE ODT A-2 BA-2 CK CK# LDM UDM LDQS LDQS# UDQS UDQS# CS# WE# ODT A-2 BA-2 CK CK# LDM UDM LDQS LDQS# UDQS UDQS# RAS# CAS# CKE U DQ DQ5 DQ DQ5 CK CK# LDM UDM LDQS LDQS# UDQS UDQS# CS# WE# ODT A-2 BA-2 CK CK# LDM UDM LDQS LDQS# UDQS UDQS# RAS# CAS# CKE U DQ DQ5 DQ6 DQ3 CK2 CK2# LDM2 UDM2 LDQS2 LDQS2# UDQS2 UDQS2# CS# WE# ODT A-2 BA-2 CK CK# LDM UDM LDQS LDQS# UDQS UDQS# RAS# CAS# CKE U2 DQ DQ5 DQ32 DQ47 CK3 CK3# LDM3 UDM3 LDQS3 LDQS3# UDQS3 UDQS3# CS# ODT A-2 BA-2 CK CK# LDM UDM LDQS LDQS# UDQS UDQS# WE# RAS# CAS# CKE U3 DQ DQ5 DQ48 DQ63 CK4 CK4# LDM4 LDQS4 LDQS4# UDQS4 UDQS4# CS# WE# ODT A-2 BA-2 CK CK# LDM UDM LDQS LDQS# UDQS UDQS# RAS# CAS# U4 CKE DQ DQ7 DQ64 DQ7 Augus 2 2 Microsemi Corporaion. All righs reserved. 2 Microsemi Corporaion (62) Rev. 2

3 FIGURE 3 PIN CONFIGURATION TOP VIEW A B C DQ34 CK3 CK3# D DQ35 DQ5 DQ5 DQ53 DQ37 CK2# CK2 E DQ52 DQ36 DQ33 BA2 DNU DQ39 LDQS2 LDQS3 DQ48 DQ32 F LDM3 LDM2 DQ49 DQ43 DQ59 DNU DQ55 DQ58 DQ42 LDQS2# LDQS3# G DQ38 DQ54 DQ6 DQ57 UDM2 DQ63 DQ56 DQ4 DQ6 DQ45 H UDM3 DQ44 DQ4 DQ46 DQ62 UDQS2# DQ47 UDQS2 UDQS3 UDQS3# J A6 A A9 A3 A2 DNU* K A A VREF A BA L A2 A4 A8 BA A5 A7 M UDQS# UDQS UDQS DQ5 UDQS# DQ3 DQ4 DQ9 DQ2 UDM N DQ3 DQ29 DQ8 DQ24 DQ3 UDM DQ25 DQ28 DQ22 DQ6 P LDQS# LDQS# DQ DQ26 DQ23 ODT DQ27 DQ DQ7 LDM LDM R DQ DQ6 LDQS LDQS DQ7 LDQS4# UDQS4 UDQS4# DQ DQ4 DQ2 T CK CK# DQ5 DQ2 DQ8 LDQS4 DQ7 CKE WE# DQ9 DQ3 U CK# CK DQ2 RAS# CAS# DQ64 DQ7 DQ65 DQ68 V CK4# CK4 CS# DQ66 DQ69 LDM4 DQ67 W Vcc * Pin J is reserved for signal A3 on 28Mx72 and higher densiies. Noe: UDQS4 and UDQS4# require a KΩ pull up resisor. UDM4 is inernally ied o Vcc Augus 2 2 Microsemi Corporaion. All righs reserved. 3 Microsemi Corporaion (62) Rev. 2

4 TABLE BALL DESCRIPTIONS Symbol Type Descripion ODT CK, CK# CKE Inpu Inpu Inpu On-Die erminaion: ODT (regisered HIGH) enables erminaion resisance inernal o he DDR2 SDRAM. When enabled, ODT is only applied o each of he following balls: DQ DQ7, LDM, UDM, LDQS, LDQS#, UDQS, and UDQS#. The ODT inpu will be ignored if disabled via he LOAD MODE command. Clock: CK and CK# are differenial clock inpus. All address and conrol inpu signals are sampled on he crossing of he posiive edge of CK and negaive edge of CK#. Oupu daa (DQs and DQS/DQS#) is referenced o he crossings of CK and CK#. Clock enable: CKE (regisered HIGH) acivaes and CKE (regisered LOW) deacivaes clocking circuiry on he DDR2 SDRAM. The specific circuiry ha is enabled/disabled is dependen on he DDR2 SDRAM configuraion and operaing mode. CKE LOW provides PRECHARGE power-down mode and SELF-REFRESH acion (all banks idle), or ACTIVE power-down (row acive in any bank). CKE is synchronous for power-down enry, Power-down exi, oupu disable, and for self refresh enry. CKE is asynchronous for self refresh exi. Inpu buffers (excluding CKE, and ODT) are disabled during power-down. Inpu buffers (excluding CKE) are disabled during self refresh. CKE is an SSTL_8 inpu bu will deec a LVCMO SLOW level once is applied during firs power-up. Afer VREF has become sable during he power on and iniializaion sequence, i mus be mainained for proper operaion of he CKE receiver. For proper SELF-REFRESH operaion, VREF mus be mainained. CS# Inpu Chip selec: CS# enables (regisered LOW) and disables (regisered HIGH) he command decoder. All commands are masked when CS# is regisered HIGH. RAS#, CAS#, WE# Inpu Command inpus: RAS#, CAS#, WE# (along wih CS#) define he command being enered. LDM, UDM BA BA2 Inpu Inpu Inpu daa mask: DM is an inpu mask signal for wrie daa. Inpu daa is masked when DM is concurrenly sampled HIGH during a WRITE access. DM is sampled on boh edges of DQS. Alhough DM balls are inpu-only, he DM loading is designed o mach ha of DQ and DQS balls. LDM is DM for lower bye DQ DQ7 and UDM is DM for upper bye DQ8 DQ5, of each of U-U4 Bank address inpus: BA BA2 define o which bank an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. BA BA2 define which mode regiser including MR, EMR, EMR(2), and EMR(3) is loaded during he LOAD MODE command. A-A2 Inpu Address inpus: Provide he row address for ACTIVE commands, and he column address and auo precharge bi (A) for READ/ WRITE commands, o selec one locaion ou of he memory array in he respecive bank. A sampled during a PRECHARGE command deermines wheher he PRECHARGE applies o one bank (A LOW, bank seleced by BA2 BA) or all banks (A HIGH) The address inpus also provide he op-code during a LOAD MODE command. DQ-7 I/O Daa inpu/oupu: Bidirecional daa bus UDQS, UDQS# LDQS, LDQS# I/O I/O Daa srobe for upper bye: Oupu wih read daa, inpu wih wrie daa for source synchronous operaion. Edge-aligned wih read daa, cener-aligned wih wrie daa. UDQS# is only used when differenial daa srobe mode is enabled via he LOAD MODE command. Daa srobe for lower bye: Oupu wih read daa, inpu wih wrie daa for source synchronous operaion. Edge-aligned wih read daa, cener-aligned wih wrie daa. LDQS# is only used when differenial daa srobe mode is enabled via he LOAD MODE command. Supply Power Supply: I/O + Core, Q is common o VREF Supply SSTL_8 reference volage. Supply Ground - No connec: These balls should be lef unconneced. DNU - Fuure use Augus 2 2 Microsemi Corporaion. All righs reserved. 4 Microsemi Corporaion (62) Rev. 2

5 DESCRIPTION The 4Gb DDR2 SDRAM is a high-speed CMOS, dynamic randomaccess memory conaining 4,294,967,296 bis. Each of he fi ve chips in he MCP are inernally confi gured as 8-bank DRAM. The block diagram of he device is shown in Figure 2. Ball assignmens and are shown in Figure 3. The 4Gb DDR2 SDRAM uses a double-daa-rae archiecure o achieve high-speed operaion. The double daa rae archiecure is essenially a 4n-prefech archiecure, wih an inerface designed o ransfer wo daa words per clock cycle a he I/O balls. A single read or wrie access for he 4Gb DDR2 SDRAM effecively consiss of a single 4n-bi-wide, one-clock-cycle daa ransfer a he inernal DRAM core and four corresponding n-bi-wide, one-half-clock-cycle daa ransfers a he I/O balls. A bidirecional daa srobe (DQS, DQS#) is ransmied exernally, along wih daa, for use in daa capure a he receiver. DQS is a srobe ransmied by he DDR2 SDRAM during READs and by he memory conroller during WRITEs. DQS is edge-aligned wih daa for READs and cener-aligned wih daa for WRITEs. There are srobes, one for he lower bye (LDQS, LDQS#) and one for he upper bye (UDQS, UDQS#). The 4Gb DDR2 SDRAM operaes from a differenial clock (CK and CK#); he crossing of CK going HIGH and CK# going LOW will be referred o as he posiive edge of CK. Commands (address and conrol signals) are regisered a every posiive edge of CK. Inpu daa is regisered on boh edges of DQS, and oupu daa is referenced o boh edges of DQS, as well as o boh edges of CK. Read and wrie accesses o he DDR2 SDRAM are burs oriened; accesses sar a a seleced locaion and coninue for a programmed number of locaions in a programmed sequence. Accesses begin wih he regisraion of an ACTIVE command, which is hen followed by a READ or WRITE command. The address bis regisered coinciden wih he ACTIVE command are used o selec he bank and row o be accessed. The address bis regisered coinciden wih he READ or WRITE command are used o selec he bank and he saring column locaion for he burs access. The DDR2 SDRAM provides for programmable read or wrie burs lenghs of four or eigh locaions. DDR2 SDRAM suppors inerruping a burs read of eigh wih anoher read, or a burs wrie of eigh wih anoher wrie. An auo precharge funcion may be enabled o provide a self-imed row precharge ha is iniiaed a he end of he burs access. As wih sandard DDR SDRAMs, he pipelined, mulibank archiecure of DDR2 SDRAMs allows for concurren operaion, hereby providing high, effecive bandwidh by hiding row precharge and acivaion ime. A self refresh mode is provided, along wih a power-saving powerdown mode. All inpus are compaible wih he JEDEC sandard for SSTL_8. All full drive-srengh oupus are SSTL_8-compaible. GENERAL NOTES The funcionaliy and he iming specifi caions discussed in his daa shee are for he DLL-enabled mode of operaion. Throughou he daa shee, he various fi gures and ex refer o DQs as DQ. The DQ erm is o be inerpreed as any and all DQ collecively, unless specifi cally saed oherwise. Addiionally, each chip is divided ino 2 byes, he lower bye and upper bye. For he lower bye (DQ DQ7), DM refers o LDM and DQS refers o LDQS. For he upper bye (DQ8 DQ5), DM refers o UDM and DQS refers o UDQS. Complee funcionaliy is described hroughou he documen and any page or diagram may have been simplifi ed o convey a opic and may no be inclusive of all requiremens. Any specifi c requiremen akes precedence over a general saemen. INITIALIZATION DDR2 SDRAMs mus be powered up and iniialized in a predefi ned manner. Operaional procedures oher han hose specifi ed may resul in undefi ned operaion. The following sequence is required for power up and iniializaion and is shown in Figure 4 on page 7. Augus 2 2 Microsemi Corporaion. All righs reserved. 5 Microsemi Corporaion (62) Rev. 2

6 FIGURE 4 POWER-UP AND INITIALIZATION L Q VTD V Vref CK# CK T CK CL CL Ta Tb Tc Td Te Tf Tg Th Ti Tj Tk Tl Tm LVCMOS CKE low level 2 SSTL_8 low level 2 ODT Command NOP 3 PRE LM 5 LM 6 LM7 LM 8 PRE 9 REF REF LM LM 2 LM 3 Valid 4 DM 5 Address 6 A = Code Code Code Code A = Code Code Code Valid DQS 5 DQ 5 R High-Z High-Z High-Z T = 2μs (MIN) 3 T = 4ns (MIN) 4 RPA MRD MRD MRD MRD RPA RFC RFC MRD MRD MRD Power-up: Vdd and sable clock (CK, CK#) EMR(2) EMR(3) EMR See no e MR wihou EMR wih EMR wih DLL RESET OCD defaul OCD exi 2 cycles of CK are required before a READ command can be issued MR wih DLL RESET Indicaes a Break in Time Scale Normal operaion Don care NOTES:. Applying power; if CKE is mainained below.2 x Q, oupus remain disabled. To guaranee RTT (ODT resisance) is off, VREF mus be valid and a low level mus be applied o he ODT ball (all oher inpus may be undefined, I/Os and oupus mus be less han Q during volage ramp ime o avoid DDR2 SDRAM device lach-up). A leas one of he following wo ses of condiions (A or B) mus be me o obain a sable supply sae (sable supply defined as, Q,VREF, and VTT are beween heir minimum and maximum values as saed in DC Operaing Condiions able): A. (single power source) The volage ramp from 3mV o (MIN) mus ake no longer han 2ms; during he volage ramp, - Q.3V. Once supply volage ramping is complee (when Q crosses (MIN), DC Operaing Condiions able specificaions apply., Q are driven from a single power converer oupu VTT is limied o.95v MAX VREF racks Q/2; VREF mus be wihin ±.3V wih respec o Q/2 during supply ramp ime. Q VREF a all imes B. (muliple power sources) Q mus be mainained during supply volage ramping, for boh AC and DC levels, unil supply volage ramping complees (Q crosses [MIN]). Once supply volage ramping is complee, DC Operaing Condiions able specificaions apply. Apply before or a he same ime as Q; volage ramp ime mus be 2ms from when ramps from 3mV o (MIN) Apply Q before or a he same ime as VTT; he Q volage ramp ime from when (MIN) is achieved o when Q (MIN) is achieved mus be 5ms; while is ramping, curren can be supplied from hrough he device o Q VREF mus rack Q/2, VREF mus be wihin ±.3V wih respec o Q/2 during supply ramp ime; Q VREF mus be me a all imes Apply VTT; The VTT volage ramp ime from when Q (MIN) is achieved o when VTT (MIN) is achieved mus be no greaer han 5ms 2. CKE uses LVCMOS inpu levels prior o sae T o ensure DQs are High-Z during device powerup prior o VREF. being sable. Afer sae T, Cke is required o have SSTL_8 inpu levels. Once CKE ransiions o a high level, i mus say HIGH for he duraion on he iniializaion sequence. 3. PRE = PRECHARGE command, LM = LOAD MODE command, MR = Mode Regiser, EMR = exended mode regiser, EMR2 = exended mode regiser 2, EMR3 = exended mode regiser 3, REF = REFRESH command, ACT = ACTIVE command, A = PRECHARGE ALL, CODE = desired value for mode regisers (blank addresses are required o be decoded), VALID - any valid command/address, RA = row address, bank address. 4. DM represens UDM & LDM, DQS represens, UDQS, UDQS#, LDQS, LDQS#, RDQS, RDQS#, DQ represens DQ For a minimum of 2μs afer sable power and clock (CK, CK#), apply NOP or DESELECT commands, hen ake CKE HIGH. 6. Wai a minimum of 4ns, hen issue a PRECHARGE ALL command. 7. Issue a LOAD MODE command o he EMR(2). (To issue an EMR(3) command, provide LOW o BA2 and BA, and provide HIGH o BA.) Se regiser E7 o "" or ";" all ohers mus be "". 8. Issue LOAD MODE command o he EMR(3). (o issue and EMR(3) command, provide HIGH o BA =, BA =, and BA2 =.) Se all regisers o "". 9. Issue a LOAD MODE command o he EMR o enable DLL. To issue a CLL ENABLE command provide LOW o BA, BA2 and A; provide HIGH o BA. Bis E7, E8 and E9 can be se o "" or ";" Micron recommends seing hem o "".. Issue a LOAD MODE command for DLL RESET. 2 cycles of clock inpu is required o lock he DLL. (To issue a DLL RESET, provide HIGH o A8 and provide LOW o BA2 = BA = BA =.) CKE mus be HIGH he enire ime... Issue PRECHARGE ALL command. 2. Issue wo or more REFRESH commands. 3. Issue a LOAD MODE command wih LOW o A8 o iniialize device operaion (i.e., o program operaing parameers wihou reseing he DLL). To access he mode regisers, BA =, BA =, BA2 =. 4. Issue a LOAD MODE command o he EMR o enable OCD defaul by seing bis E7, E8, and E9 o, and hen seing all oher desired parameers. To access he exended mode regiser, BA2 =, BA =, BA =. 5. Issue a LOAD MODE command o he EMR o enable OCD exi by seing bis E7, E8, and E9 o, and hen seing all oher desired parameers. To access he exended mode regisers, BA2 =, BA =, BA =. 6. The DDR2 SDRAM is now iniialized and ready for normal operaion 2 clock cycles afer he DLL RESET a Tf. Augus 2 2 Microsemi Corporaion. All righs reserved. 6 Microsemi Corporaion (62) Rev. 2

7 MODE REGISTER (MR) The mode regiser is used o define he specific mode of operaion of he DDR2 SDRAM. This defi niion includes he selecion of a burs lengh, burs ype, CL, operaing mode, DLL RESET, wrie recovery, and power-down mode, as shown in Figure 5. Conens of he mode regiser can be alered by re-execuing he LOAD MODE (LM) command. If he user chooses o modify only a subse of he MR variables, all variables (M M4) mus be programmed when he command is issued. The mode regiser is programmed via he LM command (bis BA2 BA =,, ) and oher bis (M2 M) will reain he sored informaion unil i is programmed again or he device loses power (excep for bi M8, which is self-clearing). Reprogramming he mode regiser will no aler he conens of he memory array, provided i is performed correcly. The LM command can only be issued (or reissued) when all banks are in he precharged sae (idle sae) and no burss are in progress. The conroller mus wai he specifi ed ime MRD before iniiaing any subsequen operaions such as an ACTIVE command. Violaing eiher of hese requiremens will resul in unspecifi ed operaion. BURST LENGTH Burs lengh is defined by bis M M3, as shown in Figure 5. Read and wrie accesses o he DDR2 SDRAM are burs-oriened, wih he burs lengh being programmable o eiher four or eigh. The burs lengh dee rmines he maximum number of column locaions ha can be accessed for a given READ or WRITE command. When a READ or WRITE command is issued, a block of columns equal o he burs lengh is effecively seleced. All accesses for ha burs ake place wihin his block, meaning ha he burs will wrap wihin he block if a boundary is reached. The block is uniquely seleced by A2 Ai when BL = 4 and by A3 Ai when BL = 8 (where Ai is he mos signifi can column address bi for a given confi guraion). The remaining (leas signifi can) address bi(s) is (are) used o selec he saring locaion wihin he block. The programmed burs lengh applies o boh READ and WRITE burss. FIGURE 5 MODE REGISTER (MR) DEFINITION BA2 BA BA MR A3 A2 A A 3 M2 2 PD PD mode Fas Exi (Normal) Slow Exi (Low Power) A9 A8 A7 A6 A5 A4 A3 A2 A A WR DLL TM CAS# Laency BT Burs Lengh M7 Mode Normal Tes M8 DLL Rese No Yes M M M9 WRITE RECOVERY M6 M5 M4 Mode Regiser Definiion Mode Regiser (MR) Exended Mode Regiser (EMR) Exended Mode Regiser (EMR2) Exended Mode Regiser (EMR3) M3 M6 M5 M4 Address Bus Mode Regiser (Mx) M2 M M Burs Lengh 4 8 Burs Type Sequenial Inerleaved CAS Laency (CL) Noe:. A3 is no used on his device 2. No all lised CL opions are suppored in any individual speed grades BURST TYPE Accesses wihin a given burs may be programmed o be eiher sequenial or inerleaved. The burs ype is seleced via bi M3, as shown in Figure 5. The ordering of accesses wihin a burs is deermined by he burs lengh, he burs ype, and he saring column address, as shown in Table 2. DDR2 SDRAM suppors 4-bi burs mode and 8-bi burs mode only. For 8-bi burs mode, full inerleave address ordering is suppored; however, sequenial address ordering is nibble-based. Augus 2 2 Microsemi Corporaion. All righs reserved. 7 Microsemi Corporaion (62) Rev. 2

8 Burs Lengh 4 TABLE 2 BURST DEFINITION Saring Column Address Order of Accesses Wih in a Burs Type = Sequenial Type = In er leaved A A A2 A A NOTES:. For a burs lengh of wo, A-Ai selec wo-daa-elemen block; A selecs he saring column wihin he block. 2. For a burs lengh of four, A2-Ai selec four-daa-elemen block; A- selec he saring column wihin he block. 3. For a burs lengh of eigh, A3-Ai selec eigh-daa-elemen block; A-2 selec he saring column wihin he block. 4. Whenever a boundary of he block is reached wihin a given sequence above, he following access wraps wihin he block. WR values of 2, 3, 4, 5, or 6 clocks may be used for programming bis M9 M. The user is required o program he value of WR, which is calculaed by dividing WR (in ns) by CK (in ns) and rounding up a non ineger value o he nex ineger; WR [cycles] = WR [ns] / CK [ns]. saes should no be used as unknown operaion or incompaibiliy wih fuure versions may resul. POWER-DOWN MODE Acive power-down (PD) mode is defi ned by bi M2, as shown in Figure 5. PD mode allows he user o deermine he acive power-down mode, which deermines performance versus power savings. PD mode bi M2 does no apply o precharge PD mode. When bi M2 =, sandard acive PD mode or fas-exi acive PD mode is enabled. The XARD parameer is used for fas-exi acive PD exi iming. The DLL is expeced o be enabled and running during his mode. When bi M2 =, a lower-power acive PD mode or slow-exi acive PD mode is enabled. The XARD parameer is used for slowexi acive PD exi iming. The DLL can be enabled, bu frozen during acive PD mode since he exi-o-read command iming is relaxed. The power difference expeced beween PD normal and PD low-power mode is defi ned in he ICC able. OPERATING MODE The normal operaing mode is seleced by issuing a command wih bi M7 se o, and all oher bis se o he desired values, as shown in Figure 5. When bi M7 is, no oher bis of he mode regiser are programmed. Programming bi M7 o places he DDR2 SDRAM ino a es mode ha is only used by he manufacurer and should no be used. No operaion or funcionaliy is guaraneed if M7 bi is. DLL RESET DLL RESET is defined by bi M8, as shown in Figure 5. Programming bi M8 o will acivae he DLL RESET funcion. Bi M8 is self-clearing, meaning i reurns back o a value of afer he DLL RESET funcion has been issued. Anyime he DLL RESET funcion is used, 2 clock cycles mus occur before a READ command can be issued o allow ime for he inernal clock o be synchronized wih he exernal clock. Failing o wai for synchronizaion o occur may resul in a violaion of he AC or DQSCK parameers. WRITE RECOVERY Wrie recovery (WR) ime is defi ned by bis M9 M, as shown in Figure 5. The WR regiser is used by he DDR2 SDRAM during WRITE wih auo precharge operaion. During WRITE wih auo precharge operaion, he DDR2 SDRAM delays he inernal auo precharge operaion by WR clocks (programmed in bis M9 M) from he las daa burs. Augus 2 2 Microsemi Corporaion. All righs reserved. 8 Microsemi Corporaion (62) Rev. 2

9 CAS LATEY (CL) The CAS laency (CL) is defined by bis M4 M6, as shown in Figure 5. CL is he delay, in clock cycles, beween he regisraion of a READ command and he availabiliy of he fi rs bi of oupu daa. The CL can be se o 3, 4, 5, or 6 clocks, depending on he speed grade opion being used. DDR2 SDRAM does no suppor any half-clock laencies. saes should no be used as unknown operaion or incompaibiliy wih fuure versions may resul. DDR2 SDRAM also suppors a feaure called posed CAS addiive laency (AL). This feaure allows he READ command o be issued prior o RCD (MIN) by delaying he inernal command o he DDR2 SDRAM by AL clocks. Examples of CL = 3 and CL = 4 are shown in Figure 6; boh assume AL =. If a READ command is regisered a clock edge n, and he CL is m clocks, he daa will be available nominally coinciden wih clock edge n+m (his assumes AL = ). FIGURE 6 CAS LATEY (CL) CK# T T T2 T3 T4 T5 T6 CK COMMAND READ NOP NOP NOP NOP NOP NOP DQS, DQS# DQ CL = 3 (AL = ) DOUT n DOUT n + DOUT n + 2 DOUT n + 3 CK# T T T2 T3 T4 T5 T6 CK COMMAND READ NOP NOP NOP NOP NOP NOP DQS, DQS# DQ CL = 4 (AL = ) DOUT n DOUT n + DOUT n + 2 DOUT n + 3 Burs lengh = 4 Posed CAS# addiive laency (AL) = Shown wih nominal AC, DQSCK and DQSQ TRANSITIONING DATA DON T CARE Augus 2 2 Microsemi Corporaion. All righs reserved. 9 Microsemi Corporaion (62) Rev. 2

10 EXTENDED MODE REGISTER (EMR) The exended mode regiser conrols funcions beyond hose conrolled by he mode regiser; hese addiional funcions are DLL enable/disable, oupu drive srengh, on die erminaion (ODT) (RTT), posed AL, off-chip driver impedance calibraion (OCD), DQS# enable/disable, RDQS/RDQS# enable/disable, and oupu disable/enable. These funcions are conrolled via he bis shown in Figure 7. The EMR is programmed via he LOAD MODE (LM) command and will reain he sored informaion unil i is programmed again or he device loses power. Reprogramming he EMR will no aler he conens of he memory array, provided i is performed correcly. The EMR mus be loaded when all banks are idle and no burss are in progress, and he conroller mus wai he specifi ed ime MRD before iniiaing any subsequen operaion. Violaing eiher of hese requiremens could resul in unspecifi ed operaion. FIGURE 7 EXTENDED MODE REGISTER DEFINITION BA2 BA BA A3 A2 A A A9 A8 A7 A6 A5 A4 A3 A2 A A Address Bus 6 5 MRS ou RDQS DQS# OCD Program RTT Posed CAS# RTT ODS DLL Exended Mode Regiser (Ex) E2 Oupus E DLL Enable Enabled E6 E2 RTT (nominal) Enable (Normal) Disabled RTT disabled Disable (Tes/Debug) E RDQS Enable 75Ω 5Ω E Oupu Drive Srengh No 5Ω Full srengh (8 Ω arge) Yes Reduced srengh (4 Ω arge) E DQS# Enable Enable Disable E9 E8 E7 OCD Operaion OCD no suppored OCD defaul sae E5 E4 E3 Posed CAS# Addiive Laency (AL) E6 E5 E4 Mode Regiser Se Mode regiser se (MRS) Exended mode regiser (EMRS) Exended mode regiser (EMRS2) Exended mode regiser (EMRS3) Noe:. During iniializaion, all hree bis mus be se o "" for OCD defaul sae, hen mus be se o "" before iniializaion is finished, as deailed in he iniializaion procedure. 2. E3 (A3) is no used on his device. Augus 2 2 Microsemi Corporaion. All righs reserved. Microsemi Corporaion (62) Rev. 2

11 DLL ENABLE/DISABLE The DLL may be enabled or disabled by programming bi E during he LM command, as shown in Figure 7. The DLL mus be enabled for normal operaion. DLL enable is required during power-up iniializaion and upon reurning o normal operaion afer having disabled he DLL for he purpose of debugging or evaluaion. Enabling he DLL should always be followed by reseing he DLL using an LM command. The DLL is auomaically disabled when enering SELF REFRESH operaion and is auomaically re-enabled and rese upon exi of SELF REFRESH operaion. Any ime he DLL is enabled (and subsequenly rese), 2 clock cycles mus occur before a READ command can be issued, o allow ime for he inernal clock o synchronize wih he exernal clock. Failing o wai for synchronizaion o occur may resul in a violaion of he AC or DQSCK parameers. OUTPUT DRIVE STRENGTH The oupu drive srengh is defined by bi E, as shown in Figure 7. The normal drive srengh for all oupus are specifi ed o be SSTL_8. Programming bi E = selecs normal (full srengh) drive srengh for all oupus. Selecing a reduced drive srengh opion (E = ) will reduce all oupus o approximaely 6 percen of he SSTL_8 drive srengh. This opion is inended for he suppor of ligher load and/or poin-o-poin environmens. eleced by enabling swich sw, which enables all R values ha are 5Ω each, enabling an effecive resisance of 75Ω (RTT2(EFF) = R2/2). Similarly, if sw2 is enabled, all R2 values ha are 3Ω each, enable an effecive ODT resisance of 5Ω (RTT2(EFF) = R2/2). Swich sw3 enables R values of Ω enabling effecive resisance of 5Ω saes should no be used, as unknown operaion or incompaibiliy wih fuure versions may resul. The ODT conrol ball is used o deermine when RTT(EFF) is urned on and off, assuming ODT has been enabled via bis E2 and E6 of he EMR. The ODT feaure and ODT inpu ball are only used during acive, acive power-down (boh fas-exi and slow-exi modes), and precharge power-down modes of operaion. ODT mus be urned off prior o enering self refresh. During power-up and iniializaion of he DDR2 SDRAM, ODT should be disabled unil issuing he EMR command o enable he ODT feaure, a which poin he ODT ball will deermine he RTT(EFF) value. Any ime he EMR enables he ODT funcion, ODT may no be driven HIGH unil eigh clocks afer he EMR has been enabled. See ODT Timing secion for ODT iming diagrams. DQS# ENABLE/DISABLE The DQS# ball is enabled by bi E. When E =, DQS# is he complemen of he differenial daa srobe pair DQS/DQS#. When disabled (E = ), DQS is used in a single ended mode and he DQS# ball is disabled. When disabled, DQS# should be lef floaing. This funcion is also used o enable/disable RDQS#. If RDQS is enabled (E = ) and DQS# is enabled (E = ), hen boh DQS# and RDQS# will be enabled. OUTPUT ENABLE/DISABLE The OUTPUT ENABLE funcion is defi ned by bi E2, as shown in Figure 7. When enabled (E2 = ), all oupus (DQs, DQS, DQS#, RDQS, RDQS#) funcion normally. When disabled (E2 = ), all DDR2 SDRAM oupus (DQs, DQS, DQS#, RDQS, RDQS#) are disabled, hus removing oupu buffer curren. The oupu disable feaure is inended o be used during ICC characerizaion of read curren. ON-DIE TERMINATION (ODT) ODT effecive resisance, RTT (EFF), is defi ned by bis E2 and E6 of he EMR, as shown in Figure 7. The ODT feaure is designed o improve signal inegriy of he memory channel by allowing he DDR2 SDRAM conroller o independenly urn on/off ODT for any or all devices. RTT effecive resisance values of 5Ω,75Ω, and 5Ω are selecable and apply o each DQ, DQS/DQS#, RDQS/ RDQS#, UDQS/UDQS#, LDQS/LDQS#, and UDM/LDM signals. Bis (E6, E2) deermine wha ODT resisance is enabled by urning on/off sw, sw2, or sw3. The ODT effecive resisance value is Augus 2 2 Microsemi Corporaion. All righs reserved. Microsemi Corporaion (62) Rev. 2

12 POSTED CAS ADDITIVE LATEY (AL) Posed CAS addiive laency (AL) is suppored o make he command and daa bus effi cien for susainable bandwidhs in DDR2 SDRAM. Bis E3 E5 defi ne he value of AL, as shown in Figure 7. Bis E3 E5 allow he user o program he DDR2 SDRAM wih an inverse AL of,, 2, 3, or 4 clocks. saes should no be used as unknown operaion or incompaibiliy wih fuure versions may resul. In his operaion, he DDR2 SDRAM allows a READ or WRITE command o be issued prior o RCD (MIN) wih he requiremen ha AL RCD (MIN). A ypical applicaion using his feaure would se AL = RCD (MIN) - x CK. The READ or WRITE command is held for he ime of he AL before i is issued inernally o he DDR2 SDRAM device. RL is conrolled by he sum of AL and CL; RL = AL+CL. Wrie laency (WL) is equal o RL minus one clock; WL = AL + CL - x CK. FIGURE 8 EXTENDED MODE REGISTER 2 (EMR2) DEFINITION BA2 BA BA A4 A3 A2 A A A9 A8 A7 A6 A5 A4 A3 A2 A A Address Bus 7 6 EMR Exended Mode Regiser (Ex) M7 M6 M5 Mode Regiser Definiion Mode regiser (MR) Exended mode regiser (EMR) Exended mode regiser (EMR2) Exended mode regiser (EMR3) E7 High Temperaure Self Refresh rae enable Commercial emperaure defaul Indusrial emperaure opion; use if T C exceeds 85 C Noe:. E3 (A3)-E(A) are reserved for fuure use and mus be programmed o "." A3 is no used in his device. Augus 2 2 Microsemi Corporaion. All righs reserved. 2 Microsemi Corporaion (62) Rev. 2

13 FIGURE 9 EXTENDED MODE REGISTER 3 (EMR3) DEFINITION BA2 BA BA A3 A2 A A A9 A8 A7 A 6 A5 A4 A3 A2 A A Address Bus EMR3 Exended Mo de Regiser (Ex) M6 M5 M4 Mode Regiser Definiion Mode regiser (MR) Exended mode regiser (EMR) Exended mode regiser (EMR2) Exended mode regiser (EMR3) Noe:. E3 (A3)-E (A) are reserved for fuure use and mus be programmed o "." A3 is no used in his device. EXTENDED MODE REGISTER 2 The exended mode regiser 2 (EMR2) conrols funcions beyond hose conrolled by he mode regiser. Currenly all bis in EMR2 are reserved, as shown in Figure 8. The EMR2 is programmed via he LM command and will reain he sored informaion unil i is programmed again or he device loses power. Reprogramming he EMR will no aler he conens of he memory array, provided i is performed correcly. Bi E7 (A7) mus be programmed as"" o provide a faser refresh rae on devices if he CASE exceeds 85 C EMR2 mus be loaded when all banks are idle and no burss are in progress, and he conroller mus wai he specifi ed ime MRD before iniiaing any subsequen operaion. Violaing eiher of hese requiremens could resul in unspecifi ed operaion. COMMAND TRUTH TABLES The following ables provide a quick reference of DDR2 SDRAM available commands, including CKE power-down modes, and bank-o-bank commands. EXTENDED MODE REGISTER 3 The exended mode regiser 3 (EMR3) conrols funcions beyond hose conrolled by he mode regiser. Currenly, all bis in EMR3 are reserved, as shown in Figure 9. The EMR3 is programmed via he LM command and will reain he sored informaion unil i is programmed again or he device loses power. Reprogramming he EMR will no aler he conens of he memory array, provided i is performed correcly. EMR3 mus be loaded when all banks are idle and no burss are in progress, and he conroller mus wai he specifi ed ime MRD before iniiaing any subsequen operaion. Violaing eiher of hese requiremens could resul in unspecifi ed operaion. Augus 2 2 Microsemi Corporaion. All righs reserved. 3 Microsemi Corporaion (62) Rev. 2

14 Funcion Previous Cycle TABLE 3 TRUTH TABLE - DDR2 COMMANDS Noes, 5, and 6 apply o all CKE Curren Cycle CS# RAS# CAS# WE# BA2 BA BA A2 A A A9-A Noes LOAD MODE H H L L L L BA OP Code 2 REFRESH H H L L L H X X X X SELF-REFRESH Enry H L L L L H X X X X SELF-REFRESH Exi L H H X X X L H H H X X X X 7 Single bank precharge H H L L H L BA X L X 2 All banks PRECHARGE H H L L H L X X H X Bank acivae H H L L H H BA Row Address WRITE H H L L H L BA WRITE wih auo precharge H H L H L L BA READ H H L H L H BA READ wih auo precharge H H L H L H BA Column Address Column Address Column Address Column Address NO OPERATION H X L H H H X X X X Device DESELECT H X H X X X X X X X POWER-DOWN enry H L POWER-DOWN exi L H H X X X L H H H H X X X L H H H L H L H Column Address Column Address Column Address Column Address X X X X 4 X X X X 4 Noe:. All DDR2 SDRAM commands are defined by saes of CS#, RAS#, CAS#, WE#, and CKE a he rising edge of he clock. 2. Bank addresses (BA) BA BA2 deermine which bank is o be operaed upon. BA during a LM command selecs which mode regiser is programmed. 3. The power-down mode does no perform any REFRESH operaions. The duraion of power-down is herefore limied by he refresh requiremens oulined in he AC parameric secion. 4. The sae of ODT does no affec he saes described in his able. The ODT funcion is no available during self refresh. See On-Die Terminaion (ODT) for deails. 5. X means H or L (bu a defined logic level). 6. Self refresh exi is asynchronous. 2, 3 2, 3 2, 3 2, 3 Augus 2 2 Microsemi Corporaion. All righs reserved. 4 Microsemi Corporaion (62) Rev. 2

15 DESELECT The DESELECT funcion (CS# HIGH) prevens new commands from being execued by he DDR2 SDRAM. The DDR2 SDRAM is effecively deseleced. Operaions already in progress are no affeced. NO OPERATION (NOP) The NO OPERATION (NOP) command is used o insruc he seleced DDR2 SDRAM o perform a NOP (CS# is LOW; RAS#, CAS#, and WE are HIGH). This prevens unwaned commands from being regisered during idle or wai saes. Operaions already in progress are no affeced. FIGURE ACTIVE COMMAND CK# CK CKE CS# RAS# LOAD MODE (LM) The mode regisers are loaded via inpus BA2 BA, and A2 A. BA2 BA deermine which mode regiser will be programmed. See Mode Regiser (MR). The LM command can only be issued when all banks are idle, and a subsequen execue able command canno be issued unil MRD is me. BANK/ROW ACTIVATION ACTIVE COMMAND The ACTIVE command is used o open (or acivae) a row in a paricular bank for a subsequen access. The value on he BA2 BA inpus selecs he bank, and he address provided on inpus A2 A selecs he row. This row remains acive (or open) for accesses unil a PRECHARGE command is issued o ha bank. A PRECHARGE command mus be issued before opening a differen row in he same bank. ACTIVE OPERATION Before any READ or WRITE commands can be issued o a bank wihin he DDR2 SDRAM, a row in ha bank mus be opened (acivaed), even when addiive laency is used. This is accomplished via he ACTIVE command, which selecs boh he bank and he row o be acivaed. Afer a row is opened wih an ACTIVE command, a READ or WRITE command may be issued o ha row, subjec o he RCD specificaion. RCD (MIN) should be divided by he clock period and rounded up o he nex whole number o deermine he earlies clock edge afer he ACTIVE command on which a READ or WRITE command can be enered. The same procedure is used o conver oher specifi caion limis from ime unis o clock cycles. For example, a RCD (MIN) specifi caion of 2ns wih a 266 MHz clock (CK = 3.75ns) resuls in 5.3 clocks, rounded up o 6. A subsequen ACTIVE command o a differen row in he same bank can only be issued afer he previous acive row has been closed (precharged). The minimum ime inerval beween successive ACTIVE commands o he same bank is defined by RC A subsequen ACTIVE command o anoher bank can be issued while he fi rs bank is being accessed, which resuls in a reducion of oal row-access overhead. The minimum ime inerval beween successive ACTIVE commands o differen banks is defined by RRD CAS# WE# ADDRESS BANK ADDRESS Row Bank DON T CARE Augus 2 2 Microsemi Corporaion. All righs reserved. 5 Microsemi Corporaion (62) Rev. 2

16 READ COMMAND The READ command is used o iniiae a burs read access o an acive row. The value on he BA2 BA inpus selecs he bank, and he address provided on inpus A i (where i = A9) selecs he saring column locaion. The value on inpu A deermines wheher or no auo precharge is used. If auo precharge is seleced, he row being accessed will be precharged a he end of he READ burs; if auo precharge is no seleced, he row will remain open for subsequen accesses. FIGURE READ COMMAND CK# CK CKE CS# READ OPERATION READ burss are iniiaed wih a READ command. The saring column and bank addresses are provided wih he READ command and auo precharge is eiher enabled or disabled for ha burs access. If auo precharge is enabled, he row being accessed is auomaically precharged a he compleion of he burs. If auo precharge is disabled, he row will be lef open afer he compleion of he burs. During READ burss, he valid daa-ou elemen from he saring column address will be available READ laency (RL) clocks laer. RL is defi ned as he sum of AL and CL; RL = AL + CL. The value for AL and CL are programmable via he MR and EMR commands, respecively. Each subsequen daa-ou elemen will be valid nominally a he nex posiive or negaive clock edge (i.e., a he nex crossing of CK and CK#). DQS/DQS# is driven by he DDR2 SDRAM along wih oupu daa. The iniial LOW sae on DQS and HIGH sae on DQS# is known as he read preamble ( RPRE). The LOW sae on DQS and HIGH sae on DQS# coinciden wih he las daa-ou elemen is known as he read posamble (RPST). Upon compleion of a burs, assuming no oher commands have been iniiaed, he DQ will go High-Z. Daa from any READ burs may be concaenaed wih daa from a subsequen READ command o provide a coninuous flow of daa. The fi rs daa elemen from he new burs follows he las elemen of a compleed burs. The new READ command should be issued x cycles afer he firs READ command, where x equals BL / 2 cycles. RAS# CAS# WE# ADDRESS AUTO PRECHARGE BANK ADDRESS Col ENABLE A DISABLE Bank DON T CARE Augus 2 2 Microsemi Corporaion. All righs reserved. 6 Microsemi Corporaion (62) Rev. 2

17 WRITE COMMAND The WRITE command is used o iniiae a burs wrie access o an acive row. The value on he BA2 BA inpus selecs he bank, and he address provided on inpus A 9 selecs he saring column locaion. The value on inpu A deermines wheher or no auo precharge is used. If auo precharge is seleced, he row being accessed will be precharged a he end of he WRITE burs; if auo precharge is no seleced, he row will remain open for subsequen accesses. Inpu daa appearing on he DQ is wrien o he memory array subjec o he DM inpu logic level appearing coinciden wih he daa. If a given DM signal is regisered LOW, he corresponding daa will be wrien o memory; if he DM signal is regisered HIGH, he corresponding daa inpus will be ignored, and a WRITE will no be execued o ha bye/column locaion. DDR2 SDRAM does no allow inerruping or runcaing any WRITE burs using BL = 4 operaion. Once he BL = 4 WRITE command is regisered, i mus be allowed o complee he enire WRITE burs cycle. However, a WRITE (wih auo precharge disabled) using BL = 8 operaion migh be inerruped and runcaed ONLY by anoher WRITE burs as long as he inerrupion occurs on a 4-bi boundary, due o he 4n prefech archiecure of DDR2 SDRAM. WRITE burs BL = 8 operaions may no o be inerruped or runcaed wih any command excep anoher WRITE command. Daa for any WRITE burs may be followed by a subsequen READ command. The number of clock cycles required o mee WTR is eiher 2 or WTR/CK, whichever is greaer. Daa for any WRITE burs may be followed by a subsequen PRECHARGE command. WT sars a he end of he daa burs, regardless of he daa mask condiion. WRITE OPERATION WRITE burss are iniiaed wih a WRITE command, as shown in Figure 2. DDR2 SDRAM uses WL equal o RL minus one clock cycle [WL = RL - CK = AL + (CL - CK)]. The saring column and bank addresses are provided wih he WRITE command, and auo precharge is eiher enabled or disabled for ha access. If auo precharge is enabled, he row being accessed is precharged a he compleion of he burs. During WRITE burss, he firs valid daa-in elemen will be regisered on he fi rs rising edge of DQS following he WRITE command, and subsequen daa elemens will be regisered on successive edges of DQS. The LOW sae on DQS beween he WRITE command and he fi rs rising edge is known as he wrie preamble; he LOW sae on DQS following he las daa-in elemen is known as he wrie posamble. The ime beween he WRITE command and he fi rs rising DQS edge is WL ± DQSS. Subsequen DQS posiive rising edges are imed, relaive o he associaed clock edge, as ± DQSS. DQSS is specifi ed wih a relaively wide range (25 percen of one clock cycle). All of he WRITE diagrams show he nominal case, and where he wo exreme cases (DQSS [MIN] and DQSS [MAX]) migh no be inuiive, hey have also been included. Upon compleion of a burs, assuming no oher commands have been iniiaed, he DQ will remain High-Z and any addiional inpu daa will be ignored. Daa for any WRITE burs may be concaenaed wih a subsequen WRITE command o provide coninuous flow of inpu daa. The firs daa elemen from he new burs is applied afer he las elemen of a compleed burs. The new WRITE command should be issued x cycles afer he fi rs WRITE command, where x equals BL/2. DDR2 SDRAM suppors concurren auo precharge opions, as shown in Table 4. Augus 2 2 Microsemi Corporaion. All righs reserved. 7 Microsemi Corporaion (62) Rev. 2

18 FIGURE 2 WRITE COMMAND CK# CK CKE HIGH CS# RAS# CAS# WE# ADDRESS C A A EN AP DIS AP BANK ADDRESS BA Noe: CA = column address; BA = bank address; EN AP = enable auo precharge; and DIS AP = disable auo precharge. DON T CARE TABLE 4 WRITE USING COURRENT AUTO PRECHARGE From Command (Bank n) To Command (Bank m) Minimum Delay (Wih Concurren Auo Precharge) Unis WRITE wih Auo Precharge READ OR READ w/ap (CL-) + (BL/2) + WTR CK WRITE or WRITE w/ap (BL/2) CK PRECHARGE or ACTIVE CK Augus 2 2 Microsemi Corporaion. All righs reserved. 8 Microsemi Corporaion (62) Rev. 2

19 PRECHARGE COMMAND The PRECHARGE command, illusraed in Figure 3, is used o deacivae he open row in a paricular bank or he open row in all banks. The bank(s) will be available for a subsequen row acivaion a specifi ed ime (RP ) afer he PRECHARGE command is issued, excep in he case of concurren auo precharge, where a READ or WRITE command o a differen bank is allowed as long as i does no inerrup he daa ransfer in he curren bank and does no violae any oher iming parameers. Once a bank has been precharged, i is in he idle sae and mus be acivaed prior o any READ or WRITE commands being issued o ha bank. A PRECHARGE command is allowed if here is no open row in ha bank (idle sae) or if he previously open row is already in he process of precharging. However, he precharge period will be deermined by he las PRECHARGE command issued o he bank. PRECHARGE OPERATION Inpu A deermines wheher one or all banks are o be precharged, and in he case where only one bank is o be precharged, inpus BA2 BA selec he bank. Oherwise BA2 BA are reaed as Don Care. When all banks are o be precharged, inpus BA2 BA are reaed as Don Care. Once a bank has been precharged, i is in he idle sae and mus be acivaed prior o any READ or WRITE commands being issued o ha bank. RPA iming applies when he PRECHARGE (ALL) command is issued, regardless of he number of banks already open or closed. If a single-bank PRECHARGE command is issued, RP iming applies. RPA (MIN) applies o all 8-bank DDR2 devices. FIGURE 3 PRECHARGE COMMAND CK# CK CKE CS# RAS# CAS# WE# ADDRESS A BA - BA2 HIGH ALL BANKS ONE BANK BA DON T CARE Noe: BA = bank address (if A is LOW; oherwise "Don' Care"). SELF REFRESH COMMAND The SELF REFRESH command can be used o reain daa in he DDR2 SDRAM, even if he res of he sysem is powered down. When in he self refresh mode, he DDR2 SDRAM reains daa wihou exernal clocking. All power supply inpus (including VREF) mus be mainained a valid levels upon enry/exi and during SELF REFRESH operaion. The SELF REFRESH command is iniiaed like a REFRESH command excep CKE is LOW. The DLL is auomaically disabled upon enering self refresh and is auomaically enabled upon exiing self refresh (2 clock cycles mus hen occur before a READ command can be issued). The differenial clock should remain sable and mee CKE specifi caions a leas x CK afer enering self refresh mode. All command and address inpu signals excep CKE are Don Care during self refresh. The procedure for exiing self refresh requires a sequence of commands. Firs, he differenial clock mus be sable and mee CK specifi caions a leas x CK prior o CKE going back HIGH. Once CKE is HIGH (CLE(MIN) has been saisfi ed wih four clock regisraions), he DDR2 SDRAM mus have NOP or DESELECT commands issued for XSNR because ime is required for he compleion of any inernal refresh in progress. A simple algorihm for meeing boh refresh and DLL requiremens is o apply NOP or DESELECT commands for 2 clock cycles before applying any oher command. Noe: Self refresh no available a miliary emperaure.. Augus 2 2 Microsemi Corporaion. All righs reserved. 9 Microsemi Corporaion (62) Rev. 2

20 DC OPERATING CONDITIONS All volages referenced o Parameer Symbol Min Typical Max Uni Noes Supply volage V I/O Reference volage VREF.49 x Q.5 x Q.5 x Q V 2 I/O Terminaion volage VTT VREF-.4 VREF VREF +.4 V 3 Noes:. and Q are ied on he device. 2. VREF is expeced o equal Q/2 of he ransmiing device and o rack variaions in he DC level of he same. Peak-o-peak noise on VREF may no exceed ± percen of he DC value. Peak-o-peak AC noise on VREF may no exceed ±2 percen of VREF. This measuremen is o be aken a he neares VREF bypass capacior. 3. VTT is no applied direcly o he device. VTT is a sysem supply for signal erminaion resisors, is expeced o be se equal o VREF and mus rack variaions in he DC level of VREF. ABSOLUTE MAXIMUM RATINGS Symbol Parameer MIN MAX Uni / Q Volage on pin relaive o V VIN, VOUT Volage on any pin relaive o V TSTG Sorage emperaure C IL Inpu leakage curren; Any inpu V<VIN<; Oher pins no under es = V -2 2 μa IOZ Oupu leakage curren; V<VOUT<; DQs and ODT are disabled -5 5 μa IVREF VREF leakage curren; VREF = Valid VREF level -8 8 μa INPUT/OUTPUT CAPACITAE TA = 25 C, f = MHz, =.8V Parameer Symbol Max Uni Inpu capaciance (A - A3, BA - BA2,CS#, RAS#,CAS#,WE#, CKE, ODT) CIN TBD pf Inpu capaciance CK, CK# CIN2 TBD pf Inpu capaciance DM, DQS, DQS# CIN3 TBD pf Inpu capaciance DQ - 7 COUT TBD pf Augus 2 2 Microsemi Corporaion. All righs reserved. 2 Microsemi Corporaion (62) Rev. 2

21 BGA THERMAL RESISTAE Descripion Symbol Typical Unis Noes Juncion o Ambien (No Airflow) Thea JA 8 C/W Juncion o Ball Thea JB 8 C/W Juncion o Case (Top) Thea JC 9 C/W INPUT DC LOGIC LEVEL All volages referenced o Parameer Symbol Min Max Uni Inpu High (Logic ) Volage VIH(DC) VREF V Inpu Low (Logic ) Volage VIL(DC) -.3 VREF -.25 V INPUT AC LOGIC LEVEL All volages referenced o Parameer Symbol Min Max Uni AC Inpu High (Logic ) Volage DDR2-4 & DDR2-533 VIH(AC) VREF +.25 V AC Inpu High (Logic ) Volage DDR2-667 VIH(AC) VREF +.2 V AC Inpu Low (Logic ) Volage DDR2-4 & DDR2-533 VIL(AC) VREF -.25 V AC Inpu Low (Logic ) Volage DDR2-667 VIL(AC) VREF -.2 V ODT DC ELECTRICAL CHARACTERISTICS All volages referenced o Parameer Symbol Min Nom Max Uni Noes RTT effecive impedance value for 75Ω seing EMR (A6, A2) =, RTT(EFF) Ω RTT effecive impedance value for 5Ω seing EMR (A6, A2) =, RTT2(EFF) Ω RTT effecive impedance value for 5Ω seing EMR (A6, A2) =, RTT3(EFF) Ω Deviaion of VM wih respec o Q/2 VM -6 6 % 2 Noe:. RTT(EFF) and RTT2(EFF) are deermined by separaely applying VIH(AC) and VIL (AC) o he ball being esed, and hen measuring curren, I(VIH(AC)), and I(VIL(AC)), respecively. RTT(EFF) = VIH(AC) - VIL(AC) I(VIH(AC)) - I(VIL(AC)) 2. Measure volage (VM) a esed ball wih no load VM = (2 x VM - ) x Augus 2 2 Microsemi Corporaion. All righs reserved. 2 Microsemi Corporaion (62) Rev. 2

22 DDR2 ICC SPECIFICATIONS AND CONDITIONS -55 C TA 25 C Symbol Proposed Condiions 667 CL6 533 CL5 4 CL4 Unis ICC Operaing one bank acive-precharge curren; CK = CK(ICC), RC = RC(ICC), RAS = RASmin(ICC); CKE is HIGH, CS# is HIGH beween valid commands; Address bus inpus are SWITCHING; Daa bus inpus are SWITCHING ma ICC ICC2P ICC2Q ICC2N ICC3P ICC3N ICC4W ICC4R ICC5 ICC6 ICC7 Operaing one bank acive-read-precharge curren; IOUT = ma; BL = 4, CL = CL(ICC), AL = ; CK = CK(ICC), RC = RC (ICC), RAS = RASmin(ICC), RCD = RCD(ICC); CKE is HIGH, CS# is HIGH beween valid commands; Address bus inpus are SWITCHING; Daa paern is same as ICC4W Precharge power-down curren; All banks idle; CK = CK(ICC); CKE is LOW; Oher conrol and address bus inpus are STABLE; Daa bus inpus are FLOATING Precharge quie sandby curren; All banks idle; CK = CK(ICC); CKE is HIGH, CS# is HIGH; Oher conrol and address bus inpus are STABLE; Daa bus inpus are FLOATING Precharge sandby curren; All banks idle; CK = CK(ICC); CKE is HIGH, CS# is HIGH; Oher conrol and address bus inpus are SWITCHING; Daa bus inpus are SWITCHING Acive power-down curren; All banks open; CK = CK(ICC); CKE is LOW; Oher conrol and address bus inpus are STABLE; Daa bus inpus are FLOATING Acive sandby curren; All banks open; CK = CK(ICC), RAS = RASMAX(ICC), RP = RP(ICC); CKE is HIGH, CS# is HIGH beween valid commands; Oher conrol and address bus inpus are SWITCHING; Daa bus inpus are SWITCHING Operaing burs wrie curren; All banks open, Coninuous burs wries; BL = 4, CL = CL(ICC), AL = ; CK = CK(ICC), RAS = RASMAX(ICC), RP = RP(ICC); CKE is HIGH, CS# is HIGH beween valid commands; Address bus inpus are SWITCHING; Daa bus inpus are SWITCHING Operaing burs read curren; All banks open, Coninuous burs reads, IOUT = ma; BL = 4, CL = CL(ICC), AL = ; CK = CK(ICC), RAS = RASMAX(ICC), RP = RP(ICC); CKE is HIGH, CS# is HIGH beween valid commands; Address bus inpus are SWITCHING Burs auo refresh curren; CK = CK(ICC); Refresh command a every RFC(ICC) inerval; CKE is HIGH, CS# is HIGH beween valid commands; Oher conrol and address bus inpus are SWITCHING; Daa bus inpus are SWITCHING Self refresh curren; CK and CK# a V; CKE.2V; Oher conrol and address bus inpus are FLOATING; Daa bus inpus are FLOATING Operaing bank inerleave read curren; All bank inerleaving reads, IOUT = ma; BL = 4, CL = CL(ICC), AL = RCD(ICC)-*CK(ICC); CK = CK(ICC), RC = RC(ICC), RRD = RRD(ICC), RCD = *CK(ICC); CKE is HIGH, CS# is HIGH beween valid commands; Address bus inpus are STABLE during DESELECTs; Daa bus inpus are swiching ma ma ma ma Fas PDN Exi MRS(2) = ma Slow PDN Exi MRS(2) = ma ma, ma, ma,2,4, ma Normal ma,58,42,42 ma Augus 2 2 Microsemi Corporaion. All righs reserved. 22 Microsemi Corporaion (62) Rev. 2