Register Allocation. k register. IR Register Allocation. IR Instruction Scheduling

Transcription

1 Register Alloation Register Alloation Part of the ompiler s ak en IR Instrution Seletion m register IR Register Alloation k register IR Instrution Sheuling Mahine oe Critial properties Proue orret oe that uses k (or fewer) registers Minimize ae loas an stores Minimize spae use to hol spille values Operate effiiently O(n), O(n log 2 n), maye O(n 2 ), ut not O(2 n ) Errors 2 1

2 Register Alloation Motivation Registers muh faster than memory Limite numer of physial registers Keep values in registers as long as possile Minimize numer of loa / store statements exeute Register alloation & assignment For simpliity Assume infinite numer of virtual registers Deie whih values to keep in finite # of virtual registers Assign virtual registers to physial registers 3 Register Alloation The Task At eah point in the oe, pik the values to keep in registers Insert oe to move values etween registers & memory No transformations (leave that to sheuling) Minimize inserte oe Use oth ynami & stati measures Make goo use of any extra registers Alloation versus assignment Alloation is eiing whih values to keep in registers Assignment is hoosing speifi registers for values This istintion is often lost in the literature The ompiler must perform oth alloation & assignment 4 2

3 Register Alloation Approahes Loal alloation (within asi loks) Top-own Assign registers y frequeny Bottom-up Spill registers y reuse istane Gloal alloation (aross asi loks) Top-own Color interferene graph Bottom-up Split live ranges 5 Loal Register Alloation What s loal? (as oppose to gloal ) A loal transformation operates on asi loks Many optimizations are one loally Does loal alloation solve the prolem? It proues eent register use insie a lok Ineffiienies an arise at ounaries etween loks How many passes an the alloator make? This is an off-line prolem As many passes as it takes Memory-to-memory vs. register-to-register moel Coe shape an safety issues 6 3

4 Register Alloation Can we o this optimally? (on real oe?) Loal Alloation Simplifie ases O(n) Real ases NP-Complete Loal Assignment Single size, no spilling O(n) Two sizes NP-Complete Gloal Alloation Gloal Assignment NP-Complete for 1 register NP-Complete NP-Complete for k registers (most su-prolems are NPC, too) Real ompilers fae real prolems 7 Oservations Alloator may nee to reserve registers to ensure feasiility Must e ale to ompute aresses Requires some minimal (feasile) set of registers, F F epens on target arhiteture Use these registers only for spilling (set them asie, i.e., not availale for register assignment) What if k F < values < k? The alloator an either Chek for this situation Notation: k is the numer of registers on the target mahine Aept the fat that the tehnique is an approximation 8 4

5 Oservations A value is live etween its efinition an its uses Fin efinitions (x ) an uses (y x...) From efinition to last use is its live range How oes a seon efinition affet this? Can represent live range as an interval [i,j] (in lok) live on exit Let MAXLIVE e the maximum, over eah instrution i in the lok, of the numer of values (pseuo-registers) live at i. If MAXLIVE k, alloation shoul e easy If MAXLIVE k, no nee to reserve F registers for spilling If MAXLIVE > k, some values must e spille to memory Fining live ranges is harer in the gloal ase 9 ILOC Instrution Set Operation Meaning Lateny loa r1 r2 MEM(r1) r2 2 store r1 r2 r1 MEM(r2) 2 loai r1 r1 1 a r1, r2 r3 r1 + r2 r3 1 su r1, r2 r3 r1 r2 r3 1 mult r1, r2 r3 r1 x r2 r3 1 lshift r1, r2 r3 r1 << r2 r3 1 rshift r1, r2 r3 r1 >> r2 r3 1 output print out MEM() 1 Assume a register-to-register memory moel, with 1 lass of registers. Latenies are important for instrution sheuling, not register alloation an assignment 10 5

6 ILOC Example Sample oe sequene loai 1028 r1 // r loa r1 r2 // r2 MEM(r1) == y mult r1, r2 r3 // r y loai 5 r4 // r4 5 su r4, r2 r5 // r5 5 y loai 8 r6 // r6 8 mult r5, r6 r7 // r7 8 (5 y) su r7, r3 r8 // r5 8 (5 y) (1028 y) store r8 r1 // MEM(r1) 8 (5 y) (1028 y) 11 ILOC Example Live Ranges Live range for r1 1 loai 1028 r1 // r1 2 loa r1 r2 // r1 r2 3 mult r1, r2 r3 // r1 r2 r3 4 loai 5 r4 // r1 r2 r3 r4 5 su r4, r2 r5 // r1 r3 r5 6 loai 8 r6 // r1 r3 r5 r6 7 mult r5, r6 r7 // r1 r3 r7 8 su r7, r3 r8 // r1 r8 9 store r8 r1 // NOTE: live sets on exit of eah instrution 12 6

7 ILOC Example Live Ranges Live range for r2 1 loai 1028 r1 // r1 2 loa r1 r2 // r1 r2 3 mult r1, r2 r3 // r1 r2 r3 4 loai 5 r4 // r1 r2 r3 r4 5 su r4, r2 r5 // r1 r3 r5 6 loai 8 r6 // r1 r3 r5 r6 7 mult r5, r6 r7 // r1 r3 r7 8 su r7, r3 r8 // r1 r8 9 store r8 r1 // NOTE: live sets on exit of eah instrution 13 ILOC Example Live Ranges Live range for r3 1 loai 1028 r1 // r1 2 loa r1 r2 // r1 r2 3 mult r1, r2 r3 // r1 r2 r3 4 loai 5 r4 // r1 r2 r3 r4 5 su r4, r2 r5 // r1 r3 r5 6 loai 8 r6 // r1 r3 r5 r6 7 mult r5, r6 r7 // r1 r3 r7 8 su r7, r3 r8 // r1 r8 9 store r8 r1 // NOTE: live sets on exit of eah instrution 14 7

8 Top-own Versus Bottom-up Alloation Top-own alloator Work from external notion of what is important Assign registers in priority orer Register assignment remains fixe for entire asi lok Save some registers for the values relegate to memory (feasile set F) Bottom-up alloator Work from etaile knowlege aout prolem instane Inorporate knowlege of partial solution at eah step Register assignment may hange aross asi lok Save some registers for the values relegate to memory (feasile set F) 15 Bottom-up Alloator The iea: Fous on replaement rather than alloation Keep values use soon in registers Algorithm: Start with empty register set Loa on eman When no register is availale, free one Replaement: Spill the value whose next use is farthest in the future Prefer lean value to irty value Soun familiar? Think ahe line / page replaement

9 Spill oe A virtual register is spille y using only registers from the feasile set (F), not the alloate set (k-f) How to insert spill oe, with F = {f1, f2, }? 2 For the efinition of the spille value (assignment of the value to the virtual register), use a feasile register as the target register an then use an aitional register to loa its aress in memory, an perform the store: a r1, r2 r3 For the use of the spille value, loa value from memory into a feasile register: a r1, r2 r3 a r1, r2 f1 f2 // value lives at memory store f1 f2 f1 // value lives at memory loa f1 f1 a f1, r2 r3 How many feasile registers o we nee for an a instrution? 17 ILOC Example Bottom-up Alloation Bottom up (3 physial registers: ra, r, r) register alloation an assignment(on exit) soure oe life ranges ra r r 1 loai 1028 r1 // r1 r1 2 loa r1 r2 // r1 r2 r1 r2 3 mult r1, r2 r3 // r1 r2 r3 r1 r2 r3 4 loai 5 r4 // r1 r2 r3 r4 r4 r2 r3 5 su r4, r2 r5 // r1 r5 r3 r4 r5 r3 6 loai 8 r6 // r1 r5 r3 r6 r6 r5 r3 7 mult r5, r6 r7 // r1 r7 r3 r6 r7 r3 8 su r7, r3 r8 // r1 r8 r6 r8 r3 9 store r8 r1 // r1 r8 r3 Part of r1 live range spille Note: this is only one possile alloation an assignment! 18 9

10 ILOC Example Bottom-up Assignment Bottom up (3 physial registers: ra, r, r) register alloation an assignment(on exit) soure oe ra r r 1 loai 1028 r1 r1 2 loa r1 r2 r1 r2 3 mult r1, r2 r3 r1 r2 r3 4 loai 5 r4 r4 r2 r3 5 su r4, r2 r5 r4 r5 r3 6 loai 8 r6 r6 r5 r3 7 mult r5, r6 r7 r6 r7 r3 8 su r7, r3 r8 r6 r8 r3 9 store r8 r1 r1 r8 r3 Let s generate oe now! 19 ILOC Example Bottom-up Assignment Bottom up (3 physial registers: ra, r, r) register alloation an assignment(on exit) soure oe ra r r write 1 loai 1028 ra r1 2 loa r1 r2 r1 r2 3 mult r1, r2 r3 r1 r2 r3 4 loai 5 r4 r4 r2 r3 5 su r4, r2 r5 r4 r5 r3 6 loai 8 r6 r6 r5 r3 7 mult r5, r6 r7 r6 r7 r3 8 su r7, r3 r8 r6 r8 r3 9 store r8 r1 r1 r8 r3 For written registers, use urrent register assignment 20 10

11 ILOC Example Bottom-up Assignment Bottom up (3 physial registers: ra, r, r) register alloation an assignment(on exit) soure oe ra r r 1 loai 1028 ra rea r1 2 loa ra r2 r1 r2 3 mult r1, r2 r3 r1 r2 r3 4 loai 5 r4 r4 r2 r3 5 su r4, r2 r5 r4 r5 r3 6 loai 8 r6 r6 r5 r3 7 mult r5, r6 r7 r6 r7 r3 8 su r7, r3 r8 r6 r8 r3 9 store r8 r1 r1 r8 r3 For rea registers, use previous register assignment 21 ILOC Example Bottom-up Assignment Bottom up (3 physial registers: ra, r, r) register alloation an assignment(on exit) soure oe ra r r 1 loai 1028 ra write r1 2 loa ra r r1 r2 3 mult r1, r2 r3 r1 r2 r3 4 loai 5 r4 r4 r2 r3 5 su r4, r2 r5 r4 r5 r3 6 loai 8 r6 r6 r5 r3 7 mult r5, r6 r7 r6 r7 r3 8 su r7, r3 r8 r6 r8 r3 9 store r8 r1 r1 r8 r

12 ILOC Example Bottom-up Assignment Bottom up (3 physial registers: ra, r, r) register alloation an assignment(on exit) soure oe ra r r 1 loai 1028 ra r1 2 loa ra r r1 r2 3 mult ra, r r r1 r2 r3 store* ra 10 spill oe r1 r2 r3 4 loai 5 r4 *NOT ILOC* r4 r2 r3 5 su r4, r2 r5 r4 r5 r3 6 loai 8 r6 r6 r5 r3 7 mult r5, r6 r7 r6 r7 r3 8 su r7, r3 r8 r6 r8 r3 9 store r8 r1 r1 r8 r3 Insert spill oe 23 ILOC Example Bottom-up Assignment Bottom up (3 physial registers: ra, r, r) register alloation an assignment(on exit) soure oe ra r r 1 loai 1028 ra r1 2 loa ra r r1 r2 3 mult ra, r r r1 r2 r3 store ra 10 spill oe r1 r2 r3 4 loai 5 ra r4 r2 r3 5 su ra, r r r4 r5 r3 6 loai 8 ra r6 r5 r3 7 mult r, ra r r6 r7 r3 8 su r, r r r6 r8 r3 9 store r8 r1 r1 r8 r

13 ILOC Example Bottom-up Assignment Bottom up (3 physial registers: ra, r, r) register alloation an assignment(on exit) soure oe ra r r 1 loai 1028 ra r1 2 loa ra r r1 r2 3 mult ra, r r r1 r2 r3 store ra 10 spill oe r1 r2 r3 4 loai 5 ra r4 r2 r3 5 su ra, r r r4 r5 r3 6 loai 8 ra r6 r5 r3 7 mult r, ra r r6 r7 r3 8 su r, r r r6 r8 r3 loa* 10 ra spill oe r1 r8 r3 9 store r8 r1 *NOT ILOC* r1 r8 r3 Insert spill oe 25 ILOC Example Bottom-up Assignment Bottom up (3 physial registers: ra, r, r) register alloation an assignment(on exit) soure oe ra r r 1 loai 1028 ra r1 2 loa ra r r1 r2 3 mult ra, r r r1 r2 r3 store* ra 10 spill oe r1 r2 r3 4 loai 5 ra r4 r2 r3 5 su ra, r r r4 r5 r3 6 loai 8 ra r6 r5 r3 7 mult r, ra r r6 r7 r3 8 su r, r r r6 r8 r3 loa* 10 ra spill oe r1 r8 r3 9 store r ra r1 r8 r3 Done 26 13

14 Top-own Alloator The iea: Keep usiest values in a register Use the feasile (reserve) set, F, for the rest Algorithm: Rank values y numer of ourrenes Alloate first k F values to registers Rewrite oe to reflet these hoies SPILL: Move values with no register into memory (a LOADs & STOREs) 27 ILOC Example Top-own Alloation Top own (3 physial registers: ra, r, r) Note that this 1 loai 1028 r1 // r1 assumes that an extra register is 2 loa r1 r2 // r1 r2 not neee for 3 mult r1, r2 r3 // r1 r2 r3 save/restore 4 loai 5 r4 // r1 r2 r3 r4 5 su r4, r2 r5 // r1 r3 r5 6 loai 8 r6 // r1 r3 r5 r6 7 mult r5, r6 r7 // r1 r3 r7 8 su r7, r3 r8 // r1 r8 9 store r8 r1 // Consier -# of ourrenes of virtual register (most important) -Fewer etter spill aniate -r1=3, r2=2, r3=2, r4=2, r5=2, r6=2, r7=2, r8=2 -Length of live range (tie reaker) -Longer etter spill aniate -r1=8, r2=3, r3=5, r4=2, r5=2, r6=1, r7=1, r8=

15 ILOC Example Top-own Assignment Top own (3 physial registers: ra, r, r) Note that this assumes that an 1 loai 1028 ra // r1 extra register is 2 loa ra r // r1 r2 not neee for 3 mult ra, r r // r1 r2 r3 save/restore store* r 10 // spill oe 4 loai 5 r // r1 r2 r3 r4 5 su r, r r // r1 r3 r5 6 loai 8 r // r1 r3 r5 r6 7 mult r, r r // r1 r3 r7 loa* 10 r // spill oe 8 su r, r r // r1 r8 9 store r ra // Insert spill oe for every ourrene of spille virtual register in asi lok 29 Register Alloation Approahes Loal alloation (within asi loks) Top-own Assign registers y frequeny Bottom-up Spill registers y reuse istane Gloal alloation (aross asi loks) Top-own Color interferene graph Bottom-up Split live ranges 30 15

16 Gloal Register Alloation Top Down Register oloring Maps register alloation to graph oloring Major steps 1. Gloal ata-flow analysis to fin live ranges 2. Buil an olor interferene graph 3. If unale to fin oloring, spill registers & repeat 31 Gloal Live Ranges Definition All efinitions whih reah a use plus all uses reahe y these efinitions a= = =a = = A single virtual register may omprise several live ranges a= =a a= =a = Live ranges elineate when variales nee to e store in the same physial register to avoi extra oe = = = = 32 16

17 Interferene Using live ranges, an interferene graph is onstrute where Verties represent live ranges Eges represent interferenes etween live ranges Both ranges are live at same point Cannot oupy the same register Coloring represents register assignment One olor per register Using a graph oloring astration sutly hanges the prolem Justifie y nee to separate optimization an alloation 33 Builing the Interferene Graph Algorithm At eah point p in the program A ege (x,y) for all pairs of live ranges x, y live at p Example a= =a = = a a= = =a = a 34 17

18 Coloring Graph oloring Given graph, fin assignment of olors to eah noe Suh that no neighors have the same olor Determining whether a graph has a k-oloring Is NP-har for k > 2 Register oloring Fin a legal oloring given k olors Where k is the numer of availale registers 35 Graph Coloring Through Simplifiation Coloring algorithm [Chaitin et al., 1981] 1. Repeately remove noes with egree < k from graph Push noes onto stak 2. If every remaining noe is egree >= k Spill noe with lowest spill ost Remove noe from graph 3. Reassemle graph with noes poppe from stak As eah noe is ae to graph Choose a olor iffering from its neighors 36 18

19 Graph Coloring Example Given interferene graph an 3 registers Simplify graph y removing noes with < 3 neighors Push noes onto stak a e e e e e Reassemle graph y popping noes from stak Assigning olors not use y neighors a e e e e e 37 Graph Coloring Given interferene graph an 2 registers Simplify graph y removing noes with < 2 neighors No suh noe, must spill noe with lowest spill ost Remaining noes an then e simplifie & olore spille a Can we o etter? Yes! 38 19

20 Optimisti Graph Coloring Optimisti oloring algorithm [Briggs et al., 1989] Remove noes with egree < k from graph (pop onto stak) If every noe has egree > k Remove noe with lowest spill ost (pop onto stak) Reassemle graph with noes poppe from stak Spill noe if it annot e olore Optimisti oloring efers spilling eision Helps if neighors of noe Are the same olor Have alreay een spille 39 Optimisti Graph Coloring Given interferene graph an 2 registers Simplify graph y removing noes with < 2 neighors No suh noe, remove noe with lowest spill ost Continue graph simplifiation a Reassemle graph y popping noes from stak Assigning olors not use y neighors a 40 20

21 Spill Coe Inserte when too few registers to hol all live ranges Insert loa efore use Insert store after efinition Effets Breaks live range into many small live ranges Reues hane of interferene Expensive Introues loa / store instrutions For eah use / ef instrution in live range 41 Spill Cost Nee to eie whih live range to spill if neee Two metris to onsier Cost of spill Cost of loa / store instrutions inserte Derease in interferene Reue nee for more spills 42 21

22 Spill Cost Possile ost funtions Possile ost estimate heuristis Cost / egree [Chaitin et al., 1981] Cost / ( egree * egree ) Et Assumes 10 loop iterations 43 Alloation with Spilling One approah Apply ifferent ost estimate heuristis Pik est result Assumptions Builing interferene graph is highest expense Spill ost estimates an e alulate inexpensively Reuing spill oe y reognizing speial ases Value moifie (irty) Store register value to memory, reloa for use Rea-only value (lean) Reloa from memory for use Constant value (rematerializale) Reompute value (no nee for memory loa! ) 44 22

23 Gloal Register Alloation Bottom Up Live range splitting Insert opies to split up live ranges Hopefully reues nee for spilling Also ontrols spill oe plaement Spill oe generate at opies Examples a = a = a = a = a = a 45 Gloal Register Alloation Bottom Up Coalesing (susumption) Alloate soure an estination of opy to same register To eliminate register-to-register opies Comines live ranges Can reverse unneessary splits Examples a = r1 = r1 = = a r1 = r1 = = r1 = r

24 Live Range Splitting Approah [Chow & Hennessy 1990] 1. Loally alloate registers for eah asi lok 2. Prioritize live ranges y estimate spill ost 3. Alloate registers to live ranges 4. Split live range if no olors availale Example interferene a a a a a a spille a spille 47 Register Alloation Examples Assuming only 1 register availale, must spill p 48 24

25 Comining Instrution Sheuling & Register Alloation Alloation efore sheuling Register assignment introues epenenes Anti & output epenenes Reues freeom of instrution sheuling Example 49 Comining Instrution Sheuling & Register Alloation Sheuling efore alloation Lengthens live range of virtual registers Inreases register pressure May ause spills Still nee to sheule spill oe after alloation Example 50 25

26 Sheuling an Alloation Are Interepenent Confliting goals for sheuling & alloation Some possile solutions Assigning registers First fit Lowest availale register numer Reues total numer of registers use Roun roin Cyle through all registers Reues memory-relate epenenes 51 Sheuling an Alloation Are Interepenent More possile solutions Change orering Postpass alloate then sheule Prepass sheule then alloate Multipass sheule, alloate, sheule Integrate prepass sheuling Sheule instrutions first as preparation Bias sheule to reue loal register pressure Alloate registers after sheuling 52 26