An Area/Delay Efficient Dual-Modular Flip-Flop with Higher SEU/SET Immunity

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1 340 PAPER Speial Setion on Ciruits and Design Tehniques for Advaned Large Sale Integration An Area/Delay Effiient Dual-Modular Flip-Flop with Higher SEU/SET Immunity Jun FURUTA a), Nonmember, Kazutoshi KOBAYASHI, Member, and Hidetoshi ONODERA, Fellow SUMMARY Aording to the proess saling, semiondutor devies are beoming more sensitive to soft errors sine amount of ritial harges are dereasing. In this paper, we propose an area/delay effiient dual modular flip-flop, whih is tolerant to SEU (Single Event Upset) and SET (Single Event Transient). It is based on a BISER (Built-in Soft Error Resiliene). The original BISER FF ahieves small area but it is vulnerable to an SET pulse on C-elements. The proposed dual modular FF doubles C-elements and weak keepers between master and slave lathes, whih enhanes SET immunity onsiderably with paying small area-delay produt than the onventional delayed TMR FFs. key words: TMR, built-in soft error, SEU, SET 1. Introdution Proess saling makes LSIs less reliable to temporal and permanent failures. Temporal failures flip a stored value on SRAMs or flip flops. High-energy neutron is one of main soures of temporal failures, whih is alled a soft error. Soft errors are lassified into Single Event Upset (SEU) and Single Event Transient (SET). SEU is aused by a partile hit on sequential elements, and SET is aused by a partile hit on ombinational iruits. One of the solutions to remove soft errors is using dual interloked storage ell lath (DICE lath) [1]. Sine DICE lath have four storage nodes, it is very strong to SEU. However, it annot protet errors from SET. Thus its soft-error tolerane is just 10 times stronger than ordinal FFs. To remove SET and mitigate more soft errors, redundant iruits are usually used. TMR (Triple modular redundany) [2] is an ultimate solution for soft errors, in whih all iruit elements are tripled and unmathed results are resolved by majority voting. It is very robust to soft errors sine it does not fail until two modules fail at the same time, but its area penalty is relatively huge. In this paper, we propose an area and delay effiient dual modular flip-flop, whih is tolerant to SEU and SET. The proposed dual modular FF is based on the flip-flop with C-elements and weak keepers so alled a BISER (Built-in Soft Error Resiliene) [3]. The original BISER FF ahieves small area but it is vulnerable to an SET pulse Manusript reeived July 10, Manusript revised Otober 1, The authors are with the Department of Communiations and Computer Engineering, Kyoto University, Kyoto-shi, Japan. The author is with the Graduate Shool of Siene and Tehnology, Kyoto Institute of Tehnology, Kyoto-shi, Japan. a) furuta@vlsi.kuee.kyoto-u.a.jp DOI: /transele.E93.C.340 on C-elements. The proposed dual modular FF doubles C-elements and weak keepers between master and slave lathes, whih enhanes SET immunity onsiderably with paying very small area overhead. The remainder of this paper is organized as follows. In Set. 2, we introdue onventional multiple modular flip flops and detailed struture of the proposed dual modular FFs. Setion 3 desribes how to estimate soft error rates of the flip flops by using iruit-level simulations. Setion 4 examines area and delay penalties of the proposed and onventional redundant FFs for error resiliene. Setion 5 summarizes this paper. 2. Soft Error Tolerant Flip Flops 2.1 Dual Interloked Storage Cell Lath Figure 1 shows dual interloked storage ell lath using transmission gate, so alled DICE lath. It has four storage nodes. Even if one storage node is flipped by SEU, other storage nodes keep orret values. However DICE lath an not keep orret value when two storage nodes are flipped by a partile hit, whih situation is alled Multi Cell Upset (MCU). While MCU may be happened to other redundant FFs. DICE lath has no tolerane to SET. Thus its tolerane to soft error is just 10 times better than ordinal nonredundant FFs. 2.2 Conventional Multiple-Modular FFs Figure 2 shows a onventional TMR iruit (TMR onv ). The voter resolves stored values at lathes. Voters must be tripled to avoid failure due to SET pulses from a voter itself. Fig. 1 Dual interloked storage ell lath [1]. Copyright 2010 The Institute of Eletronis, Information and Communiation Engineers

2 FURUTA et al.: AN AREA/DELAY EFFICIENT DUAL-MODULAR FLIP-FLOP WITH HIGHER SEU/SET IMMUNITY 341 Fig. 5 A proposed DMR FF alled Double-Delayed DMR FF. Fig. 2 Conventional TMR flip flop tolerant to temporal errors from ombinational iruits and FFs (TMR onv )[2]. Fig. 6 Another proposed DMR FF alled Enhaned delayed DMR FF. Fig. 3 Delayed-TMR flip flop tolerant to temporal errors from ombinational iruits and FFs. (DTMR) [4]. Fig. 4 Delayed-DMR flip flop (DDMR FF or BISER) using a delay element, C-elements and weak keepers to remove SETs and SEUs [3]. It shows tight robustness to soft errors from ombinational iruits and FFs, but the area penalty should be huge. It is more than 3 times bigger than a non-redundant iruit. Figure 3 is a delayed-tmr FF (DTMR) [4] tolerant to soft errors on ombinational iruits, master and slave lathes. Two delay elements denoted by τ prevent an SET pulse being aptured by multiple lathes. Temporal soft errors on lathes an be resolved using the voter and delay elements. An SET pulse from the voter an be removed by the delay elements on the next stage. Thus a voter is plaed after slave lathes and have no redundany. Figure 4 is a delayed DMR (DDMR) FF using C- elements and weak keepers (BISER) [3]. A C-element and a weak keeper hold the urrent value if two input signals are different. It is also robust to an SET pulse from ombinational iruits and also to an SEU on lathes or weak keepers. But it is very weak against an SET pulse from C- elements. If an SET pulse is generated from a C-element before the slave lathes, both of them apture the inorret value aused by the SET pulse. 2.3 Proposed DMR Flip Flops Immune Against Soft Errors on C-Elements As desribed in the previous setion, the onventional BISER FF is not resilient to SET pulses on the C-element. We propose two modified struture to enhane SER immunity with small area and delay penalty. In order to avoid multiple flips on lathes by an SET pulse from the C- element, one possible solution is to insert another delay element between the C-element and the redundant slave lath. The other solution adds another pair of the C-element and weak keeper between redundant master and slave lathes. Figure 5 shows one proposed struture alled Double- Delayed DMR FF (D 3 MR FF). To avoid multiple flips aused by an SET pulse from the C-element, an additional delay element is attahed before the redundant slave lath. But the dual modular FF has a fundamental drawbak to eliminate multiple flips by a delay element. It is beause the weak keeper prolongs an SET pulse. When an SET pulse is generated at the input port of the slave lath, the weak keeper is flipped temporally. The feedbak inverter in the weak keeper prevents the input port going bak to its original state. Figure 6 shows another proposed struture alled Enhaned delayed DMR FF (ED 2 MR FF). C-elements and weak keepers between master/slave lathes are doubled to avoid simultaneous flips on slave lathes. It ahieves small area and delay penalties ompared with D 3 MR FF. Details of the error resilieny, area and delay overhead of the proposed and onventional multiple-modular FFs are disussed in Set. 4.

3 Soft Error Rates of FFs Here we estimate amount of harge to flip lathed in a DICE lath and multiple-modular FFs aused by a partile hit on lathes, weak keepers and ombinational iruits by iruitlevel simulations and show analytial equations to ompute SERs of soft error tolerant FFs. 3.1 Estimation of SERs by Critial Charge Table 1 Parameters for SER estimation. F m 2 s 1 Q s 13fC K 2.2e-5 f 1 GHz T ps In the terrestrial environment, high-energy neutrons are main soures of errors. A high-energy neutron injeted to silion produes a seondary harged partile. If it hits a silion atom near a drain region, eletrons or holes are olleted to the drain region by drift and diffusion. We use the single-exponential model as in Eq. (1) [5], for transient urrent aused by the partile. I(t) = Q 2 T π t ( t ) T exp T where T is a time onstant depending on a fabriated proess and Q is a total harge olleted to the drain region. Q rit is defined as the minimum harge to flip a lath in FFs. After obtaining Q rit, Eq. (2) from [6] is used to ompute SERs. ( N SER (Q rit ) = F A K exp Q ) rit (2) Q s where F is the high-energy neutron flux and A is the drain area of transistors related to soft errors. K is a fitting parameter. Q s is alled harge olletion effiieny that is orrespond to the sensitivity of the ritial harge. Q s strongly depends on doping and supply voltage [7]. We use the parameter values as in Table 1 obtained from [6] for a 100 nm proess. But iruit simulations are done by 90 nm proess parameters. We use three different T value, 10 ps, 20 ps and 30 ps, sine T widely hanges by proess onditions. On the other hand, Q s value is equivalent to that of the 100 nm proess beause Q s is proportional to the proess saling instead of proess onditions. In our experiments, an ideal urrent soure in Eq. (1) is attahed to a iruit node to estimate the ritial harge. Ciruit-level simulations with a 90 nm proess estimate amount of ritial harge by adding the ideal urrent soure on a node of a partile hit. We assume the following onditions to simply iruit simulations. 1. Partiles hit on drain regions of only NMOS, not PMOS. 2. NMOS is always off so as to flip the inverter by the harges generated from the partile hits. From the ondition 1, we may underestimate the SER. The overall SER should be doubled in the CMOS iruits. But it an be said that the probability when NMOS is off is 50%. Therefore, the above assumption gives the reasonable SERs onsidering partile hits on both NMOS and PMOS. (1) Fig. 7 Inverter hain with fanouts. A high-energy neutron hits to N SER Caused by a Partile Hit on Combinational Ciruits Figure 7 shows a iruit struture to estimate SEUs aused by SET pulses from ombinational iruits. We assume that a 11FO4 inverter hain is onneted to an FF. Q rit of logi gates annot be estimated easily sine operating iruits fail only when a generated transient pulse is lathed. We have to onsider these three masking effets to estimate SEUs aused by SET pulses from logi gates, eletrial masking, lathing window masking and logial masking [8]. Beause of eletrial masking, SET pulses are gradually attenuated after passing through the series of logi gates. Table 2 shows amount of required harge on N0 to generate an SET pulse at the output node of the 11FO4 inverter hain. The row of the Minimum means the required harge to generate a minimum pulse at the output node, while that of the 50 [ps] means the required harge to generate a pulse ontinuing for 50 ps at the output node. By assigning eah value of harge to Q rit in Eq. (2), we an obtain the rate of the pulse above the width suh as 50 ps, 75 ps, et. After obtaining the harge tables for all nodes (N0-N10), the rate of the SET pulse above all widths in the table an be derived by aumulating the error rates of all nodes. Table 3 shows the rate of the SET pulse above the speified with (N I )andtherate of the SET pulse between the speified width range (ΔN I ). An SEU happens if an SET pulse is longer than the sum of setup and hold time of an FF alled lathing window. But the possibility to lath the SET pulse is varied aording the the lathing window time w and the lok period. The total SER aused by the 11FO4 inverter on the non-redundant onventional FF is omputed from Eq. (3) [8]. +w N IFF = ΔN I (t) t w dt (3) w where ΔN I (t) denotes the rate of the SET pulse with the

4 FURUTA et al.: AN AREA/DELAY EFFICIENT DUAL-MODULAR FLIP-FLOP WITH HIGHER SEU/SET IMMUNITY 343 Table 2 Amount of required harge at N0 to generate an SET pulse at the output node of the 11FO4 inverter hain. Pulse Q[fC] Width [ps] N0 N2 N4 N6 N8 N10 Minimum NA Table 4 SER in FIT/bit of a 11FO4 inverter hain aording to τ of delay elements. T(ps) 10ps 20ps 30ps τ(ps) DMR TMR DMR TMR DMR TMR 0 9.3e-5 1.0e-4 9.7e e-6 5.1e-6 2.7e-5 5.3e-5 3.8e-5 7.3e e e e-6 1.0e-5 1.5e-5 3.0e e-8 1.1e-7 3.2e-6 6.5e-6 Table 3 Rate of the SET pulse aording to the pulse width. Pulse Width [ps] N I [FIT] PW Range[ps] ΔN I [FIT] Min e-03 Min e-04 < e e-04 > e e-04 > e e-04 > e e-04 > e e-06 > e e-13 > e-32 Fig. 9 A Lath iruit diagram. A high-energy neutron hits to N0, 1 or 2 to flip the stored value of the lath. Fig. 8 Filtering a SET pulse by delay elements. of the delayed FFs are expressed as follows. N IDTMR = 2 + 2τ+w τ+w +w 2τ+w ΔN I (t) t τ w dt N I DDMR = N ID 3 MR = N IED 2 MR 2τ+w ΔN I (t) t w dt (4) = ΔN I (t) t τ w dt (5) τ+w Table 4 shows SER of a 11F04 inverter hain omputed from Eqs. (4), (5). It is exponentially redued by τ of the delay element. 3.3 SER Caused by a Partile Hit on Lathes pulse width t, whih value an be omplemented from ΔN I in Table 3. The SER aused by the 11FO4 inverter on DICE lath is also omputed from Eq. (3) beause of having no mitigation to SET pulse. A delay element before redundant master lathes prevents to flip multiple lathes by an SET pulse. Suppose that the width of an SET pulse is P and P <. Figure 8 explains three onditions in the ase of DDMR and DTMR flip flops. A delay element with τ delay time prevents multiple flip flops to apture an inorret value aused by an SET pulse shorter than τ + w (Condition 1). When τ + w<p < 2τ + w, multiple FFs may apture an inorret value for (P τ w) within a lok yle (Condition 2). The lathing window appears one in DDMR and twie in DTMR. When P > 2τ+w, the period to apture an inorret value beomes P w only in DTMR (Condition 3). By onsidering the above three onditions, error rates A lath in Fig. 9 is used for simulations. If CLK is 0, DATA drives all inverters and CMOS swithes in the lath. Therefore, SEUs at CLK=0 an be ignored and the possibility of SEUs in lathes is almost halved. The total SER of a lath is expressed as in Eq. (6) N L = N SER (Q Li ) (6) i=0 where Q L0, Q L1, Q L2 are the ritial harges to flip the lath aused by partile hits at N0,1,2respetively. In the ase of the DICE lath, the total SER is desribed as in Eq. (7). N D = N SER (Q Di ) (7) i=0

5 344 Q Di indiate the ritial harges of four storage nodes. Table 5 shows SERs in FIT/bit of lath and DICE lath. Compared with lath, DICE lath is very strong to SEU in our simulation results. In the delayed TMR iruit, even if one lath flipped by a partile hit, it keeps orret value by a voter. However, if two or three lathes are flipped by partile hits during a lok yle, it annot keep orret value. Hereafter, we all the error in whih an FF is flipped to the wrong state as ritial error. For example, it is a ritial error when two master/slave lathes are flipped in the TMR FFs. The SER aused by SEUs on lathes (N LDTMR ) is desribed as in Eq. (8). N LDTMR = 3 N 2 L N3 L 3 N 2 L (8) Figure 10 shows how to estimate SER of the DDMR FF. The bottom two lines in Table 5 are SERs of a weak keeper and a C-element. SER of the weak keeper is the sum of SERs aused by partiles on N3-5. If there is no error on the two masterlathes, N4 is strongly driven by the inverter. But when one of master lathes is flipped, N4 is floating. In that ase, a partile hit on N3 flips the state of the weak keeper and auses ritial error. The SER values in Table 5 is estimated onsidering these floating state. SER of the C- element is defined as the SER in whih two slave lathes are flipped by an SET pulse from the C-element. As shown in Table 5, SERs of the weak keeper and C-element are lose to that of the lath. An SEU on a weak keeper an be reovered by the C-element. On the other hand, simultaneous SEUs on the two slave lathes aused by SET pulses on the C-element always beome ritial errors. The total SER of the DDMR FF aused by a partile hit on lathes, weak keepers and C-elements an be expressed as follows. N L DDMR N 2 L + 2N LN W + N C (9) Table 5 SERs in FIT/bit of a lath, weak keeper and C-element. T 10 ps 20 ps 30 ps Lath (N L ) 3.4e-4 3.3e-4 3.1e-4 DICE lath (N D ) NO ERROR NO ERROR 4.1e-37 Weak Keeper (N W ) 2.4e-4 3.8e-4 3.5e-4 C-element (N C ) 1.9e-5 2.7e-5 3.0e-5 +w N C = ΔN C (t) t w dt (10) w where ΔN C (t) denotes the rate of the SET pulse on the C- element with the pulse width t. As shown in Eq. (9), the SER of the DDMR does not beome small beause of the SER of the C-element (N C ). These simultaneous SEUs on the slave lathes should be eliminated to derease the error rate. In the ase of our proposed DMR FFs, N C is eliminated by delay element or doubled C-element and expressed as follows. 2τ+w N CD 3 MR = ΔN C (t) t τ w dt (11) τ+w N CED2 MR = (N C ) 2 (12) Compared with DDMR, D 3 MR FF and ED 2 MR FF ahieves relatively small SER. 4. Simulation Results 4.1 Total SERs of the Conventional Redundant FFs From Eqs. (3) (12), we an ompute the total soft error rates onsidering SEUs aused by a partile hit on FFs or inverter hains onneted to them. Table 6 shows the total SERs of DICE lath and redundant FFs with the 11FO4 inverter hain at their input ports. We assume three time onstant (T) values from 10 ps to 30 ps. Sine DICE lath an not mitigate SET, its soft-error tolerane is just 10 times stronger than ordinal FF. This result show that SET mitigation is neessary to ahieve higher soft error tolerane. Figures show the total SERs of multiplemodular FFs and proposed FFs from delay value τ=0ps to τ=200 ps. If a suffiient value of τ is seleted, DTMR FF, D 3 MR FF and ED 2 MR FF ahieve SERs almost equivalent to onventional TMR FF whih triples all iruit omponents. However, the SER of the DDMR FF is 1/20 1/40 of the ordinal non-redundant FF. It is beause the SER by the C-element is relatively high as desribed in Eq. (9). SERs of delayed FFs are dereasing aording to τ. We hoose the values of τ to saturate the SER to the minimum values. Table 6 SERs of onventional redundant FFs. T=10 ps T=20 ps T=30 ps Ordinal FF 7.7e e e-04 DICE lath 9.3e e e-5 TMR FF 3.8e e e-28 DTMR FF 3.8e e e-26 (τ) (100 ps) (150 ps) (200 ps) DDMR FF 1.9e e e-05 (τ) (75 ps) (100 ps) (125 ps) D 3 MR FF 4.4e e e-27 (τ) (100 ps) (150 ps) (250 ps) Fig. 10 Estimation of SER of weak keeper and C-element. High-energy neutron on N3-5 may flip a weak keeper and two slave lathes. ED 2 MR FF 4.4e e e-27 (τ) (100 ps) (150 ps) (200 ps)

6 FURUTA et al.: AN AREA/DELAY EFFICIENT DUAL-MODULAR FLIP-FLOP WITH HIGHER SEU/SET IMMUNITY Area and Delay Overhead of the Proposed Dual Modular FFs Table 7 and Fig. 14 shows area, delay and power onsumption of the proposed DMR FFs and the DTMR FF normalized by those of onventional non-redundant FF. Note that the τ is hosen to make the SER is less than 1e-7 FIT. In the error rate of 1e-7 FIT, one million high-end proessors inluding 120 thousand FFs keep on working for one year. Note that an 11FO4 inverter hain is attahed to eah FF to simplify the SER estimation. It may be relatively low error rate. But when 1000 proessor ores embedded in a workstation, one Million proessors are equivalent to 1000 workstations. The area is omputed to sum up areas of lathes, inverters for delay elements, voters and C-elements implemented in standard ells. The delay and power onsumption are estimated by iruit-level simulations using a 90 nm proess parameter. Delay is defined as the minimum transition time from D (FF input) to Q (FF output). Power is defined as Fig. 11 T=10 ps. Total SERs of multiple-modular FFs and proposed FFs at Fig. 13 T=30 ps. Total SERs of multiple-modular FFs and proposed FFs at Fig. 12 T=20 ps. Total SERs of multiple-modular FFs and proposed FFs at Fig. 14 Area and delay of the onventional and proposed FFs normalized by those of the onventional non-redundant FF. Table 7 Area, delay and power onsumption of the proposed DMR and DTMR FFs normalized by those of onventional non-redundant FF. (τ is hosen to make the SER <1e-7) T=10 ps T=20 ps T=30 ps τ Area Delay ADP* Power τ A D ADP P τ A D ADP P DTMR FF 75 ps ps ps D 3 MR FF 75 ps ps ps ED 2 MR FF 75 ps ps ps ADP: Area-Delay Produt

7 346 maximum dynami onsumption at 1 GHz lok frequeny. As shown in Table 7, all delay values are over 2 times larger than the onventional non-redundant FF, whih is mainly beause the delay elements prolong the delay time of redundant lathes. For all T values from 10ps to 30ps, ED 2 MR FF shows smallest area-delay produt (ADP). For T=30 ps, ED 2 MR FF ahieves 13.4 ADP whih is 58% of the DTMR FF and 46% of the D 3 MR FF respetively. ED 2 MR FF also shows smallest power onsumption. For T=30 ps, ED 2 MR FF onsumes 4.3X ompared with non-redundant FF whih is 73% of the DTMR FF and 74% of the D 3 MR FF respetively. 5. Conlusion In this paper, we estimate the SERs of DICE lath and onventional redundant flip-flops to eliminate soft errors on LSIs. Sine DICE lath an not mitigate SET, its soft-error tolerane is 10 times stronger than ordinal FF. On the other hand, it is revealed that so-alled BISER FF is very weak to soft errors and annot ahieve over 50 times stronger softerror tolerane sine a partile hit on the C-element an flip the two slave lathes simultaneously with high possibility. In order to mitigate errors aused by the C-element, we propose two strutures modified from the original BISER FF. One struture alled ED 2 MR (Enhaned Dual Modular Redundany) FF ahieves SERs almost equivalent to delayed TMR FF by doubling C-elements and weak keepers between master/slave lathes. It ahieves 76% area, 76% delay, 73% power onsumption and 58% Area-Delay produt of the delayed TMR FF on the lower soft error rate below 1e-7FIT/bit. Referenes [1] T. Calin, M. Niolaidis, and R. Velazo, Upset hardened memory design for submiron CMOS tehnology, IEEE Trans. Nul. Si., vol.43, no.6, Part 1, pp , [2] L. Anghel, D. Alexandresu, and M. Niolaidis, Evaluation of a soft error tolerane tehnique based on time and/or spae redundany, SBCCI 00: Pro. 13th Symposium on Integrated Ciruits and Systems Design, p.237, IEEE Computer Soiety, Washington, DC, USA, [3] S. Mitra, M. Zhang, N. Seifert, B. Gill, S. Waqas, and K. Kim, Combinational logi soft error orretion, International Test Conferene, [4] D. Mavis and P. Eaton, Soft error rate mitigation tehniques for modern miroiruits, Pro. Reliability Physis Symposium, 40th Annual, pp , [5] L.B. Freeman, Critial harge alulations for a bipolar SRAM array, IBM J. Res. Dev., vol.40, no.1, pp , [6] P. Hazuha, C. Svensson, and S. Wender, Cosmi-ray soft error rate haraterization of a standard 0.6-μmCMOS proess, IEEE J. Solid- State Ciruits, vol.35, no.10, pp , [7] P. Hazuha and C. Svensson, Impat of CMOS tehnology saling on the atmospheri neutron soft error rate, IEEE Trans. Nul. Si., vol.47, no.6, pp , [8] P. Shivakumar, M. Kistler, S. Kekler, D. Burger, and L. Alvisi, Modeling the effet of tehnology trends on the soft error rate of ombinational logi, Internatiol Conferene on Dependable Systems and Networks, pp , Jun Furuta reeived the B.E. degree in Eletrial and Eletroni Engineering from Kyoto University, Kyoto, Japan, in He is presently a master s ourse student at Kyoto University. Kazutoshi Kobayashi was born in Kyoto, Japan in He reeived the B.E., M.E. and Dr.Eng. degrees in Eletroni Engineering from Kyoto University, Kyoto, Japan, in 1991, 1993, 1999, respetively. His interests are in reonfigurable arhitetures utilizing devie variations, arhitetures and implementations of parallel omputers. He was an Instrutor ( ), an Assoiate Professor ( , ) in Department of Communiations and Computer Engineering, Graduate Shool of Informatis, Kyoto University. From 2002 to 2004, he was an Assoiate Professor of VLSI Design and Eduation Center (VDEC) at the University of Tokyo. Sine 2009, he is a Professor in Kyoto Institute of Tehnology. He reeived a best paper award of IEICE in 2009 He is a member of IEEE and IPSJ. Hidetoshi Onodera reeived the B.E., and M.E., and Dr. Eng. degrees in Eletroni Engineering from Kyoto University, Kyoto, Japan, in 1978, 1980, 1984, respetively. He joined the Department of Eletronis, Kyoto University, in 1983, and urrently a Professor in the Department of Communiations and Computer Engineering, Graduate Shool of Informatis, Kyoto University. His researh interests inlude design tehnologies for Digital, Analog, and RF LSIs, with partiular emphasis on high-speed and lowpower design and analysis for manufaturability, and SoC arhitetures. Dr. Onodera served as the Program Chair and General Chair of ICCAD and ASP-DAC. He was the Chairman of the Tehnial Group of VLSI Design Tehnologies, IEICE, Japan, and the Chairman of the IEEE Kansai SSCS Chapter, and the Chairman of the SIG-SLDM (System LSI Design Methodology), IPSJ, Japan. He is urrently the Chairman of the IEEE Kansai CASS Chapter. He served as the Editor-in-Chief of IEICE Transations on Eletronis, and urrently he is serving as the Editor-in-Chief of IPSJ Transations on System LSI Design methodology.