Article Power Balancing Control for Grid Energy Storage System in Photovoltaic Applications Real Time Digital Simulation Implementation

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1 Article Pwer Balancing Cntrl fr Grid Energy Strage System in Phtvltaic Applicatins Real Time Digital Simulatin Implementatin Sridhar Vavilapalli 1, Sanjeevikumar Padmanaban 2, *, Umashankar Subramaniam 1 and Lucian Mihet-Ppa 3 1 Department f Energy and Pwer Electrnics, Schl f Electrical Engineering, VIT University, Vellre , India; sridhar.spark@gmail.cm (S.V.); shankarums@gmail.cm (U.S.) 2 Department f Electrical and Electrnics Engineering, University f Jhannesburg, Auckland, Jhannesburg 2006, Suth Africa 3 Faculty f Engineering, Østfld University Cllege, Kbberslagerstredet 5, 1671 Kråkery, Fredrikstad, Nrway; lucian.mihet@hif.n * Crrespndence: sanjeevi_12@yah.c.in; Tel.: Academic Editr: Sergi Sapnara Received: 19 May 2017; Accepted: 30 June 2017; Published: 5 July 2017 Abstract: A grid energy strage system fr pht vltaic (PV) applicatins cntains three different pwer surces i.e., PV array, battery strage system and the grid. It is advisable t islate these three different surces t ensure the equipment safety. The cnfiguratin prpsed in this paper prvides cmplete islatin between the three surces. A Pwer Balancing Cntrl (PBC) methd fr this cnfiguratin is prpsed t perate the system in three different mdes f peratin. Cntrl f a dual active bridge (DAB)-based battery charger which prvides a galvanic islatin between batteries and ther surces is explained briefly. Varius mdes f peratin f a grid energy strage system are als presented in this paper. Hardware-In-the-Lp (HIL) simulatin is carried ut t check the perfrmance f the system and the PBC algrithm. A pwer circuit (cmprised f the inverter, dual active bridge based battery charger, grid, PV cell, batteries, cntactrs, and switches) is simulated and the cntrller hardware and user interface panel are cnnected as HIL with the simulated pwer circuit thrugh Real Time Digital Simulatr (RTDS). HIL simulatin results are presented t explain the cntrl peratin, steady-state perfrmance in different mdes f peratin and the dynamic respnse f the system. Keywrds: active pwer cntrl; battery charging; dual active bridge; energy strage system; hardware-in-the-lp; LCL filter 1. Intrductin In slar pwer plants, active pwer transfers frm the pht vltaic (PV) array t the grid during daytime and the array lses its pwer generating capability during nighttime r when the slar irradiatin is weak. T als supply pwer t the grid during nighttime, energy strage is required. Since the pwer requirements during nighttime are usually much lwer than thse during the daytime, energy strage with 25% f the PV array rated pwer may be selected fr 24-h peratin. A blck diagram f a grid energy strage system in a slar PV pwer plant is shwn in Figure 1. Energies2016, 9, 928; di: /en

2 2016, 9, f 22 Figure 1. Generalized blck diagram f a grid energy strage system in pht vltaic applicatins. The different mdes f peratin f the abve system are explained belw: Mde1: During the daytime, the PV array feeds active pwer t the grid thrugh an inverter and prvides charging current t the battery thrugh the battery charger. Mde2: The battery is in charged cnditin and the PV array cannt feed full pwer t the grid i.e., during partial cludiness r during nighttime r when the slar irradiatin is weak. In this mde f peratin, PV array feeds the pwer t the grid based n maximum pwer pint (MPP) and the batteries als feed active pwer t the grid. Mde3: The battery is in fully discharged state and the PV array cannt prvide the charging current t the battery i.e., during nighttime. In this mde f peratin, the grid prvides the charging current t the batteries thrugh the inverter and battery charger. With such systems, it is als pssible t charge the batteries frm the grid during nn-peak lad hurs and the batteries alng with PV array feed pwer t the grid during peak lad hurs [1]. Since the system is cnnected t three different pwer surces i.e., PV array, battery strage system and the grid, these three pwer surces need t be islated t ensure the safety f the equipment. Existing energy strage systems fr PV applicatins using a buck-bst chpper-based battery charger are briefly explained belw. In the cnfiguratin presented in [2], a DC-DC cnverter is cnnected between the PV array and PV inverter and the battery is cnnected acrss the DC link as shwn in Figure 2a. In such systems, the DC/DC cnverter needs t be designed fr the maximum capacity f the PV array even thugh the battery capacity is much less when the system perates in Mde3, the inverter shuld act like an active rectifier t charge the batteries and there is n islatin between the PV array and the batteries. In the cnfiguratin shwn in Figure 2b, the PV array and PV inverter are cnnected t the DC link and the battery is cnnected t the DC link thrugh a buck-bst chpper. In this case, the charger needs t be rated nly fr the rating f the battery. In the cnfiguratin presented in [3,4], independent DC-DC cnverters are required t cnnect the battery and PV array t the DC link as shwn in Figure 2c. An ptimized peratin f a dual active bridge (DAB) cnverter feeding a PV inverter cnnected t the grid is presented in [5,6]. Islatin between the grid and DC side is prvided thrugh a highfrequency transfrmer used in the DAB as shwn in Figure 2d. In such a cnfiguratin, the DAB needs t be designed fr the full capacity f the PV array. Since the design f a DAB is cmplex fr high pwer ratings, this cnfiguratin is mre suitable fr lw pwer applicatins. There is als n islatin between the DC link and the pwer bank with this cnfiguratin.

3 2016, 9, f 22 Figure 2. Buck-bst chpper-based energy strage system cnfiguratins fr pht vltaic applicatins (a); tw stage cnversin with battery directly cnnected t DC Link (b); single stage cnversin with chpper based Battery charger (c); tw stage cnversin with chpper based battery charger (d); dual active bridge based pht vltaic inverter with chpper based battery charger. Frm the abve discussins, it is bserved that buck-bst chpper-based ESS cannt prvide cmplete islatin. In this paper, a DAB-based energy strage system (ESS) fr PV applicatins is prpsed which can mitigate the drawbacks f buck-bst chpper-based systems. In the DAB-based ESS cnfiguratin, PV array and the PV inverter are directly cnnected t the DC link and the battery is cnnected t the DC link thrugh a DAB-based bi-directinal battery charger as shwn in Figure 3. A high-frequency transfrmer in the DAB prvides islatin between the DC link and the pwer bank. A transfrmer cnnected between the inverter and grid prvides islatin between the DC surces and AC grid. Figure 3. Dual active bridge-based energy strage system fr a grid cnnected PV system.

4 2016, 9, f 22 The fllwing technical features are the main advantages f the prpsed system: The battery charger nly needs t be designed fr the battery capacity. Independent cntrls fr the battery charger and inverter are pssible. When the system perates in Mde3, the inverter acts like a simple dide rectifier and the battery charger takes care f the charging current. The high-frequency transfrmer in the DAB prvides islatin between the PV array and the battery. In this paper, a pwer balancing cntrl fr the DAB-based energy strage system is prpsed and validated thrugh real-time simulatins. Detailed discussins n the prpsed system, design calculatins, and the cntrl structure are presented in Sectin 2. The prpsed pwer balancing cntrl algrithm is explained in Sectin 3. In Sectin 4, a hardware-in-the-lp (HIL) simulatin setup t validate the cntrl algrithm is explained. HIL results are presented in Sectin Dual Active Bridge Based Energy Strage System fr Pht Vltaic Applicatins As shwn in Figure 3, in a dual active bridge-based energy strage system, the PV array is cnnected t the DC link directly and the battery is cnnected t the DC link thrugh a DAB-based bidirectinal DC-DC cnverter. The PV inverter is cnnected t the grid thrugh an islatin transfrmer. The transfrmer secndary is the pint f cmmn cupling (PCC) i.e., the cupling pint f the grid, PV inverter utput and the lcal lad. A sine filter is used at the utput terminals f the PV-inverter t smthen the inverter utput vltage. In this paper, design, and cntrl f the prpsed system with a 100 kva PV-inverter and energy strage f 25% capacity fr 4 h minimum backup time are presented. An verview f the electrical requirements f the system is shwn in Table 1. Since the lcal lad is rated fr a 415 V, 50 Hz, 3-phase, the PCC vltage is selected t be the same as the rated vltage f the lcal lad t avid an additinal transfrmer acrss the lad and the PCC. Design calculatins fr the system t meet the electrical specificatins are presented in the next subsectin. Table 1. Electrical specificatins/requirements f the system. SL. NO Parameter Value Units Remarks 1 Grid Vltage 11 kv 3-Phase 2 Grid Frequency (F) 50 Hz 3 PCC Vltage 415 V Rated Vltage f Lcal lad 4 Maximum PV-Inverter Pwer 100 kw 5 Backup Pwer 25 kw 25% f PV-Inverter Pwer 6 Minimum Back Up Time 4 h 2.1. Design Calculatins fr the Pht Vltaic-Inverter The design calculatins fr the inverter and the filter are presented in Table 2. An LCL filter (2 inductances-l cnnected in series with a capacitr-c in parallel) is ften used t intercnnect an inverter t the utility grid in rder t filter the harmnics prduced by the inverter. Since the PCC vltage is 415 V and the grid vltage is 11 kv, the grid side transfrmer with a transfrmatin rati f 11 kv/415 V with minimum 100 kva rating is selected. Due t the L-C-L filter used at the utput side f the inverter, there is an vltage drp acrss the filter, s the inverter utput vltage shuld be the sum f PCC vltage and the vltage drp acrss the filter. Cnsidering the sinusidal PWM (SPWM) technique fr pulse generatin, the minimum DC link vltage required is calculated based n the inverter utput vltage. Since the inverter needs t be designed t handle the filter capacitr current in additin t the rated lad current, an ptimal filter capacitr is selected which draw less than 5% f rated current. The Inverter side inductr L1 is derived frm the value f the capacitr C and the crner frequency Fc. After selecting the inductr L1, the grid side inductr L2 can be selected based n the maximum filter drp allwed. Inductance

5 2016, 9, f 22 L2 can als be made part f the transfrmer n the grid side t eliminate the physical inductr L2 in the system. Table 2. Design calculatins fr the pht vltaic-inverter. SL. NO Parameter Value Units Remarks 1 Pwer Rating 100 kw 2 PCC Vltage (Vpcc) 415 V 3 Inverter RMS Current 140 A Pwer/(1.732 PCC Vltage) 4 Maximum Filter Drp 6 % Drp acrss L-C-L Filter 5 Inverter Vltage (Vinv) 440 V PCC Vltage + filter Drp 6 Minimum DC Link Vltage 620 V Vdc = (Vinv/0.71) With SPWM Selectin f Filter Capacitr (C) 7 Maximum Reactive Pwer(Qc) 5 % 5% f 500 kva i.e., 25 kvar 8 Current Rating f Capacitr (Ic) 11.5 A Qc/PCC Vltage 9 Maximum Capacitance 85 uf Ic/(2 * pi * F * Vpcc) 10 Selected Value f Capacitance 80 uf <Maximum capacitance Selectin f Inverter Side Filter Inductr (L1) 11 Crner Frequency selected (Fc) 1.25 khz Switching Frequency/4 12 Inductance f Inductr L1 203 uh Fc = 1/[2 * pi * (LC)] 13 % Vltage Drp in Inductr L1 2.1 % [Irms (2 * pi * F * L1)]/Vpcc Selectin f Grid Side Filter Inductr (L2) 14 Maximum Drp allwed acrss L2 3.9 % Max Drp-% Drp acrss L1 15 Maximum Inductance f L2 382 uh (3.9% * Vpcc)/[Irms * 2 * pi * F] 2.2. Selectin f Battery Type The prcedure fr the calculatin f PV pwer requirement fr battery charging is explained in Table 3. As mentined earlier, since the pwer requirement during nighttime is much lwer than that during the daytime, an energy strage with 25% f the rated pwer f the PV array is selected. A Lithium-in battery with a nminal vltage f 350 V is selected as an energy strage in this system. The ampere-hur rating f the battery is decided based n the minimum backup time required and the battery discharging current. Similarly,the charging current f the battery is calculated based n the charging time and ampere-hur rating f the battery. The pwer required frm the PV array fr charging the battery is determined frm the battery nminal vltage and the charging current. Table 3.Electrical parameters f the battery. SL. NO Parameter Value Units Remarks Selectin f Battery 1 Nminal Vltage f Battery (Vnm) 350 V 2 Maximum Battery Vltage 406 V 116% f Vnm fr Li-In battery 3 Minimum battery Vltage 306 V >87.5% fr Safe peratin 4 Battery Rated Pwer 25 kw 25% f PV-Inverter rating 5 Maximum Battery Current 72 A Battery Pwer/Vnm 5 Minimum Backup time 4 h 6 Ah Rating f Battery 288 Ah Current X Backup Time 7 Battery Charging time 8 H PV Pwer availability time 8 Charging Current (I_Charging) 36 A Ah Rating/Charging Time 9 PV Pwer Required fr Charging 12.5 kw Vnm I_charging The battery selected fr this system can be mdeled as a vltage surce [1,7,8] and the mdel was implemented based n the equatin fr the battery vltage expressed as belw [9]. Battery Vltage: VBatt = E0 K [Q/(Q-I * T)] + Ae (-B * I * T) [IBatt * R] (1)

6 2016, 9, f 22 where VBatt is the battery vltage (V), IBatt is the battery current (A), E0 is the nminal vltage (V), Q is ampere-hur rating f the battery (Ah), B is the nminal discharge current (Ah) 1, K is the fully charged vltage (V)which is arund 116%, A is the expnential vltage (V), which is arund 105%, R is the internal resistance f the battery, and I * T is the discharged capacity (Ah) which is determined by integrating the battery current. State f charge f the battery can be btained after integrating the battery current: % SOC = 100 {1 [(I * T)/Q]} (2) 2.3. Selectin f the PV Array Frm the abve discussins, a PV array fr a minimum pwer rating f 113 kw is required, since a pwer f 100 kw fr the grid and 13 kw fr battery charging is required frm the PV array. Design calculatins fr the PV array using 435 watt PV mdule (Make: M/s Sunpwer, Mdel: SPR-435NE- WHT-D) is explained and the prcedure fr selecting a number f series, parallel PV mdules in a PV array is als presented in Table 4. An perating temperature range f 25 t 55 C is cnsidered fr the calculatins. PV mdule parameters such as MPP vltage, MPP current, pen circuit vltage and shrt circuit current at 25 C are btained frm the data sheet and the values at 55 C are derived using the temperature cefficients f the PV mdules. The perating range f PV mdule vltages and currents are tabulated. Table 4. Pht vltaic array selectin. SL. NO Parameter Value Units Remarks PV Array Requirement 1 Minimum Pwer Requirement 113 kw PV Inverter + Charging Pwer 2 Minimum PV Vltage (V_PV_Min) 620 V Vdc Minimum Refer Table 2 3 Maximum PV Current 182 A Pwer/V_PV_Min Details f Selected PV Mdule 4 Make Sunpwer 5 Type Number SPR-435NE-WHT-D 6 Operating Temperature Range C Electrical Ratings f Selected PV Mdule at 25 C 7 Pwer Rating f Each Mdule 435 W 8 Open Circuit Vltage (Vc) 85.6 V 9 Shrt Circuit Current (Isc) 6.43 A Frm Datasheet 10 MPP Vltage (Vmpp 72.9 V 11 MPP Current (Impp) 5.97 A Temperature Cefficients f Selected PV Mdule 12 Temperature Cefficient fr pwer 0.38 %/K 13 Temperature Cefficient fr Vltage mv/k Frm Datasheet 14 Temperature Cefficient fr Vltage 3.5 ma/k Electrical Ratings f Selected PV Mdule at 55 C 15 Open Circuit Vltage (Vc) V 16 Shrt Circuit Current (Isc) A Derived Frm Values at 25 C and the 17 MPP Vltage (Vmpp) V Temperature Cefficients 18 MPP Current (Impp) 6.08 A Selected PV Mdule Electrical Ratings in the Operating Temperature Range 19 Minimum Vltage (Vmd_min) V Vmpp at 55 C 20 Maximum Vltage (Vmd_max) 85.6 V Vc at 25 C 21 Maximum Current (Imd_max) A Isc at 55 C 22 Maximum pwer (Pmd_max) 435 W Frm Datasheet Electrical Ratings f PV Array 23 Minimum N. f Mdules required (N) 260 N s PV pwer/pmd_max 24 Minimum N. f Mdules in Series (Nse) 10 N s V_PV_Min/Vmd_min 25 N. f Mdules in parallel (Np) 26 N s N/Nse 26 Minimum Vltage f PV Array V Vmd_min Nse 27 Maximum Vltage f PV Array 856 V Vmd_max Nse 28 Maximum pwer frm PV Array 113 kw Nse Np Pmd_max

7 2016, 9, f 22 The ttal number f PV mdules required in the PV array is calculated based n the ttal pwer requirement and the pwer rating f each PV mdule. The number f series PV mdules in a PV array is selected based n the minimum DC link vltage requirement fr the PV-inverter. Fr this system, the minimum DC link vltage required is 620 Vlts t match the inverter vltage with the PCC vltage. Hence the PV array minimum vltage shuld always be mre than 620 V in the perating temperature range. The minimum number f parallel PV mdules in the PV array is calculated frm a ttal number f PV mdules and the number f series PV mdules selected. The PV array can be mdeled as a current surce [1,7,10] and the mathematical expressin fr the PV array mdel is as given belw [11]. PV Current: I = Iph [Is (e (V + I * Rs )/N * Vt 1) ] [(V + I * Rs )/Rp] (3) where I is PV current and V is the PV vltage. Iph is the phtn current and it is expressed as: Iph = Irradiance * (Isc/Ir) (4) where Isc is the shrt circuit current f the PV array = Isc f each mdule, N represents the number f parallel mdules, Ir is the measured irradiance = 1000 W/m 2 (frm the datasheet), Is is the dide saturatin current and expressed as: Is = Isc/(exp(Vc/(n * Vt)) 1) (5) where Isc is the shrt circuit current f the PV array, Vc is the pen-circuit vltage= Vc f each mdule, multiply by the number f series mdules, n is the quality factr and Vt is the thermal vltage and expressed as: Vt = k * T/q (6) where k is Bltzmann s cnstant = , T is the perating temperature = 25 C, q is charge f an electrn = , RS is the series resistance f the PV array, Rp is the parallel resistance f the PV array Design Calculatins fr the Battery Charger Battery charger ratings are decided after selecting the PV array. Since the PV array and the battery charger are cnnected t the cmmn DC link, the battery charger input vltage range is the PV array perating vltage range. The battery charger utput vltage range is the battery perating vltage range. Based n the input and utput vltage range f the battery charger, an islatin transfrmer with a transfrmatin rati f 1:2 is selected. Electrical parameters fr the battery charger system are listed in Table 5. Table 5.Electrical parameters f the battery charger system. SL. NO Parameter Value Units Remarks Selectin f Battery 1 Battery Charger Rated Pwer 25 kw Battery discharging capacity 2 Battery Charger Input Vltage V PV Operating Range 3 Battery Charger Output Vltage V Battery Operating Vltage 4 Islatin Transfrmer Turns Rati 1:2 5 Transfrmer Primary Current 38 A Rated Pwer/Min Input Vltage 6 Transfrmer Secndary Current 82 A Rated Pwer/Min Output Vltage 7 Minimum kva f Primary 32.5 kva Primary Max Vltage Current 8 Minimum kva f Secndary 33.3 kva Secndary Max Vltage Current 9 Selected Transfrmer KVA Rating 35 kva Mre than minimum kva Design calculatins fr the prpsed system are explained briefly in this subsectin. The cntrl methdlgy fr the battery charger and the PV-inverter are explained in next subsectins.

8 2016, 9, f Cntrl f the Dual Active Bridge-Based Battery Charger The DAB-based DC-DC cnverter cnsists f tw H-bridges and a high-frequency transfrmer. The surce side H-bridge is cnnected t the DC link and the lad side H-bridge is cnnected t the battery, as shwn in Figure 3. A high-frequency transfrmer is required t match the battery vltage with the DC link vltage and als t prvide islatin between the PV array and the battery. The transfrmer s leakage inductance helps in bst peratin mde [12,13]. The transfrmer winding cnnected t the surce side H-bridge is cnsidered as the primary and the winding cnnected t the lad side H-bridge is cnsidered as the secndary. A cntrl blck diagram f the DAB-based battery charger is shwn in Figure 4. Surce side and lad side H-bridges act like a simple square wave inverter. Square pulses with 50% duty cycle are prvided t the lad side and surce side H-bridges. Pwer flw thrugh the DAB is cntrlled using phase shift cntrl. The pulse generatr prvides the gate pulses fr the surce side and lad side H-bridges based n the phase shift btained thrugh a PI cntrller. Figure 4. Cntrl blck diagram f the DAB-based battery charger. During current cntrl mde, when the battery current reference is zer, then the gate pulses fr surce side and lad side H-bridges will be in phase with each ther. During frward pwer flw i.e., fr charging the battery, the gate pulse f the surce side H-bridge will be in leading t the gate pulse f the lad side H-bridge. Similarly, during reverse pwer flw i.e., during battery discharging mde, the lad side gate pulse will be leading. The amunt f pwer transfer depends n the phase angle between the gate pulses fr the surce side bridge and lad side bridge. As the size and cst f a high-frequency transfrmer are much less than thse f a high-frequency transfrmer fr the same pwer rating, battery charger size and cst can be reduced by using a high-frequency transfrmer in a DAB. During vltage cntrl mde, the battery side H-bridge receives 50% duty cycle gate pulses and the DC link side H-bridge is cntrlled t maintain the DC link equal t the reference DC link vltage. The detailed cntrl philsphy f the DAB-based battery charging system during varius mdes f peratin is explained belw: (1) Inputs t the reference generatr blck are the mde f peratin, MPP f the PV array, active pwer reference, and battery vltage signals. (2) When the system is perating in either Mde1 r Mde3: The battery is in charging mde f peratin hence the battery current reference is taken as psitive. Based n the battery SOC, the reference charging current is btained thrugh a lk-uptable. When the battery SOC is in the range f 80 t 115%, then the battery charging current is maintained at 0.12 C i.e., 36 A (0.12 * amp-hur rating f battery) as shwn in Table 3.

9 2016, 9, f 22 When the battery is fully charged, then the battery vltage will reach the maximum vltage, then the reference battery current is made zer t avid vercharging. In this case, the peratin can be transferred t Mde2, if the lad requirement is mre than the PV pwer. When the battery is fully discharged, then the battery vltage will be less than 0.9 times the nminal vltage, then the charging current is adjusted t 0.2 C i.e., 57 A fr fast charging. (3) When the system is perating in Mde2: In this mde, the battery is in discharging mde f peratin hence the battery current reference is taken as negative. In this case, if the PV array is in an inactive state i.e., PV vltage is mre than the minimum DC link vltage required (i.e., 620 V) but the MPP f the PV array is less than the critical lad requirement: The battery discharging current is btained frm the Amp-hur rating f the battery and the discharging time. Since the minimum backup time in this system is 4 h, the user can adjust the backup time t be mre than 4 h. In case the PV vltage is less than the minimum DC link vltage required then the battery charger needs t prvide the required vltage t the DC link: In this case, the DC link vltage reference (Vdc_ref) is generated by the reference generatr. Vdc_ref is always maintained at mre than the minimum required DC link vltage (620 V) Cntrl f the Grid-Cnnected Pht Vltaic Inverter A typical grid cnnected slar pwer cnditining system cnsists f a three-phase tw level PV-inverter fr cnverting DC pwer t AC pwer, a sine filter t smthen the AC utput and a transfrmer t cuple the inverter and the grid. The transfrmer als prvides islatin between AC side and DC side. Figure 5 shws a cntrl blck diagram fr a grid cnnected PV-inverter. In this system, the PV array vltage and currents are t be mnitred fr MPP tracking and the grid vltage is t be mnitred fr the phase-lcked lp (PLL). The cntrller senses the charging current r discharging current f the battery and the MPP f the PV array and then calculates the maximum pssible pwer that can be fed t the grid. The current reference is generated based n the maximum pssible pwer and the PLL utput. Three phase grid vltage is applied t the PLL t find ut the angle wt. Angle wt btained thrugh the PLL is used t generate Id and Iq cmpnents frm three phase grid currents. After cmparing the reference Idq currents and actual Idq currents, the errr signals are given t the PI cntrllers fr the active and reactive pwer cntrl. The PI cntrller utputs are cnverted back t three Phase mdulating signals and given t the PWM generatr t generate inverter gate pulses [14,15].

10 2016, 9, f 22 Figure 5. Cntrl blck diagram f a grid-cnnected pht vltaic inverter. The perturb and bserve methd is used fr maximum pwer pint tracking (MPPT). In this methd, the fllwing activities are carried ut: (a) Initially, When the system starts the PV pwer (Ppv) = 0 In this state, PV vltage = Vc and the PV current = 0 Initialize PV pwer reference MPP = 0 Minimum PV pwer reference (MPP_Ref_Min) is limited t 0. Maximum PV pwer reference (MPP_Ref_Max) is limited t 113 kw. (b) Nw increase the PV pwer reference (MPP) in 500 Watt steps: Measure PV vltage and current and calculate the new PV pwer (Ppv_New) If Ppv_New is mre than Ppv Ppv == Ppv_New MPP == MPP +500 Watt If Ppv_New is less than Ppv Ppv == Ppv_New MPP == MPP 500 Watt (c) Based n MPP_Ref and battery current, the reference inverter current is btained. (d) Steps b and c perate in a cntinuus lp. (e) Since this activity is nt required when the slar irradiatin is weak, this lp can be bypassed during the nighttime Operatin Sequence f the System The nrmal peratin sequence f the system is explained belw: (a) During nighttime, the PV vltage is less than the minimum required DC link vltage. Cnsidering that the battery is in discharged mde and being charged frm the grid, hence the system is in Mde3. (b) Nw when the irradiatin imprves in the mrning, MPP tracking is started and when the MPP becmes mre than the minimum pwer required fr system peratins and ther critical requirements then the system switches t Mde1. (c) As the irradiance imprves during the daytime, since the battery charging pwer is almst cnstant, pwer transfer t the grid increases. (d) Again when the irradiatin is getting reduced, the pwer transferred t the grid als reduces. (e) In case the pwer requirement fr the grid is mre than the available PV pwer, then the system can be transferred manually t themde2 peratin t meet the pwer demand. (f) When the irradiatin reduces further and becmes zer, then the battery stays in Mde2 till the battery gets discharged and the peratin shifts t Mde3 and the prcess lps back t step (a). In this wrk, a new pwer balancing cntrl algrithm fr the prpsed cnfiguratin is develped t meet the peratinal requirements f the system. The prpsed algrithm is explained in the next sectin. 3. Pwer Balancing Cntrl f the Grid Energy Strage System in Pht Vltaic Applicatins Pwer cntrl f PV with ESS fr ff-grid applicatins is presented in [16]. In the system presented, the battery and PV arrays are cnnected t the cmmn AC lad thrugh independent cnverters i.e., as an AC-centric system. During charging f the battery, the PV array supplies pwer t the AC lad and battery. When the battery is fully charged, the battery and PV arrays supply pwer t the cmmn AC lad. Cnditins fr battery charging and discharging and cntrl f pwer

11 2016, 9, f 22 cnverters during Mde1 and Mde2 peratin are explained briefly. Experimental results were presented t shw the dynamic respnse f the system during mde changever. Cntrl fr high pwer PV + a fuel cell plant with hybrid energy strage cnsisting f a battery and the supercapacitr is presented in [17]. Each energy surce and energy string element are cnnected t a cmmn DC link thrugh independent cnverters in this cnfiguratin. Energy management amng the different surces, cntrl fr charging the super-capacitr and batteries is explained briefly. Experimental results were presented fr explaining the dynamic characteristics f the system and plant perfrmance during lng lad and shrt lad cycles. Since the system presented is fr ff-grid applicatins, Mde3 peratin i.e., charging the battery frm the grid supply is nt cvered in this wrk. Real-time simulatin f the hybrid energy system with wind-pv-battery strage is presented in [18]. In the presented system, independent cnverters fr battery, PV mdules, and the wind are used. Based n the pwer availability f all the surces, an algrithm is develped fr battery charging, discharging and lad shedding. The systems presented in [16 18] are fr ff-grid applicatins hence the cntrl during Mde3 f peratin is nt cvered. System cnfiguratins presented in the abve wrks require independent cnverters fr each surce, which may increase the cst f the system and als may increase the cmplexity f the cntrl algrithm. The abve mentined drawbacks can be mitigated with the prpsed system cnfiguratin and with the pwer balancing cntrl algrithm explained in the next subsectin. The prpsed system is the cmbinatin f three phase PV inverter and a DAB-based battery charger explained in Sectin 2. Pwer flw thrugh the inverter can be cntrlled ver a wide range thrugh current cntrl. Battery current can be cntrlled in bth directins thrugh DAB using a phase angle cntrl. Pwer balancing amng the three surces in the presently prpsed system is achieved by cntrlling the pwer flw thrugh the battery charger and inverter. The pwer balance cntrl algrithm shwn in Figure 6 is explained belw: (1) Once the system is ready and the start cmmand is given by the user, the cntrller reads the grid vltages fr determining wt thrugh PLL. (2) The cntrller initializes the value f the inverter reference current (Id_Inv_Ref) and battery reference currents (I_Batt_Ref) as 0. (3) The cntrller reads the PV vltage (Vpv), PV current(ipv), battery vltage(vbatt) and battery current (I Batt) If the PV vltage (Vpv) is less than the minimum PV vltage required (Vpv_Min) then MPP f the PV array is zer. Vpv_Min is the minimum DC required t match the inverter utput vltage with the transfrmer secndary vltage. In this system, 620 V is the minimum DC link vltage required, as shwn in Table 2. In this case, if the battery vltage is als less than the nminal battery vltage Vb_Nminal then the system is in Mde3. In this mde, the battery needs t be charged but the PV array cannt prvide any pwer fr battery charging, s the grid shall supply the pwer required fr battery charging. In this mde f peratin, the inverter acts like a simple dide rectifier t prvide DC input t the battery charger. Based n the SOC f battery, the reference battery charging current I_Batt_Ref is btained. If the PV vltage (Vpv) is higherthanthe minimum PV vltage (Vpv_Min) then the cntrller tracks the MPP f the PV array by mnitring the PV vltage and current. In case the MPP is higher than minimum value i.e., P_PV_Min then the system is in Mde1. In this mde f peratin, the battery will be in charging state and the PV array prvides the pwer fr battery charging. The remaining pwer after battery charging will be transferred t the grid.

12 2016, 9, f 22 Based n the SOC f the battery, the reference battery charging current I_Batt_Ref is btained. Thrugh the pwer balancing equatin, the inverter reference current Id_Inv_Ref is calculated based n the MPP and battery current: Inverter pwer reference = MPP battery pwer reference (the battery Pwer reference is psitive during charging mde and negative in discharging mde) Inverter Pwer Reference = MPP (I_Batt_ref * V_Battery) 3 * Vabc_rms * Iabc_rms_Ref = MPP (I_Batt_ref * V_Battery) where Vabc_rms is the RMS value f line vltage f the grid/inverter and Iabc_rms_ref is the reference RMS value f line current f the inverter Iabc_rms_ref = (MPP [I_Batt_ref * V_Battery])/( 3 * Vabc_rms) Id_Inv_Ref can be calculated thrugh the abc t dq transfrmatin. Since in this system Iq_reference is always maintained at zer, the magnitude f Id_Inv_Ref can als be btained as given belw: Id_Inv_Ref = 2 * Iabc_rms_ref Id_Inv_Ref = 2 * (MPP [I_Batt_ref * V_Battery])/( 3 * Vabc_rms) If the MPP is less than the minimum value (P_PV_Min) but the battery is in charged cnditin then the system is in Mde2. In this case based n the backup time adjusted by the user, the reference battery current I_Batt_ref is calculated. In case the backup time adjusted by the user is 6 h, then the battery current reference is calculated as fllws: I_Batt_ref = rated Amp-hur rating f the battery/backup time I_Batt_ref = 288 Ah/6 h = 48 A Thrugh the pwer balancing equatin, the inverter reference current Id_Inv_Ref is calculated based n the MPP and battery current: Id_Inv_Ref = 2 * (MPP [I_Batt_ref * V_Battery])/( 3 * Vabc_rms) When the PV vltage is mre than the minimum DC link vltage, then the battery charger is perated with clsed lp current cntrl t maintain I_Batt = I_Batt_Ref. When the PV vltage is less than the minimum DC link vltage then the battery charger perates with clsed lp vltage cntrl t maintain a cnstant DC link vltage i.e., Vdc_Link = Vdc_Link_Ref. (4) After determining the battery reference current I_Batt_Ref and inverter reference current Id_Inv_ref, the cntrller implements the clsed lp current cntrl thrugh PI cntrllers and releases the gate pulses t the inverter stack and battery charger stack. The prpsed algrithm was tested n the real cntrller with the help f Hardware-In-Lp simulatins. The need fr HIL simulatins, features f the real-time digital simulatr and the setup built fr HIL simulatin fr the prpsed cnfiguratin are explained in the next sectins.

13 2016, 9, f 22 Figure 6. Algrithm fr pwer balancing cntrl f grid energy strage system in pht vltaic applicatins. 4. Hardware-in-the-Lp Simulatin Setup fr the Prpsed System

14 2016, 9, f 22 In general, cntrller and cntrl sftware are validated by integrating the cntrller with actual plant hardware. Hwever, in the case f any errr in the cntrl system, there are risks f persnal injuries, damage t the equipment and delays. Hardware-in-the-Lp (HIL) simulatin is a useful tl t avid such issues. In HIL simulatin, instead f a real plant a mathematical mdel representing the plant laded in the real-time simulatr t act like an actual plant. Thrugh HIL simulatins, the respnse f a cntrller in real time peratin can be validated [19]. The fllwing are the advantages with the HIL simulatin: (a) prttype cntrller sftware can be develped with minr assumptins abut the plant parameters; (b) nce the cntrl parameters are calculated with the HIL simulatin, it is easy t tune the parameters f the actual system; (c) it saves design cst and time (d) system prtectins in real time can be analyzed by simulating faults. T validate the cntrl sftware fr the prpsed system, HIL simulatins were carried ut. A plant cnsisting f a PV array, inverter, battery charger, islatin transfrmers, grid, battery and cntactrs was simulated using the Matlab- Simulink sftware. The simulated mdel is cmpiled and laded int the prcessr f a real-time digital simulatr (RTDS). The simulated plant can be accessed by the external cntrller cards and ther hardware thrugh the I/O channels available in the RTDS. The DSP-based cntrller is cnnected as hardware in the lp as shwn in Figure 7. Figure 7. Blck diagram fr hardware-in-the-lp simulatin f the prpsed grid energy strage system. The RTDS used fr the HIL simulatins is the Opal-RT Simulatr and the cntrller hardware is based n a Texas Instruments TMS320F2812 DSP-based cntrller card. The user interface panel cnsisting f pushbuttns and ptentimeters (POT) is used fr user cmmands and fr simulating the faults. Figure 8 shws the hardware setup fr the HIL simulatins.

15 2016, 9, f 22 Figure 8. Hardware-in-the-lp simulatin setup fr the prpsed grid energy strage system fr pht vltaic applicatins Input-Output Channels f Real-Time Digital Simulatr The Opal-RT RTDS is equipped with analg and digital input-utput mdules. The vltage range fr analg signals is ±15 V whereas the vltage levels fr digital signals is 0 and +15 V Input-Output Channels f Cntrller Card The cntrller used in this wrk is a TMS320F2812 DSP prcessr-based cntrller card. The vltage range fr analg signals is ±10 V whereas the vltage levels fr digital signals is 0 and +15 V User Interface Panel Signals The input t the simulated PV array is slar irradiance, which can be prvided t the simulated plant thrugh the analg input channel f RTDS frm a POT munted n a user interface panel. The minimum value f the POT utput refers t an irradiance f 0 and the maximum value f the POT refers t 1000 W/m 2. Frm the user interface panel, start/stp cmmands, and emergency stp cmmands are given t the cntrller card fr the plant peratins. The cntrller card receives temperature signals f frm the islatin transfrmers and pwer stacks frm the user interface panel. The pssible fault signals are als sent t the cntrller card hence different faults can be simulated t check the functinality f the cntrller and cntrl algrithm Signals frm Simulated Plant t Cntrller The cntrller receives the analg signals f the plant thrugh the analg utput channels f the RTDS. The cntrller receives PV vltage and current signals which are required fr tracking MPP. Battery vltage is required fr finding ut the charging current reference and battery current signal is required fr clsed lp current cntrl f the battery charger. Three phase grid vltage signals are required fr the PLL and inverter side vltages are mnitred fr synchrnizatin purpses. Three phase inverter currents are required fr the clsed lp current cntrl f the PV inverter. Based n the start-stp cmmands received frm the user interface panel, the cntrller gives the ON/OFF cmmands t the PV switch, grid switch and battery switches thrugh the digital input channels f RTDS. Switch status utputs t the cntrller are given t the cntrller thrugh the digital utput channels f the RTDS Online Plant Parameter Mdificatins Online mdificatin f simulated plant parameters i.e., transfrmer parameters, filter parameters, battery SOC, DC link capacitr values and lad parameters, etc. during the real-time digital simulatin is als pssible thrugh RT lab main cntrller. Thrugh nline mdificatins, the ptimum values f the plant cmpnents can als be btained. 5. Results and Discussins 5.1. Inverter, Grid and Lad Currents in Different Mdes f Operatin Figure 9 shws the current wavefrms in Mde1 f peratin. Since the PV array can prduce mre than the minimum pwer required fr charging the battery and feeding the internal lads cnnected t the plant, the additinal pwer prduced by the PV array is supplied t the grid. An irradiance f 1000 W/m 2 is adjusted n the user interface panel, hence the PV array is prducing the maximum pssible pwer. Frm the presented result, it can be bserved that the grid current is phase displaced by 180 degree with respect t the inverter current.

16 2016, 9, f 22 Figure 9. Currents f inverter, grid, lad, and vltage at PCC in Mde1 f peratin. In Mde2 f peratin, an irradiance f 0 W/m 2 is adjusted n the user interface panel; hence the PV array cannt prduce any pwer. The battery is in charged cnditin and supplies the pwer t the lad based n the Amp-hur rating f the battery and the discharging time r backup time adjusted by the user. Since the lcal lads cnsume mre than the inverter supplied current, the remaining current is drawn frm the grid as shwn in Figure 10. Since the lad is drawing current frm bth the surces, the grid current and the inverter current are in phase with each ther. Figure 10. Currents f inverter, grid, lad, andvltage at PCC in Mde2 f peratin.

17 2016, 9, f 22 In Mde3 Operatin, the PV array cannt prduce any pwer and the battery is in discharged cnditin. Since the battery is t be charged, the grid supplies the necessary charging current t the battery and the current required fr the lcal lads as shwn in Figure 11. Figure 11. Currents f inverter, grid, lad, and vltage at PCC in Mde3 f peratin. The dynamic respnse f the system t a step change in inverter reference pwer is shwn in Figure 12. Figure 12. Currents f inverter, grid, lad fr a step change in reference pwer.

18 2016, 9, f 22 When the inverter pwer reference is mre than the lcal lad requirement then the inverter is supplying current t grid and lad. Since the grid is receiving the current, the phase displacement between grid and inverter currents is 180 degrees. After a step change in the reference pwer, since the reference pwer is less than the lad requirement, the lad current is supplied frm bth the inverter and the grid, hence the bth the currents are in phase with each ther. With the present cntrls, the system reaches the steady state within ne cycle time Battery Charger Input and Output Currents in Different Mdes f Operatin Battery current is cnsidered as psitive during charging and negative during discharging f the battery. The battery will be in charged cnditin in Mde1 and Mde3 f peratins as explained earlier. During charging, depending n the SOC f the battery, the charging current reference is btained and the cntrller carries the clsed lp current cntrl f the battery charger. The battery charger input and utput currents fr different mdes f peratin are discussed belw. In Mde1 peratin, since the battery is in charging cnditin, battery current and the average value f battery charger input current are psitive, as shwn in Figure 13. Figure 13. Battery charger input and utput currents in mde1 peratin. In Mde2 f peratin, when the PV array vltage is less than the minimum DC link vltage then the battery charger perates with clsed lp vltage cntrl and maintains a cnstant DC link vltage. The current thrugh the battery depends n the Id Reference f the inverter which is btained thrugh the Amp-hur rating f the battery and the backup time required fr the user. Since the battery is in discharging cnditin, battery current and the average value f the battery charger input current are negative, as shwn in Figure 14.

19 2016, 9, f 22 Figure 14. Battery charger input and utput currents in mde-2 peratin. Similar t Mde1, in Mde3 peratin battery current and the average value f the battery charger input current are als psitive as shwn in Figure 15. The charging current required fr the battery is prvided frm the grid supply in this case. Battery Charger Input Current Battery Current Figure 15. Battery charger input and utput currents in mde3 peratin. The dynamic respnse f the battery charger system is bserved by applying a step change in the battery current reference. The system takes apprximately 250 millisecnds t cme t the steady state as shwn in Figure 16.

20 2016, 9, f 22 Figure 16. Battery charger reference and actual currents fr a step change in reference current. 6. Future Scpe The results presented in this paper are btained thrugh real-time digital simulatins. A scaled dwn mdel f the plant i.e., pwer circuit can als be made t test the cntrller and cntrl algrithm. A predictive diagnstic in high-pwer transfrmers used in tractin grade uninterruptible pwer supplies is presented in [20]. In similar lines, predictive diagnsis f the system cmpnents in a grid energy strage system can als be addressed as future wrk. The presented system can als be extended fr smart grid applicatins by incrprating additinal energy surces alng with the PV and battery, then as future wrk, the security and privacy prblems in this smart grid can be addressed, as discussed in [21]. In this paper, design and cntrl f grid energy strage system with a cnventinal PV inverter is explained in detail. Additinal feature reactive pwer cmpensatin can be incrprated t make the system wrk as PV-STATCOM. This system can als be extended fr high pwer applicatins by using multilevel cnfiguratins fr the PV inverter [22 23]. 7. Cnclusins In this paper, a pwer balancing cntrl fr a grid energy strage system is presented. The PBC technique is implemented n a TMS320F2812 prcessr-based cntrller card and tested. Dynamic respnses f the inverter and battery charger system are verified by applying a step change in the reference values. Frm the presented HIL results, it is bserved that the perfrmance f PBC cntrl is satisfactry in all three mdes f peratin and gd dynamic perfrmance is als achieved using this technique. As the cntrls are tested thrugh HIL simulatins in this wrk, plant parameters are cnsidered as ideal whereas the plant parameters vary with perating temperatures in real time peratin. Hence, minr mdificatins in plant parameters and tuning f cntrl parameters are required t implement the prpsal n areal system. The same system can be extended further t have the feature f reactive pwer cmpensatin thrugh the mdified PBC cntrl. Acknwledgments: N funding resurces Authr Cntributins: Sridhar Vavilapalli, Sanjeevikumar Padmanaban, Umashankar Subramaniam had develped the riginally prpsed research wrk and implemented with numerical simulatin sftware and real time RTDS system fr investigatin and perfrmance validatin. Sanjeevikumar Padmanaban, Umashankar Subramaniam, Lucian Mihet-Ppa cntributed their expertise in the prpsed subject f research and

21 2016, 9, f 22 verificatin f the btained results based n theretical cncepts and insight backgrund. All authrs invlved t articulate the research wrk fr its final depictin as a research paper. Cnflicts f Interest: The authrs declare n cnflict f interest. References 1. Mihet-Ppa, L.; Bindner, H. Simulatin mdels develped fr vltage cntrl in a distributin netwrk using energy strage systems fr PV penetratin. In Prceedings f the 39th Annual Cnference f the IEEE Industrial Electrnics Sciety IECON 13, Vienna, Austria, Nvember 2013; pp El Khateb, A.; Rahim, N.A.; Selvaraj, J. Ćuk-Buck Cnverter fr Standalne Phtvltaic System. J. Clean Energy Technl.2013, 1, Wu, T.; Xia, Q.; Wu, L.; Zhang, J.; Wang, M. Study and implementatin n batteries charging methd f Micr-Grid phtvltaic systems. Smart Grid Renew. Energy 2011, 204, Chi, H.; Jang, M.; Cibtaru, M.; Agelidis, V.G. Hybrid energy strage fr large PV systems using bidirectinal high-gain cnverters. In Prceedings f the 2016 IEEE Internatinal Cnference n Industrial Technlgy (ICIT), Taipei, Taiwan, March 2016; pp Shi, Y.; Li, R.; Xue, Y.; Li, H. Optimized peratin f current-fed dual active bridge DC DC cnverter fr PV applicatins. IEEE Trans. Ind. Electrn. 2015, 62, Bharathi, K.; Sasikumar, M. Vltage Cmpensatin f Smart Grid using Bidirectinal Intelligent Semicnductr Transfrmer and PV Cell. Indian J. Sci. Technl.2016, 9, Mihet-Ppa, L.; Kch-Cibtaru, C.; Isleifssn, F.; Bindner, H. Develpment f tls fr DER Cmpnents in a distributin netwrk. In Prceedings f the 2012 XXth Internatinal Cnference n Electrical Machines (ICEM), Marseille, France, 2 5 September 2012; pp Chen, M.; Rincn-Mra, G.A. Accurate electrical battery mdel capable f predicting runtime and I-V perfrmance. IEEE Trans. Energy Cnvers. 2006, 21, MathWrks. Available nline: jsessinid= f c734b7a8e92d (accessed n 15 June 2017). 10. Kch-Cibtaru, C.; Mihet-Ppa, L.; Isleifssn, F.; Bindner, H. Simulatin Mdel develped fr a Small- Scale PV-System in a Distributin Netwrk. In Prceedings f the 7th Internatinal Sympsium n Applied Cmputatinal Intelligence and Infrmatics IEEE SACI 2012, Timisara, Rmania, May 2012; pp Rahman, S.A.; Varma, R.K.; Vanderheide, T. Generalised mdel f a phtvltaic panel. IET Renew. Pwer Gener. 2014, 8, Jeng, D.K.; Kim, H.S.; Baek, J.W.; Kim, J.Y.; Kim, H.J. Dual active bridge cnverter fr Energy Strage System in DC micrgrid. In Prceedings f the 2016 IEEE Cnference and Exp Transprtatin Electrificatin Asia-Pacific (ITEC Asia-Pacific), Busan, Krea, 1 4 June 2016; pp Dutta, S.; Hazra, S.; Bhattacharya, S. A Digital Predictive Current-Mde Cntrller fr a Single-Phase High- Frequency Transfrmer-Islated Dual-Active Bridge DC-t-DC Cnverter. IEEE Trans. Ind. Electrn. 2016, 63, Kumar, N.; Saha, T.K.; Dey, J. Sliding-mde cntrl f PWM dual inverter-based grid-cnnected PV system: Mdeling and perfrmance analysis. IEEE J. Emerg. Sel. Tp. Pwer Electrn. 2016, 4, Tdeji, H.; Farkhnia, N.; Riahy, G.H. Integratin f PV mdule and STATCOM t extract maximum pwer frm PV. In Prceedings f the Internatinal Cnference n Electric Pwer and Energy Cnversin Systems, Sharjah, UAE, Nvember 2009; pp Serban, E.; Ordnez, M.; Pndiche, C.; Feng, K.; Anun, M.; Servati, P. Pwer management cntrl strategy in phtvltaic and energy strage fr ff-grid pwer systems. In Prceedings f the 2016 IEEE 7th Internatinal Sympsium n Pwer Electrnics fr Distributed Generatin Systems (PEDG), Vancuver, BC, Canada, June 2016; pp Sikkabut, S.; Mungprn, P.; Ekkaravardme, C.; Bizn, N.; Tricli, P.; Nahid-Mbarakeh, B.; Thunthng, P. Cntrl f High-Energy High-Pwer Densities Strage Devices by Li-in Battery and Supercapacitr fr Fuel Cell/Phtvltaic Hybrid Pwer Plant fr Autnmus System Applicatins. IEEE Trans. Ind. Appl. 2016, 52, Merabet, A.; Ahmed, K.T.; Ibrahim, H.; Beguenane, R.; Ghias, A.M. Energy Management and Cntrl System fr Labratry Scale Micrgrid Based Wind-PV-Battery. IEEE Trans. Sustain. Energy 2017, 8,

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