Spartan-3 / 3E / UMC-12A 90 nm

Transcription

1 Spartan-3 / 3E / UMC-12A 90 nm Qualification Report RPT012 (v2.0.2) October 7, 2009 R

2 R Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the Documentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information. THE DOCUMENTATION IS DISCLOSED TO YOU AS-IS WITH NO WARRANTY OF ANY KIND. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DOCUMENTATION, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NONINFRINGEMENT OF THIRD-PARTY RIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOSS OF DATA OR LOST PROFITS, ARISING FROM YOUR USE OF THE DOCUMENTATION Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. Spartan-3 / 3E / UMC-12A 90 nm RPT012 (v2.0.2) October 7, 2009

3 Revision History Spartan-3 / 3E / UMC-12A 90 nm, RPT012 (v2.0.2) October 7, 2009 The following table shows the revision history for this document. Version Revision 05/05/ Initial Xilinx release. 08/05/ Added Phase II Production data 12/14/ Added Spartan-3E FPGA information 03/06/ Updated wear out table. 01/26/ Updated Mask Qualification Summary (Table 5). 03/16/ Changes to Table 4. 07/15/ Typographical errors corrected. 08/24/ Added a fourth and changed other footnotes in Table /07/ Replaced Table 26 and Figure 1, Figure 2, Figure 3, and Figure 4. 02/04/ Typographical errors corrected. 10/07/ Typographical updates. Spartan-3 / 3E / UMC-12A 90 nm RPT012 (v2.0.2) October 7, 2009

4 Spartan-3 / 3E / UMC-12A 90 nm RPT012 (v2.0.2) October 7, 2009

5 Table of Contents Overview Executive Summary Product Qualification Requirement and Phase Engineering Sample (ES) Phase I Production Release Phase II Production Release Process Attributes Product/Package Matrix Qualification Summary Generic Process Qualification Mask Qualification Summary Package Qualification Summary Appendix Life and Environmental Stress Data Wear Out Data Drift Analysis Spartan-3 / 3E / UMC-12A 90 nm RPT012 (v2.0.2) October 7, 2009

6 Spartan-3 / 3E / UMC-12A 90 nm RPT012 (v2.0.2) October 7, 2009

7 R Spartan-3 / 3E / UMC-12A 90 nm Overview Executive Summary This report presents general process qualification data for the 90 nm Spartan -3 and Spartan-3E families, mask qualification for the individual Spartan-3 and Spartan-3E devices, package qualification data for FG320, FG1156, and Pb-free package qualification data for Spartan-3 and Spartan-3E packages. Product high-temperature operating life (HTOL) test successfully completed 1,000 hours and 7 lots completed 2,000 hours. Based on the HTOL data, 22 FIT failure rate at junction temperature (TJ) of 55 C and 60% confidence level (C.L.) was demonstrated. The technology wear-out data demonstrate the production lifetime, meeting minimum 10-year lifetime requirement at 100 C or 20-year lifetime requirement at 85 C. Based on the data available to date, all of the Spartan-3 and Spartan-3E FPGA products/packages listed in the following table have been released to Phase-II production. Table 1: Phase 2 Production Devices Device 3S50 3S200 3S400 3S1000 3S1500 3S2000 3S4000 3S5000 3S100E 3S250E 3S500E Package CP132, VQ100, TQ144, PQ208 VQ100, TQ144, PQ208, FT256 TQ144, PQ208, FT256, FG320, FG456 FT256, FG320, FG456, FG676 FG320, FG456, FG676 FG456, FG676, FG900 FG676, FG900, FG1156 FG900, FG1156 VQ100, TQ144 VQ100, TQ144, CP132, PQ208, FT256 CP132, PQ208, FT256, FG320 Spartan-3 / 3E / UMC-12A 90 nm RPT012 (v2.0.2) October 7,

8 Product Qualification Requirement and Phase R Table 1: Phase 2 Production Devices (Cont d) Device Package 3S1200E FT256, FG320, FG400 3S1600E FG320, FG400, FG484 Table 2: Phase 2 Lead-Free Production Devices Device Lead-Free Package 3S50 CPG132, VQG100, TQG144, PQG208 3S200 VQG100, TQG144, PQG208, FTG256 3S400 TQG144, PQG208, FTG256, FGG320, FGG456 3S1000 FTG256, FGG320, FGG456, FGG676 3S1500 FGG320, FGG456, FGG676 3S2000 FGG456, FGG676, FGG900 3S4000 FGG676, FGG900, FGG1156 3S5000 FGG900, FGG1156 3S100E VQG100, TQG144 3S250E VQG100, TQG144, CPG132, PQG208, FTG256 3S500E CPG132, PQG208, FTG256, FGG320 3S1200E FTG256, FGG320, FGG400 3S1600E FGG320, FGG400, FGG484 Product Qualification Requirement and Phase As a new process and new product are introduced, a full set of reliability stress and wearout tests (process qualification) are applied for reliability qualification. After the process qualifies, the qualification for other additional devices from the same product family is reduced to ESD and latch-up tests (mask qualification). Similarly, as a new package is introduced, a full set of environmental stress tests is applied for reliability qualification (package qualification). For the existing qualified packages, only the die package interaction (DPI) qualification test, temperature cycling, is required. Engineering Sample (ES) Before a product is fully qualified, an engineering sample is available to meet customers' design-in and prototyping needs and to provide early application feedback. Products at the ES stage are considered medium risk and should not be used for customer end product qualification. There can also be limitations (errata) associated with ES products that customers should be made aware of. 8 RPT012 (v2.0.2) October 7, Spartan-3 / 3E / UMC-12A 90 nm

9 R Process Attributes Phase I Production Release Products at Phase I production release are considered low risk. Manufacturing volume is generally ramped at this time. Although not all of the qualification testing may be completed, there is sufficient data to indicate that the product can meet customer application needs with low risk. Decreased risk and, therefore, increased confidence in the product's health, is paralleled by increases in production shipments. HTOL data demonstrate failure rate 200 FIT Wear-out test complete on 1 lot and meeting minimum 10-year requirement Pass 1,000 temperature cycles Phase II Production Release Process Attributes Pass 500 hours of other environmental tests A product reaches Phase II Production Release when all assessments have been completed and formal risk assessment shows that all risks are negligible. This means that sufficient data exists to demonstrate that the product meets the production qualification requirements of each of the validation plans. Closure of all corrective actions is complete or imminent and validated adequately. Product will perform as designed in customers' use environments. The product responsibilities are transferable to sustaining or manufacturing engineering. HTOL data demonstrate failure rate 50 FIT Wear-out test complete on 3 lots and meeting minimum 10-year requirement Complete and pass environmental tests Wafer Fab Location UMC 12A, 300 mm, Tainan, Taiwan Process Technology 90 nm 1P8M CMOS logic process Dual gate oxide 7 layers copper for Spartan-3 devices, 8 layers of copper for Spartan-3E devices FSG inter metal dielectric (IMD) 1 layer aluminum for bond pad and redistribution layer (RDL) Package All wire bond package Both Pb and Pb-Free packages Assembly at Silicon Precision Industries (SPIL), Taiwan Amkor for FG(G)320 & CP(G)132 Spartan-3 / 3E / UMC-12A 90 nm RPT012 (v2.0.2) October 7,

10 Product/Package Matrix R Product/Package Matrix Device 3S50 3S200 3S400 3S1000 3S1500 3S2000 3S4000 3S5000 CP132 VQ100 TQ144 PQ208 FT256 FG320 FG456 FG676 FG900 FG1156 Process Qual Process Qual Process Qual TCB & TH Process & Pack Qual TC TCB & TH = by extension = actual test done Device 3S50 3S200 3S400 3S1000 3S1500 3S2000 3S4000 3S5000 CPG132 HTS, TC VQG100 TC TQG144 PQG208 FTG256 FGG320 TC, TH TC, TH FGG456 FGG676 FGG900 FGG1156 TC, HTS, TH TC = by extension = actual test done 10 RPT012 (v2.0.2) October 7, Spartan-3 / 3E / UMC-12A 90 nm

11 R Qualification Summary Device 3S100E 3S250E 3S500E 3S1200E 3S1600E VQG100 TC TC TQG144 CPG132 TC, HTS, TH, THB PQG208 FTG256 FGG320 TC FGG400 FGG484 = by extension = actual test done Qualification Summary Generic Process Qualification Product Stress Test Summary Table 3: Product Stress Test Summary Test Conditions Test Vehicles Lot Qty Cumulative Device-Hr/Cyc # of Failures 3S HTOL (Static/Dynamic) Ta = 125 C, V CCMAX 3S1500 3S ,391,197 2 (3) (22 FIT) (2) 3S HTS Ta = 150 C 3S ,729 0 THB (1) 85 C, 85%RH, Bias V CCMAX 3S ,216 0 TH w/o B (1) 85 C, 85%RH 3S ,076 0 TC-B (1) -55 C/+125 C 3S ,140 0 Notes: 1. Level-3 reconditioning applied to THB, TH and TC samples prior to the stress tests. 2. The failure rate is calculated based on 0.7 ev, Tj of 55 C and 60% C.L. 3. Basic Functional V CC sensitive (soft) 1000 hrs, FA results - no defect found; 1 Basic Functional (soft) 61 hrs, HTOL continued to 2000 hrs & electrical signature not changed. Spartan-3 / 3E / UMC-12A 90 nm RPT012 (v2.0.2) October 7,

12 Qualification Summary R Wear Out Test Summary Table 4: Wear Out Test Summary Mechanism Sample Size Conditions of Stress Test Conditions of Quoted Results Failure Criterion Comments Product C Product C Product C Hot Carrier Injection 20 per condition 3 Voltages, 25 C 1.05 V CC, 125 C for Core, -55 C for IO NMOS ΔIdsat > 10% Worst at cold for IO NMOS & hot for others 150 yrs for IO PMOS 141 yrs for IO PMOS 129 yrs for IO PMOS Vt stability 10 per condition C 1.05 V CC 100 mv for Core Oxide; 110 mv for 2.5V device; 200 mv for 3.3V device Verified by product HTOL 216 yrs 95 yrs 18 yrs Gate Oxide TDDB 20 per condition 3 Voltages/ 3 temp., 100 to 160 C 1.05 V CC Ign/Ign-1 >1.2 for Core NMOS & 2 for Core PMOS, >10 for IO CDF = 0.1% Equivalent to 11 FIT s after 10 years 49 yrs for 3S yrs for 3S yrs for 3S5000 Electromigration per condition 250 to 350 C design rule J use ΔR/R>20% CDF = 100 PPM Equivalent to 1 FIT s after 10 years 105 yrs 34 yrs 6 yrs VRDB Total test areas > 0.2cm 2 for area; > 1E3cm for STI edge; > 1E4cm for poly edge Voltage C DD Ign/Ign-1 >1.2 for core, >10 for IO B mode 1.1V CC < VBD < pass pass pass 2.3V CC 12 RPT012 (v2.0.2) October 7, Spartan-3 / 3E / UMC-12A 90 nm

13 R Qualification Summary Table 4: Wear Out Test Summary (Cont d) Mechanism Sample Size Conditions of Stress Test Conditions of Quoted Results Failure Criterion Comments Product C Product C Product C SM per condition 3 Temperatures 1,000 hrs pass or fail ΔR/R > 20% or EDR for single via; ΔR/R > 2.5% for Via Chains No sample stress fail allowed pass pass pass BEOL TDDB per condition C 1.1V CC line to line leakage > 1μA CDF=0.01 % Equivalent to 1 FIT s after 10 years 795 yrs 646 yrs 214 yrs Mask Qualification Summary The Latch-Up, HBM, and CDM tests are performed according to the following industrial standard specifications Latch-Up: JESD-78, ± 200mA and 1.5 x V DD at 125 C. HBM: JESD-22-A114, ESDA STM5.1 CDM: JESD-22-A115, ESDA STM5.3.1 MM: EIA/JESD22-A115-A Table 5: Mask Qualification Summary Device Latch-Up HBM Passing Voltage CDM Passing Voltage MM Passing Voltage Package XC3S50 Pass +/-2,000V (1) +/-500V +/- 200V PQ208 XC3S200 Pass +/-2,000V +/-500V +/- 200V PQ208, FT256 (2) XC3S400 Pass +/-2,000V +/-500V +/- 200V PQ208, FG456 (2) XC3S1000 Pass +/-2,000V +/-500V +/- 200V PQ208, FG676 (2) XC3S1500 Pass +/-2,000V +/-500V +/- 200V FG456 XC3S2000 Pass +/-2,000V +/-500V +/- 200V PQ208, FG900 (2) XC3S4000 Pass +/-2,000V +/-500V +/- 200V FG900, FG1156 (2) XC3S5000 Pass +/-2,000V +/-500V +/- 200V FG1156 XC3S100E Pass +/-2,000V +/-500V +/- 200V PQ208, TQ144 XC3S250E Pass +/-2,000V +/-500V +/- 200V PQ208, FT256 XC3S500E Pass +/-2,000V +/-500V +/- 200V PQ208, FG320 XC3S1200E Pass +/-2,000V +/-500V +/- 200V FG320 Spartan-3 / 3E / UMC-12A 90 nm RPT012 (v2.0.2) October 7,

14 Qualification Summary R Table 5: Mask Qualification Summary (Cont d) Device Latch-Up HBM Passing Voltage CDM Passing Voltage MM Passing Voltage Package XC3S1600E Pass +/-2,000V +/-500V +/- 200V FG484 Notes: 1. The HBM passing voltage for XC3S50 has been revised from the previous 1500V to 2000V when No Connect (NC) pins are not tested per JEDEC 22A114D and ESD Association bulletin. 2. These packages were tested for CDM only and passed. Package Qualification Summary Table 6: FG1156 Package Qualification Summary Test Conditions Device SS Duration Hrs/Cycles # of Failures TC-B -55 to +125 C XC3S ,000 0 TH 85 C, 85%RH, V DDMAX XC3S ,000 0 Table 7: FG320 Package Qualification Summary Test Conditions Device SS Duration Hrs/Cycles # of Failures TC-B -55 to +125 C XC3S ,500 0 TH 85 C, 85%RH, V DDMAX XC3S ,000 0 Table 8: FG900 Package Qualification Summary Test Conditions Device SS Duration Hrs/Cycles # of Failures TC-B -55 to +125 C XC3S ,000 0 Table 9: CPG132 Package Qualification Summary Test Conditions Device SS Duration Hrs/Cycles # of Failures TCB -55 to 125 C XC3S ,000 0 HTS 150 o C XC3S TCB -55 o C to 125 o C XC3S500E HTS 150 o C XC3S500E RPT012 (v2.0.2) October 7, Spartan-3 / 3E / UMC-12A 90 nm

15 R Qualification Summary Table 9: CPG132 Package Qualification Summary (Cont d) Test Conditions Device SS Duration Hrs/Cycles # of Failures TH 85 o C,85%RH XC3S500E THB 85 o C,85%RH XC3S500E Table 10: FGG1156 Package Qualification Summary Test Conditions Device SS Duration Hrs/Cycles # of Failures TCB -55 to 125 C XC3S ,000 0 HTS 150 C XC3S ,000 0 TH 85 C, 85%RH XC3S ,000 0 TCB -55 to 125 C XC3S ,000 0 Table 11: FGG320 Package Qualification Summary Test Conditions Device SS Duration Hrs/Cycles # of Failures TCB -55 to 125 C XC3S ,000 0 TCB -55 to 125 C XC3S ,000 0 TH 85 C, 85%RH XC3S ,000 0 TH 85 C, 85%RH XC3S ,000 0 TCB -55 o C to 125 o C XC3S1600E 77 1,000 0 Table 12: PQ208 Package Qualification Summary Test Conditions Device SS Duration Hrs/Cycles # of Failures TCB -55 to 125 C XC2S200E 76 1,000 0 TH 85 C, 85%RH XC2S200E 76 1,000 0 HTS 150 C XC2S200E 32 1,000 0 Table 13: TQG144 Package Qualification Summary Test Conditions Device SS Duration Hrs/Cycles # of Failures TCC -65 C to 150 C XC2S50E 38 1,000 0 TH 85 C, 85%RH XC2S50E 76 1,000 0 Spartan-3 / 3E / UMC-12A 90 nm RPT012 (v2.0.2) October 7,

16 Qualification Summary R Table 14: VQG100 Package Qualification Summary Test Conditions Device SS Duration Hrs/Cycles # of Failures TCB -55 C to 125 C XC3S ,000 0 TCB -55 C to 125 C XC3S100E 82 2,000 0 TCB -55 C to 125 C XC3S250E 77 1, RPT012 (v2.0.2) October 7, Spartan-3 / 3E / UMC-12A 90 nm

17 R Appendix Appendix Life and Environmental Stress Data Table 15: Life and Environmental Stress Data Test Conditions Device Package SS Duration (hrs) # of Failures Cumulative Hours 3S1500 FG ,000 1 (2) 3S1500 FG , S1500 PQ , S1500 FG , S1500 PQ ,500 0 HTOL Ta = 125 C, V CCMAX, Static or Dynamic (4) 3S1500 FG , S1500 FG , S1500 FG , S1500 PQ ,391,197 3S2000 PQ , S4000 PQ ,500 1 (3) 3S1000 (4) PQ , S1000 (4) FG , S1000 (4) FG ,000 0 HTS Ta = 150 C 3S1500 FG , S1500 FG , ,729 3S1500 PQ ,678 0 THB (1) 85 C, 85%RH, Bias V CCMAX TH w/o B (1) 85 C, 85%RH TC-B (1) -55 C/ +125 C 3S1500 PQ , S1500 PQ , S1500 PQ , S1500 FG , S1500 FG , S1500 FG , S1500 FG , , , ,140 Notes: 1. Level-3 preconditioning applied to THB, TH, and TC samples prior to the stress tests. 2. Basic Functional V CC sensitive (soft) 1,000 hours, FA results no defect found. 3. Basic Functional (soft) 61 hours, HTOL continued to 2,000 hrs and electrical signature not changed. 4. HTOL test was done in dynamic. Spartan-3 / 3E / UMC-12A 90 nm RPT012 (v2.0.2) October 7,

18 Appendix R Wear Out Data Hot Carrier Injection Table 16: Wear Out Data, Hot Carrier Injection Transistor Device Type Lot Tox (A) NMOS PMOS 1.2V NMOS 1.2V NMOS low Vt 2.5V NMOS KN1 KP013 KN350 KN1 KP013 KN350 KN1 KP013 KN350 Negative Bias Temperature Instability Worst Conditions V; 125 C V; 125 C V; -40 C Lifetime (yrs) 4.51E E E E E E E E E V NMOS KN V; -40 C 8.61E V PMOS 2.5V PMOS KN1 KP013 KN350 KN1 KP013 KN350 Table 17: Wear Out Data, Negative Bias Temperature Instability V; 125 C V; 125 C 6.42E E E E E E V PMOS KN V; 125 C 1.29E+02 PMOS Lot Tox (A) Worst Conditions 1.2V PMOS 2.5V PMOS KN1 KP013 KN350 KN1 KP013 KN V; 125 C V; 125 C Lifetime 125C 3.75E E E E E E V PMOS KR V; 125 C 3.19E RPT012 (v2.0.2) October 7, Spartan-3 / 3E / UMC-12A 90 nm

19 R Appendix Gate Oxide TDDB Weibull Distribution: CDF = 1 - exp [-(t / to) m ] For thin oxide (16A core), power law model: to = Co V -n exp(ea/kt) A -(1/m) Failure criterion: 1.2 x current change (soft breakdown) for NMOS & 2X for PMOS For thick oxide (52A I/O), E-field model: to = Co exp(-γ V) exp(ea/kt) A -(1/m) Failure criterion: 10x current change Table 18: Gate Oxide TDDB, Inversion Mode Test Items Tox Use Cond. Lot ID Qualification Results (yrs) Specification Pass/Fail Thin Oxide Nwell 16Å 1.32V, 125 C KN1 KP013 KP E E E+01 Thin Oxide Pwell 16Å 1.32V, 125 C KN1 KP013 KP E E E+02 Mid Oxide Nwell Mid Oxide Pwell 22Å 22Å 1.65V, 125 C 1.65V, 125 C KN1 KP013 KP KN1 KP013 KP E E E E E E+04 Lifetime > 10 yrs Pass Thick Oxide Nwell 52Å 3.45V, 125 C KN1 KP013 KP E E E+03 Thick Oxide Pwell 52Å 3.45V, 125 C KN1 KP013 KP E E E+02 Product's TDDB lifetime is limited by PFET core and the above TDDB lifetime is calculated based on gate oxide area of 10 mm 2 for core and 3 mm 2 for IO. Table 19 shows the detail TDDB lifetimes of each devices. Spartan-3 / 3E / UMC-12A 90 nm RPT012 (v2.0.2) October 7,

20 Appendix R Table 19: Detail of TDDB Lifetime in Years of Each Device Lifetime (yrs) XC3S XC3SE Lot Temp E 250E 500E 1200E 1600E 85 C KN1 100 C C C KP C C C KP C C Electromigration Black's Equation and lognormal distribution: MTTF = A J -n exp(ea/kt) Failure criterion: (R final -R initial )/R initial = 20%; Lifetime calculation with CDF=100 ppm Parameters: Ea = 0.87 ev, n = 1.1 Table 20: Electromigration Interconnect Structure Design Usage Lot ID CA/M1 CA/M1 (wide line) M1 Lifetime (yrs) C Sigma KSA KM KN KSA KM KN RPT012 (v2.0.2) October 7, Spartan-3 / 3E / UMC-12A 90 nm

21 R Appendix Table 20: Electromigration (Cont d) Interconnect Structure Design Usage Lot ID V1/M1 V1/M1 (wide line) V1/M2 V2/M2 V1/M2 (wide line) V2/M2 (wide line) V6/M7 V7/M7 V6/M7 (wide line) V7/M7 (wide line) 1X: M2 - M6 2X: M7, M8 Lifetime (yrs) C Sigma KSA KM KN KSA KM KN KN KSB46/ KP655/ KSB46/ KP655/ KSH34.02/ KN146.02/ KSB46/ KP655/ KSB46/ KP KSH KL KSA KM KL KSA KM KL KSA KM KL KSA KM Spartan-3 / 3E / UMC-12A 90 nm RPT012 (v2.0.2) October 7,

22 Appendix R Table 20: Electromigration (Cont d) Interconnect Structure Design Usage Lot ID V8/M9 M11/V10/M10 L1L2 4X: M9, M10 RDL Lifetime (yrs) C Sigma KL KSA KM KL KSA KM KL KSA KM RPT012 (v2.0.2) October 7, Spartan-3 / 3E / UMC-12A 90 nm

23 R Appendix Area/Edge Intensive Vbd (Breakdown Voltage for Gate Oxide Integrity) Table 21: Area/Edge Intensive Vbd (Breakdown Voltage for Gate Oxide Integrity) Area Intensive Test Items Lot ID Tox (Å) NW/SG PW/SG NW/MG PW/MG NW/TG PW/TG Qualification Results DD<2.97/cm 2 KQ DD<3.3/cm 2 KQ829 DD<3.3/cm 2 DD<2.96/cm 2 KQ DD<3.3/cm 2 KQ829 DD<3.3/cm 2 DD<1.59/cm 2 KQ DD<1.77/cm 2 KQ829 DD<1.77/cm 2 DD<1.59/cm 2 KQ DD<1.77/cm 2 KQ829 DD<1.77/cm 2 DD<1.59/cm 2 KQ DD<3.54/cm 2 KQ829 DD<1.77/cm 2 DD<1.59/cm 2 KQ DD<1.77/cm 2 KQ829 DD<1.77/cm 2 Specification DD< 5 /cm 2 Pass/Fail Pass Spartan-3 / 3E / UMC-12A 90 nm RPT012 (v2.0.2) October 7,

24 Appendix R Table 21: Area/Edge Intensive Vbd (Breakdown Voltage for Gate Oxide Integrity) (Cont d) Poly Edge Intensive Test Items Lot ID Tox (Å) NW/SG PW/SG NW/MG PW/MG NW/TG PW/TG KQ593 KQ829 KQ593 KQ829 KQ593 KQ829 KQ593 KQ829 KQ593 KQ829 KQ593 KQ Qualification Results DD<0.0001/cm DD<0.0001/cm DD< /cm DD< /cm DD<0.0001/cm DD<0.0001/cm DD< /cm DD< /cm Specification DD<0.0001/cm Pass/Fail Pass 24 RPT012 (v2.0.2) October 7, Spartan-3 / 3E / UMC-12A 90 nm

25 R Appendix Table 21: Area/Edge Intensive Vbd (Breakdown Voltage for Gate Oxide Integrity) (Cont d) STI Edge Intensive Test Items Lot ID Tox (Å) NW/SG PW/SG NW/MG PW/MG NW/TG PW/TG KQ593 KQ829 KQ593 KQ829 KQ593 KQ829 KQ593 KQ829 KQ593 KQ829 KQ593 KQ Qualification Results Specification DD<0.001/cm Pass/Fail Pass BEOL (Backend of line) TDDB at 100 C Table 22: Backend of line TDDB at 100 o C Test Items Lot ID Lifetime 100 o C KSA E+08 Intra-Level M1 KM E+06 KN E+02 KSA E+03 Intra-Level M2 KM E+03 KN E+02 KSA E+09 Intra-Level M7 KM E+09 KN E+10 Spartan-3 / 3E / UMC-12A 90 nm RPT012 (v2.0.2) October 7,

26 Appendix R Stress Migration Stress conditions: 175 o C, 225 o C, 275 o C, 500/1,000 hrs Test structures & failure criterion Via chain: (R final -R initial )/R initial = 2.5% 1K, 10K, stacked, plate, design variations Single via (Kelvin): Rf = design corner (EDR limit) Via at line edge vs. center Table 23: Stress Migration Test Items Lot ID Qualification Status Specification Pass/Fail Via Chain Stack Via Chain Single Via Plate Structure No 1,000 hrs No 1,000 hrs No 1,000 hrs No 1,000 hrs No 1,000 hrs No 1,000 hrs No 1,000 hrs No 1,000 hrs No 1,000 hrs No 1,000 hrs No 1,000 hrs No 1,000 hrs No sample fail is allowed Pass 26 RPT012 (v2.0.2) October 7, Spartan-3 / 3E / UMC-12A 90 nm

27 R Appendix Temperature Cycling Test under Stress Condition of -55 C to +150 C Table 24: Temperature Cycling Test under Stress Condition of -55 C to +150 C Test Items Lot ID Qualification Status Specification Pass/Fail Via Chain Stack Via Chain Single Via Plate Structure No fail after 500 cycles No fail after 500 cycles No fail after 500 cycles No fail after 500 cycles No fail after 500 cycles No fail after 500 cycles No fail after 500 cycles No fail after 500 cycles No fail after 500 cycles No fail after 500 cycles No fail after 500 cycles No fail after 500 cycles No sample fail is allowed Pass Spartan-3 / 3E / UMC-12A 90 nm RPT012 (v2.0.2) October 7,

28 Appendix R Drift Analysis HTOL: 125 o C ambient, 1.26V VCCINT, 3.45V VCCO Conclusion: Parametric drifts are covered by test guard band Table 25: Drift Analysis for Spartan-3 Devices Parameters Definition Device 0 hrs 1,000 hr TILO_r TILO_f Icc max Icc standby Delay rise time, PMOS dominated Delay fall time, NMOS dominated Gross Icc unconfigured Quiescent supply current (configured) % of Change 3S % Test Guard Band or Limit Limited by TILO_f 3S % 3% 3S % 100 ma 3S % 80 ma Table 26: Drift Analysis for Spartan-3E Devices Parameters Definition Device 0 hr TILO_r TILO_f Delay rise time PMOS dominated Delay rise time NMOS dominated 1,500 hrs % of Change (1) 3S500E ns ns 4.65% Test Guardband or limit Limited by TILO_f 3S500E ns ns 0.12% 3% Icc Core Gross Icc unconfigured 3S500E ma ma 0.43% o C Icc Stdby Quiescent supply current 3S500E ma ma 1.87% o C 28 RPT012 (v2.0.2) October 7, Spartan-3 / 3E / UMC-12A 90 nm

29 R Appendix 3S500E 1500hrs TILO_r vs. 0hr TILO_r hrs TILO_NW_r (ns) y = x R 2 = hr TILO_NW_r (ns) Figure 1: 3S500E 1,500 hrs TILO_r vs. 0hr TILO_r 3S500E 1500hrs TILO_f Vs. 0hr TILO_f hrs TILO_NW_f (ns) y = x R 2 = hr TILO_NW_f (ns) Figure 2: 3S500E 1,500 hrs TILO_f Vs. 0hr TILO_f 25 3S500E 1500hrs Icc_core (ma) Vs. 0hr Icc_core (ma) hrs Icc_Max (ma) y = x R 2 = hr Icc_Max (ma) Figure 3: 3S500E 1,500 hrs Icc_core (ma) Vs. 0hr Icc_core (ma) Spartan-3 / 3E / UMC-12A 90 nm RPT012 (v2.0.2) October 7,

30 Appendix R 1500hrs_Icc_Standby (ma) S500E 1500hrs Icc_stdby (ma) vs. 0hr_Icc_stdby (ma) y = x R 2 = hr_Icc_Standby (ma) Figure 4: 3S500E 1,500 hrs Icc_stdby (ma) vs. 0hr_Icc_stdby (ma) 30 RPT012 (v2.0.2) October 7, Spartan-3 / 3E / UMC-12A 90 nm