A Time-to-Digital Converter with Small Circuitry

Transcription

1 Gunma University Kobayashi AB1 ASP-DAC 2009 University SI Design Contest 1D-10 A Time-to-Digital Converter with Small Circuitry Kazuya Shimizu, Masato Kaneta, Shigeyuki Nishimura, aijun in, aruo Kobayashi, Nobukazu Takai Gunma University Masao otta Musashi Institute of Technology

2 Research Goal 2 Development of new architecture for a time-to-digital converter with - fine time resolution - high linearity - small circuitry - low power.

3 TDC (Time-to-Digital-Converter) 3 Time interval measurement Digital output T Start Stop TDC Dout

4 Structure of Basic TDC 4 Delay line τ start stop τ τ τ τ D Q D Q D Q D0 D1 D2 Encoder Dout[k]

5 Operation of Basic TDC 5 τ start stop τ τ τ τ D Q D Q D Q D0 D1 D2 Start Stop Timing chart D0=1 D1=1 D2=1 D3=0 D4=0 Encoder Dout[k] Encoder Thermometer code binary code 1SB = tau1 Minimum value depends on CMOS process rule

6 Structure of Vernia Delay ine TDC 6 τ start τ1 τ1 τ1 τ1 D D D Q Q Q stop D0 D1 D2 τ 1 > Encoder

7 Operation of Vernia Delay ine TDC 7 start stop τ1 τ1 τ1 τ1 D D D Q Q Q D0 D1 D2 Encoder Dout[k] Start stage1 D0=1 stage2 D1=1 stage3 D2=1 Stop τ = ( τ1 - ) x M 1SB = τ1 - fine time resolution buffer delay difference stage4 D3=0

8 Structure of Proposed TDC 8 start stop τ1 τ1 τ1 D Q D Q D Q D D D Q Q Q Time Resolution τ 1 - τ 2 D D Q Q D Q Encoder Dout[k]

9 Operation of Proposed TDC 9 In case of 20ps delay Time resolution10ps CK 20ps 30ps 60ps 90ps 120ps 150ps τ1 τ1 τ1 τ1 τ1 50ps 80ps 110ps 140ps 40ps 70ps 100ps 130ps 160ps τ1 = 30ps = 20ps (90nm CMOS)

10 Operation of Proposed TDC 10 In case of 30ps delay Time resolution10ps CK 20ps 30ps 60ps 90ps 120ps 150ps τ1 τ1 τ1 τ1 τ1 50ps 80ps 110ps 140ps 40ps 70ps 100ps 130ps 160ps τ1 = 30ps = 20ps (90nm CMOS)

11 Operation of Proposed TDC 11 In case of 40ps delay Time resolution10ps CK 20ps 30ps 60ps 90ps 120ps 150ps τ1 τ1 τ1 τ1 τ1 50ps 80ps 110ps 140ps 40ps 70ps 100ps 130ps 160ps τ1 = 30ps = 20ps (90nm CMOS)

12 Operation of Proposed TDC 12 In case of 50ps delay Time resolution10ps CK 20ps 30ps 60ps 90ps 120ps 150ps τ1 τ1 τ1 τ1 τ1 50ps 80ps 110ps 140ps 40ps 70ps 100ps 130ps 160ps τ1 = 30ps = 20ps (90nm CMOS)

13 Operation of Proposed TDC 13 In case of 60ps delay Time resolution10ps CK 20ps 30ps 60ps 90ps 120ps 150ps τ1 τ1 τ1 τ1 τ1 50ps 80ps 110ps 140ps 40ps 70ps 100ps 130ps 160ps τ1 = 30ps = 20ps (90nm CMOS)

14 Operation of Proposed TDC 14 In case of 70ps delay Time resolution10ps CK 20ps 30ps 60ps 90ps 120ps 150ps τ1 τ1 τ1 τ1 τ1 50ps 80ps 110ps 140ps 40ps 70ps 100ps 130ps 160ps τ1 = 30ps = 20ps (90nm CMOS)

15 Operation of Proposed TDC 15 In case of 140ps delay Time resolution10ps CK 20ps 30ps 60ps 90ps 120ps 150ps τ1 τ1 τ1 τ1 τ1 50ps 80ps 110ps 140ps 40ps 70ps 100ps 130ps 160ps τ1 = 30ps = 20ps (90nm CMOS)

16 Comparison among TDC Architectures 16 Basic TDC Vernier Delay ine TDC Proposed TDC Time resolution τ1- τ1-20ps 10ps 10ps # of delay buffers τ1 : 30ps : 20ps Input range : 0-200ps

17 Bias1 Proposed TDC Circuit Design Specification Vdd:1.8V Time resolution:100ps 5bit output TSMC 0.18um CMOS process Bias circuit1 in0 in1 Unit cell mp1 DFF atched Comparator τ1 mn1 mp2 mn2 q0 q1 q2 17 out Start Stop mp1 mn1 In0 out In1 mp1 mn1 In0 out In1 mp1 mn1 In0 out In1 mp1 mn1 In0 out In1 mp2 mn2 q0 q1 q2 mp2 mn2 q0 q1 q2 mp2 mn2 q0 q1 q2 mp2 mn2 q0 q1 q2 Bias2 Bias circuit2 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q29 Q30 Q31

18 atched Comparator Circuit Vdd 18 Out Start Stop Out_bar start atched Comparator Truth Table stop out old out old

19 Proposed TDC ayout Process: TSMC 0.18um CMOS (1P6M) Vdd:1.8[V] 5bit output time interval:100ps Output buffer 850um Current source1 19 Delay line1 300um Delay line2 Current source2

20 Proposed TDC Chip Photo 20 TDC

21 Pulse generator ewlett Packard 8110A ON ON Measurement Set up Oscilloscope Infinium 1.5Gz 8Gsanp/s 21 Stop signal Start signal Power supply KIKUSUI PMC18-5A 2.2V ogic analyzer ewlett Packard 1663C IC chip

22 atched Comparator Output Waveform 22 atched Comparator Truth Table start stop out out Faster Stop Faster Start old old Start Stop CMP Out

23 23 Whole TDC Measurement Results output igh output ow +2nsec delay OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 OUT9 OUT10 OUT11 OUT12 OUT13 OUT14 OUT15 OUT16 OUT17 OUT18 OUT19 OUT20 OUT21 OUT22 OUT23 OUT24 OUT25 OUT26 OUT27 OUT28 OUT29 OUT30 OUT31 OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 OUT9 OUT10 OUT11 OUT12 OUT13 OUT14 OUT15 OUT16 OUT17 OUT18 OUT19 OUT20 OUT21 OUT22 OUT23 OUT24 OUT25 OUT26 OUT27 OUT28 OUT29 OUT30 OUT31 OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 OUT9 OUT10 OUT11 OUT12 OUT13 OUT14 OUT15 OUT16 OUT17 OUT18 OUT19 OUT20 OUT21 OUT22 OUT23 OUT24 OUT25 OUT26 OUT27 OUT28 OUT29 OUT30 OUT31

24 Conclusion 24 We have proposed a TDC architecture with small circuitry. We have designed and laid out a prototype TDC. We have measured the prototype TDC Its principle is confirmed.