Measurements and Analysis of a 13um Pitch Charge Transfer TDI Suitable for Space Applications Using a Standard CMOS Technology

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1 Measurements and Analysis of a 13um Pitch Charge Transfer TDI Suitable for Space Applications Using a Standard CMOS Technology Frederic Mayer, Bruno Gili, Henri Bugnet, Frederic Ramus, Frederic Devriere, Thierry Ligozat CNES Workshop November 2013

2 Summary Quick description of the TDI function Presentation of the test chip and the CMOS TDI pixel architecture Electro-Optical results Optimized Future TDI Architecture Conclusions Slide 2

Why working on Time Delay Integration (TDI)?

high speed) Space Earth observation (high sensitivity, SNR boost to overcome shot noise limitation)

numeric on chip, more functionality Lower power consumption Smaller pixel size And ultimately better

3 Why working on Time Delay Integration (TDI)? for high sensitivity, high speed applications Main Applications: Machine vision (high sensitivity, high speed) Space Earth observation (high sensitivity, SNR boost to overcome shot noise limitation) Why moving from CCD to CMOS: Less cost at system level Compact system (better integration with numeric on chip, more functionality Lower power consumption Smaller pixel size And ultimately better performances? Eliixa+ is a successful TDI CMOS but is limited to 4 TDI lines A new architecture is needed to overcome the limitation of the Eliixa camera Slide 3

4 2 main ways to achieve TDI operation in CMOS technology TDI mode (Charge summation) is done in the digital domain TDI mode (Charge summation) is done inside the pixel Vdd GRST TRA SF RST SEL Charge to voltage conversion is done at pixel level Column Charge transfer structure Charge to voltage conversion is done at column level after the charge summation PhD SN Digital Summation ADCs Charge Transfer Summation Dynamic range Unlimited Qsat Qsat limited by pixel Detectivity level High noise level Low noise level Motion MTF Spatial oversampling needed Multiphase pixel ADC speed Slope ADC not suitable Operating at line rate Pixel architecture Standard pixel Charge transfer hard to achieve in CMOS IS process Slide 4

5 Summary Quick description of the TDI function Presentation of the test chip and the CMOS TDI pixel architecture Electro-Optical results Optimized Future TDI Architecture Conclusions Slide 5

Classical CCD like structure Hammershape structure (2 phases in this example): - 1 phase is composed

6 Charge Transfer Structures E2V developed the charge transfer TDI in order to benefit from: - Absence of summation noise - High motion MTF Two structures are fabricated using a standard CMOS IS process Classical CCD like structure Hammershape structure (2 phases in this example): - 1 phase is composed of: - a photodiode part - a pinching gate - a transfer gate - High fill factor due to the photodiode part Slide 6

Comparative operation of both transfer structures Hammershape CCD like Pixel n-1 Pixel n Pixel n+1 Phase 1 Phase 2 Phase 1 Phase 2 Phase 1 Phase 2 Phase 1 Moving direction t 0 T int /2 Pixel n-1

7 Comparative operation of both transfer structures Hammershape CCD like Pixel n-1 Pixel n Pixel n+1 Phase 1 Phase 2 Phase 1 Phase 2 Phase 1 Phase 2 Phase 1 Moving direction t 0 T int /2 Pixel n-1 Pixel n Pixel n+1 Phase 2 Phase 4 Phase 2 Phase 4 Phase 2 Phase 4 Phase 1 Phase 3 Phase 1 Phase 3 Phase 1 Phase 3 Moving direction t 0 T int /4 T int /4 T int /4+δ T int /2 T int /2+δ Moving direction T int /4+δ T int /4+2δ Moving direction T int /2 T int T int /4+2δ T int /2 T int T int + δ T int /2 T int /2+2δ Moving direction Moving direction T int /2+2δ 3.T int /4 T int 3/2.T int 3.T int /4+2δ 3.T int /4+2δ Moving direction Slide 7

6 - Classical CCD video signal: RST/RST coupling/signal Vout (V) 3.5 3.4 3.

8 Test Chip Organization - Full analog test chip - 40 lines of TDI - Devices 7um & 13um - Possibility of controlled electrical charge injection Classical CCD video signal: RST/RST coupling/signal Vout (V) Vout (V) RST level RST coupling Signal time (us) time (us) Slide 8

9 Summary Quick description of the TDI function Presentation of the test chip and the CMOS TDI pixel architecture Electro-Optical results Optimized Future TDI Architecture Conclusions Slide 9

10 CTE Comparison between both Structures 1,0 0,9 *CTE of CCD like is done for a 2-phase equivalent CDD ref (10000 columns, ε= ) - Carriers can be converted into voltage at the bottom of each column fewer transfers compared to CDD (no need for horizontal registers) CTI requirements are relaxed compared to the CCD CTE 0,8 0,7 Hammershape 13um Hammershape 7um Buried CCD like 13um Buried CCD like 7um - At low level, the CTE is better for the Hammershape structure because the carriers are stored in the photodiode and thus are far away from interface states. CTE 0, CTE is measured as : Nbstages ( ε ) = 1 CTI CTE Qsat (%) empty residual ε = =1 Nbstages. Vsignal V - Furthermore, the CTE discrepancy between 7 and 13um is smaller for the Hammershape structure - Qsat CCD like > Qsat Hammershape Slide 10

11 QE and MTF Comparison between both structures 60 - Actual Hammershape: photodiode ~25% of pixel - Optimized Hammershape: ~75% of photodiode area - Poor QE in blue for the CCD like due to the poly absorption - No ulenses - Use of Bulk wafer high QE in NIR (but lower MTF) QE (%) Hammershape Measurements Optimized Hammershape Simulation CCD like Measurements Wavelength (nm) LED Wavelength (nm) Static MTF across Hammershape the track (%) CCD like Static MTF along Hammershape the track (%) CCD like MTF across the track is similar in both cases - MTF along the track is slightly better for the Hammershape structure, but not sure why Slide 11

12 Summary Quick description of the TDI function Presentation of the test chip and the CMOS TDI pixel architecture Electro-Optical results Optimized Future TDI Architecture Conclusions Slide 12

13 Future Work: Optimized TDI array (1/2) - CCD like: high Qsat, lower CTE - Hammershape: lower Qsat, better CTE - CTE may degrade after irradiation at the end of the mission s life For all these reasons, splitting the TDI array into a few sub arrays (typically 2 or 3) will relax the CTI requirement, increasing the Qsat and giving some margin versus end of life requirements The sub TDI will be added digitally Total TDI array Sub TDI array 1 Sub TDI array 2 Sub TDI array 3 ADCs and shift registers Adding the sub arrays may also enable some new features like misalignment corrections Slide 13

14 Future work: Optimized TDI array (2/2) The trade-off could be splitting the TDI pixel array in 2, 3 or M sub-arrays Read 0 Read 1 Read 2 Row Dec Read M-1 Read M ADC Driver sub array 1 sub array 2 sub array M Col. ADC 1 Digital shift registers 1 Col. ADC 2 Col. ADC M-2 Digital shift registers M-2 Read line on each side of TDI sub-array bi-directionnality Relaxed requirement for CTE Full Well enhanced by a factor M Each data has the same processing Optimization of ROW FPN Bi-directionnality supported but Read Noise degraded by M Col. ADC M-1 Data out registers Slide 14

15 Future work: trade off between the number of sub TDI Total CTE 1 0,95 0,9 0,85 0,8 0,75 0,7 Typical Space Requirement Typical Machine Vision Requirement ε=0.002 ε= ε= ε=0.001 ε= Number of stages Increasing the number of sub divisions raises both the Noise/Saturation Equivalent Energy (NEE/SEE) thus on one hand leading to a poorer detection level, but on the other hand leading to a higher saturation level. As the digitalization is done column wise, the number of transfers is limited to the number of TDI stages, unlike the CCD. Thus what is an acceptable unitary CTI (ε) for a CMOS TDI? In order to achieve high CTE, with a ε~10-3, a sub TDI of 20 lines could be a good compromise NEE (a.u.) Example for M*N lines =40 NEE & SEE level of the full digital TDI NEE & SEE level of the full charge transfer TDI M sub divisions NEE SEE SEE (a.u.) Slide 15

16 Conclusion - E2V developed two charge transfer architectures using a classical IS CMOS process: a CCD like structure and an innovative high QE structure called Hammershape - Both devices were fabricated with a 13 and 7 um pitch, characterized and compared - An optimized architecture for future TDI was presented: splitting the main TDI array into sub-tdis allows to relax the CTI constraints and improve the saturation level while keeping low detectivity level. - The next step is to improve slightly the charge transfer efficiency of the structures and to optimize the pixel geometry Thank you for your attention!... And now it s time for questions Slide 16

Analysis and control of vehicle steering wheel angular vibrations

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