General Processor Information
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1 General Information Copyright Tom Burd Last Modified: January 10, 2001 (DISCLAIMER: SPEC performance numbers are the highest rated for a given processor version. Actual performance depends on the computer configuration, and may be less, even significantly less than, the numbers given here. Also note that non-italicized numbers may be company estimates of perforamnce when actual numbers are not available) Intel x86 Source Date v/ v/16 SPEC-92 Units / Pipe Cache Tec V dd M Power (W) int fp int/ldst/fp kb Assoc (um) peak typ /1 1/1/na /1 1/1/na v/ /1 1/1/na v/ /1 1/1/na i386dx i386sx i386sl / [vi,41] /1 4/na/na ~ /1 4/na/na
2 Intel x86 Source Date i486dx i486sx 89 SPEC-92 Units / Pipe Cache Tec V dd M Power (W) int fp int/ldst/fp kb Assoc (um) peak typ [vi,45] /1 5/na/5? 8 u /1 5/na/5? i486sl 92 i486dx2 i486dx4 P /1 5/na/5? /1 5/na/5? 8 u [vi,20] /1 5/na/5? 16 u. 4? [vi,42] /2 5/na/8 8/8 2/ [2,10]
3 Intel x86 P54VRT (Mobile) Source Date [vi,sp] 94 Pipe Cache Tec Vdd M Power (W) [vi,sp] /2 5/na/8 8/8 2/ [mr,vi] P54C [2,11,vi] /2 5/na/8 8/8 2/ P54CQS [47,vi] /2 5/na/8 8/8 2/ P54CS P55C (MMX) P55VRT (Mobile MMX) P6 (Pentium Pro) [53,vi] [31,vi] /2 5/na/8 8/8 2/ /2 6/na/8 16/16 4/ /2 6/na/8 16/16 4/ ? (L) /? 14/14/16 (D) 8/8 (L) 4/ (L) /14/16 7/? (D) 8/8 (M) /2 195 (M) /14/16 (D) 8/8 (N) 4/ (N)
4 Intel x86 Source Date Pentium II (Klamath) Pentium II (Deschutes) Mobile Pentium II (Deschutes) Celeron (Deschutes) Pent II Xeon (Deschutes) Pent III (Katmai) Pent III Xeon (Katmai) [vi,is97,sp] SPEC-95 Units / Pipe Cache (i/d/l2) Tec V dd M Power (W) int fp int/ldst/fp kb Assoc (um) peak typ [vi,by] [vi,is98] /? 16/16 4/ [th]
5 Intel x86 Source Date Celeron (Mendocino) Mobile Celeron (Mendocino) Mobile Pentium II (Dixon) SPEC-95 Units / Pipe Cache (i/d/l2) Tec V dd M Power (W) int fp int/ldst/fp kb Assoc (um) peak typ /16?/? ? /16?/? ? /16?/? ?
6 Intel x86 Pentium III (Coppermine) PentIII Xeon (Coppermine?) Mobile Pentium III (Coppermine) Source Date SPEC-95 Units / Pipe Cache (i/d/l2) Tec Vdd M Power (W) int fp int/ldst/fp kb Assoc (um) peak typ / / / / /700 16/ / /16 256?/? 8?/? 8?/?
7 Intel x86 Source Date Celeron (Coppermine) Mobile Celeron (Coppermine) Pentium Itanium 01 v/64 (Merced) SPEC-95 Units / Pipe Cache (i/d/l2) Tec V dd M Power (W) int fp int/ldst/fp kb Assoc (um) peak typ 16/ /16 128?/? 4?/?
8 Cyrix/ IBM x86 Source Date PR Rating SPEC-95 Units / Pipe Cache (i/d/l2) Tec V dd M Power (W) int fp int/ldst/fp kb Assoc (um) peak typ 486SLC [vi,cm] 20 92? 33 1/ DX4 [vi,cm] 93? 100 2/1 8 u x /1 6/6/? 16 u (M1sc) /1 6/6/? 16 u [is96] gx /1 6/6/? (MediaGX) 16 u PR x86 (M1) 6x86 (M1R) 6x86MX (MII) MXi (Cayenne) [46] /2 7/7/? 16 u [pn,vi] PR PR / PR150 3/2 7/7/? 16 u [pn,vi] 133 PR PR PR166 [vi,55] PR200 ~5.1 ~2.2 [vi,55] 188 PR233 ~ PR PR PR333 99? PR300 PR400 3/2 7/7/? 64 u u ~90
9 VIA Cyrix x86 Source Date MII 99 Cyrix III (M3, or Jalapeno) 00 Samuel 01 PR Rating 300 PR PR PR PR PR PR PR533 SPEC-95 Units / Pipe Cache (i/d/l2) Tec V dd M Power (W) int fp int/ldst/fp kb Assoc (um) peak typ 3/2 7/7/? 64 u. 4 7/?/? 64 u ~120
10 Nexgen (AMD) AMD Source Date Pipe Cache (i/d/l2) Tec V dd M Power (W) Nx586 [42,43] /1 (D) 7/9/na (D) 16/ /1 (D) 7/9/? (D) 16/ [cm] 90 Am486 [pn] / ~3 Am5x /1 16 u Am5k86 K5 K6 K6-2 (K6-3D) [39,vi] [39,vi] (PR75) 90 (PR90) 6/? 5/5/5? 16/8 4/ (PR100) 90 (PR120) (PR133) 6/? 5/5/5? 16/8 4/ (PR166) [vi, is97, 200 ~6.2 ~ ] ~6.8 ~3.8 7/? 6/7/7 (D) /32 2/2 [by] /? 6/7/7 (D) 32/32 2/
11 AMD Mobile K6-2-P K6-III (K6+-3D) Mobile K6-III-P Source Date SPEC-95 Units / Pipe Cache (i/d/l2) Tec V dd M Power (W) int fp int/ldst/fp kb Assoc (um) peak typ /? 6/7/7 (D) 32/32 2/ /? 6/7/7 (D) 32/ /? 6/7/7 (D) 32/
12 AMD Athlon (K7) Duron (K7) Source Date K8 00/1 v/ SPEC-95 Units / Pipe Cache (i/d/l2) Tec V dd M Power (W) int fp int/ldst/fp kb Assoc (um) peak typ /? 64/64 2/ /?
13 IDT WinChip (C6) WinChip2 (C6+) Source Date [vi,55] Pipe Cache (i/d/l2) Tec Vdd M Power (W) 200 ~4.1 ~ /1 (D) 5/5/? 32/32 2/ /2-6/6/? 32/32 2/ ? 300 IDT s Centaur division was acquired by VIA, eliminating plans for WinChip3 and WinChip4 Mot 68k Source Date Pipe Cache (i/d/l2) Tec Vdd M Power (W) int fp int fp int/ldst/fp kb Assoc (um) peak typ [45] NA NA 1/1?/na/na NA/.25 NA/ [41,45] 50 NA 1/1 3/na/na.25/.25 1/ [10,45] /1 6/na/6 4/4 4/ ? [15,21] ~60 (B) ~45 (B) 3/2 8/na/8 8/8 4/
14 Power PC Source Date 601 [15,25] /3 4/5/6 32 u [9,vi] v 32 4/3 4/5/6 32 u [43] /2 4?/5?/6? 4/4 2/ [2,6,25] /2 4/5/6 8/8 2/ [44, vi] e 32 4/2 4/5/6 16/16 4/ ~ q /1 5/5/5? 16/8 4/ [7,8,vi] (H) 120 (H) e Pipe Cache (i/d/l2) Tec Vdd M Power (W) [53,vi,sp] (H) 157 (H) /4-4/5/6 16/16 4/ [mw,vi] [sp] ~ /4-4/5/6 32/32 4/
15 Power PC Source Date 620 [pn,43] /32 8/ /4-4/5/ ~9 64/ x704 [vi,is97] ?/3 6/6?/6? 740 (G3) 750 (G3) (was 613) [vi-mot] 200 [vi-mot] Pipe Cache (i/d/l2) Tec Vdd M Power (W) 2/2 32?/?? [mw] 32 6/3-4/5/6 32/32 8/ [vi-mot] [vi-mot] (mot) 5 67 [mw,is97] (ibm) [vi-mot] [vi-mot] /3-4/5/6 32/32 8/8 [vi-ibm] [vi-ibm] [vi-mot] [vi-ibm]
16 Power PC Power Source Date RS64 [vi-ibm] /64 RS64-II [vi-ibm] /4 64/ / /5 5?/5?/? 32/64 (Power3) (G4) 74XX (G4+) P2SC [vi-mot] Q [vi-mot] /3-4/5/6 32/32 8/ Pipe Cache (i/d/l2) Tec Vdd M Power (W) /4-7/9/11 32/ / ~ /6-32/
17 Sparc Source Date Pipe Cache Tec Vdd M Power (W) CY7C601 [19,20] 90? /1 5/na/na na/na na/na Weitek 2x [20] 92? /1 16/ Micro [20,41] 91? /1 4/ Micro 2 [20,37] /1 5/na/5? 16/ Micro Hyper (Ross) [20] 93? /2-6/6/6 8/na?/na 0.8 [37] /2-6/6/6 8/na?/na (C) 1.7 (C) [49] /2-6/6/6 8/na?/na 0.4 [pn,vi] /2-6/6/6 8/na?/na 0.4 [pn,vi] /2-6/6/6 16/ Super [10,20,vi] ~1.5 ~1.7 5/3 4/4/5 20/16 5/ Super 2 [29,37,vi] /3 4/4/5 20/16 5/4 5? ~3.5 ~ Thunder 1 [21] / ~6
18 Sparc Source Date Pipe Cache Tec Vdd M Power (W) Ultra I [35,43,vi] /4 9/9/9 16/16 2/ Ultra I /4 9/9/9 16/16 2/ ~350 ~ ~ Ultra II Ultra IIi /4 9/9/9 16/16 2/ [is97,vi] < /4 9/9/9 16/16 2/ Ultra III SPARC64 SPARC64II Turbo (Toshiba) Viper (Ross) [vi,43] (HAL) / /4 4/6/7 (F) 4/ ?/60 (G) / / 21.9 (G)
19 a Alpha 21066a PC 21164a Source Date Pipe Cache (i/d/l2) Tec Vdd M Power (W) /2-7/7/10 8/8 1/ [1,4,23] /2-7/7/10 16/16 1/ [18,23] ?/2-7/7/10 8/8 1/ [34,37] /8 1/1 [22,21] /4-7/7/ ? [vi,is97] /4-7/7/9 16/8 1/ ~500 ~ /8 1/ /4-7/7/ ?
20 Alpha Source Date Pipe Cache (i/d/l2) Tec Vdd M Power (W) /4 7/7/10 64/64 2/ ~ [vi,is97] PC [by] /4 7/7/ a [cg,by] /4 7/7/ [cg,by] ~70 ~120 6?/4 6/6/? 64/ / [cg] ~250
21 MIPS Source Date Pipe Cache Tec Vdd M Power (W) R2000 [mc] R3000 [12,20] /1 5/na/na na/na na/na R6000 (E) [20,32] /1 5?/na/na na/na na/na (E) R4000 [20,32] /1 8/na/10 8/8 1/ R4200 [2,5] 93? /1 5/na/5 16/8 1/ [52] R4300i 1/1 5/na/5 16/8 1?/1? R4400 [10,17,sp] [37,38] ? 2/1? 8/na/10 16/16 1/ [53,sp] ~2.2 R4600 [13,37] /1 5/na/5 16/16 2/ R4700 [37,vi] /1 5/na/5 16/ [sp] R /2-5/na/8 32/32 2/ R5000A RM RM ~13 ~15?/2 16/16 4/ R8000 [20,37] /4-5/5/? 16/16 1/ ~ (C) 3.43 (C)
22 MIPS R10000 Source Date 96 Pipe Cache Tec Vdd M Power (W) /4 5/6/7 32/32 2/ ~ ? 275 >12 >24 R H1 00 H ARM Source Date Pipe Cache Tec Vdd M Power (W) 610 [ 3,15,27 ] NA 1/1 3/na/na 4 u [27] NA 1/1 3/na/na 8 u NA 1/1 5/na/na 8 u. 4? ? [vi,is96] NA 1/1 5/na/na 16/16 32/ SA NA NA 1.0 SA NA 1/1 5/na/na 16/8 32/ NA T NA 1/1 5/na/na 4/4 64/ T /
23 Hobbit [3,15] NA 1/1 3/na/na PA- RISC SH Hitachi Source Date Pipe Cache Tec Vdd M Power (W) 92020S [40] NA 7000 [32,54] /1 5/na/na na/na na/na HARP-1 [41] [3,10,sp] /2-5/na/6 na/na na/na [24,sp] 94? /2-5/na/6? na/na na/na LC [24] /2 5/na/6? 1/na?/na ~ [24] ~150 ~ /2 5/na/6? na/2 na/ LC ~200 ~ /2 5/na/6? 64/64 2/ [33,48] >400 > /4-7/9/9 na/na na/na > ?/4 1M / 0.5M 4/ ~ M/ M ? ? 64 II [21] 93 16/ ~8 NA 1/1 5/5/na 4 u ~ (III) [21] 94 16/32 60 ~35 NA 1/1 5/5/na 8 u (III) 97 16/ /1 5/5/na 8 u (IV) 97 16/ ?/2 8/
24 Source Date Pipe Cache Tec Vdd M Power (W) not available yet. Power: peak power numbers used when available, else estimated from average power. Easier to find peak, rather than average. Units: Functional units NOT including system unit; : Peak instructions issued per cycle; - : Indicates limitations on peak issue rate. Cache: On-chip cache (except where footnoted). SPEC: Numbers that are in Italics indicate official CINT95 and CFP95 numbers registered with SPEC (these are peak, not base). B : Estimated that x60 is 3 times the performance of the x40. C : Combined total for 2 chips. D : Data for the RISC-like core. (AMD: rops; NextGen: RISC86 instructions; Intel: uops; IDT: micro-instructions) E : This was an ECL implementation of the MIPS II ISA.. F : External (in an MCM package) G : Single-chip CPU / Combined MCM package. H : These are the highest SPEC numbers reported so far for the 604, which fall below the original estimates (100MHz - 160/165; 133MHz - 200/200) J : This chip reportedly combines a Pentium and PPC604 on one chip (multiple die?). L: This P6 has a 256kB L2 (15.5 million xsistors) in the same MCM package (but xsistors not counted in total). M: This P6 has a 512kB L2 (31 million xsistors) in the same MCM package (but xsistors not counted in total). N: This P6 has a 1MB L2 (62 million xsistors) in the same MCM package (but xsistors not counted in total). O: Includes an integrated on-chip graphics co-processor, but is not included in the unit/issue count.
25 SOURCES (* = Can be found on the CPU Info Center) [1] = ISSCC92 [2] = ISSCC94 [3] = Hot Chips IV [4]* = [5]* = Preliminary Product Sheet for R4200 [6] = to be published. [7]* = Press Release 4/19/94: 100MHz PPC604 [8] = up 4/94 (as reported by M. Horowitz) [9]* = Press Release 3/30/94: 100MHz PPC601 [10] = Spectrum 12/93 [11] = to be published. [12] = Courtesy M. Horowitz, SPEC Table [13]* = Product Sheet for R4600 [15] = CompCon 93 [16] = CompCon 94 [17]* = Product sheet for R4400 [18]* = DEC Press Release. [19] = CY7C601 Data Book [20] = SPECtable from John Dimarco. [21] = Hot Chips 94. [22]* = DEC Press Release 9/7/94 [23]* = John DiMarco s SPEC Table. [24]* = HP s Online server ( [25]* = PowerPC WhitePapers ( p2ppc_tech.html) [27] = from Dave Jaggar, chief architect of the ARM. [30] = 10/10/94 EE Times [31]* = Computergram News [32] = A Guide to RISC Microprocessors. Michael Slater, [33]* = from comp.arch ( pa8000_overview) [34] = 11/21/94 EE Times [35] = Leslis Kohn, Ultrasparc, Invited Speaker, Micro 27 Conf. [36] = from comp.arch -- Alain Lachapelle (alainl@cam.org) [37] = up 12/26/94 [38]* = MIPS Home Page ( [39] = up 10/24/94 [40] = up 1/24/94 [41]* = CHIPS and SYSTEMS SPEC Chart, by Gary Snow. ( snow_survey) [42]* = CHIPLIST 7.2 by Aad Offerman ( [43] = ISSCC95 [44] = Motorola PPC Home Page: ( [45] = Advanced Microprocessors, Daniel Tabak, 1991 [46] = up 2/16/94 [47]* = Intel Press Release [48] = Compcon 95. [49] = Electronic News 3/20/95 [52]* = Press Release 4/17/95 [53] = up 6/19/95 [54] = A Practitioner s Guide to RISC Microprocessor Architecture, Patrick Stakem, 1996 [55] = = Vendor Info [vp]* = Vendor Press Release [pn]* = PowerPC News [mw] = MacWeek (online) [by] = Byte [bw] = Business Wire [mr] = Microprocessor Report [sp] = SPEC [is##] = ISSCC, where the ## indicates the year. [cg] = Computergram International [th]* = Tom s Hardware Guide [re] = The Register NOTE: Hobbit & ARM SPEC calculated from 28k Drystones ~= 8 SPECint92 Hobbit = 27k 20 MHz ARM6 = 28k 20 MHz
General Processor Information
General Processor Information Copyright 1994-2000 Tom Burd Last Modified: April 11, 2000 (DISCLAIMER: SPEC performance numbers are the highest rated for a given processor version. Actual performance depends
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