Helping Moore s Law: Architectural Techniques to Address Parameter Variation

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1 Helping Moore s Law: Architectural Techniques to Address Parameter Variation Computer Science Department University of Illinois at Urbana-Champaign

2 Technology scaling continues Quad Opteron Core 2 Duo Pentium 4 Pentium 3 number of transistors 2 transistor size

3 Challenges to scaling Manufacturing process Environmental Sub-wavelength lithography Temperature variation 45nm 192nm light!"#$ % & '( (07$ BC@A Dopant density fluctuations Supply voltage fluctuations *+,,-.%/0-123$%&4) 4#256%7$-"28"-"1.%9%,0:$7 4#";6%<7$=+$;(.!"#$%&µ'$() 3

4 Variation in transistor parameters pdf Frequency Reliability Power nominal switching speed leakage power AMD Quad-core Opteron Intel 80-core Polaris 4

5 Process variation effects HOF 130nm 5*#$"6)7%-'8#%92%+0: HOD HOG HOH HOQ ABC One generation of process technology is lost to process variation. DBE QOM Q J HQ HJ GQ Shekhar Borkar et al, Intel, DAC

6 Variation components die-to-die fast, leaky transistors within-die C1 C2 C3 C4 slower, less leaky transistors 6

7 Addressing parameter variation Variation reduction Variation tolerance computing stack Runtime system dynamic fine-grain body biasing variation-aware application scheduling and power management C1 C2 C3 C4 C5 variation tolerance Microarchitecture C1 C2 L2 Cache C6 C7 C8 C9 C10 variation reduction C11 C12 C13 C14 C15 Circuits C3 C4 L2 Cache C16 C17 C18 C19 C20 reduce power of high power cells speed up slow cells 7

8 Outline Two solutions: Runtime system variation tolerance Microarchitecture variation reduction Circuits Dynamic fine-grain body biasing [MICRO 07] Variation aware scheduling and power management [ISCA 08] Evaluation Future work 8

9 Outline Two solutions: Runtime system variation tolerance Microarchitecture variation reduction Circuits Dynamic fine-grain body biasing Variation aware scheduling and power management Evaluation Future work 9

10 Body biasing A voltage is applied between source/drain and substrate of a group of transistors Forward body bias (FBB) Reverse body bias (RBB) Frequency Frequency Leakage Leakage Key knob to trade off frequency for leakage power Frequency BB Leakage power Frequency DVFS Dynamic power 10

11 Static fine-grain body biasing (S-FGBB) [Tschanz et al, Intel] RBB reduces static power of leaky cells C1 C2 C3 C4 FBB speeds up slow cells The result is reduced WID variation Frequency FGBB Leakage power improved processor frequency, lower power Additional control over a chip s frequency and power 11

12 Static fine-grain body biasing BB values fixed for the lifetime of the chip Bin 1 Frequency Fmax Bin 2 Bin 3 S-FGBB has to be conservative High power Worst case conditions (temperature, power) are assumed Bin 4 Leakage Leakage power limit 12

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14 Dynamic fine-grain body biasing max T Target: Fmax (07$ RBB S-FGBB BB - fixed BC@A BC@A (07$ slow FBB Higher power consumption average T Target: Fmax (07$ RBB D-FGBB BC@A BC@A fast Lower power consumption BB - variable (07$ FBB 14

15 Dynamic fine-grain body biasing max T Target: Fmax (07$ RBB S-FGBB BB - fixed BC@A BC@A (07$ slow FBB Higher power consumption The goal of D-FGBB is to keep the body bias optimal as temperature changes average T Target: Fmax (07$ RBB D-FGBB BC@A BC@A fast Lower power consumption BB - variable (07$ FBB 14

16 Finding the optimal BB Dynamically measure the delay of each BB cell Delay sampling circuit: CLK FBB Critical Path Replica Phase Detector RBB delay sampling circuit BB for each cell is adjusted as temperature changes Until optimal delay is reached 15

17 D-FGBB environments environment goal Standard Improve frequency and power High performance Maximize frequency Low power Minimize leakage power 16

18 Standard environment Average conditions (Tavg) S-FGBB finds and sets Fmax D-FGBB at Tavg Frequency Fmax S-FGBB at Tavg D-FGBB saves leakage power compared to S-FGBB at Fmax Forig Original chip Power limit Leakage 17

19 D-FGBB Summary S-FGBB64 D-FGBB is very effective at reducing WID variation: NoBB NoBB S-FGBB144 S-FGBB64 S-FGBB64 D-FGBB S-FGBB144 D-FGBB D-FGBB frequency frequency frequency leakage (b) leakage leakage leakage (b) leakage leakage leakage (c) leakage leakag (d) (d) NoBB S-FGBB D-FGBB Figure Frequency versus versus leakage power power for for a batch a batch of 200 of 200 chips chips at usual at usual T and T a s are normalized D-FGBB144. to NoBB. In In the the figure, figure, the Constant the bars bars arefrequency normalized to to NoBB. NoBB. On execution time On average, by40% 6% over lower D-FGBB144 leakage reduces the the execution time time by by 6% 6% over over First, we look at the case when the frequency of First, First, thewe chip we look does look at the at the case case wh NoBB and S-FGBB144. (not Moreover, compared to to NoBB NoBBandand S-FGBB1 (not (not not change. The result is shown in Figure 16. In not not Figure change. 16(a), The The we result result is shown is 0%. shown shown in the in the figure), the the reduction is 10%. is 10%. 10% higher repeat frequency the frequency-leakage scatter plot of Figure repeat repeat 10(a), the the this frequency-leakage time sc at usual T and load conditions. As a result, the at leakage at usual usual T power and T and load is load conditions. NoBB NoBB S-FGBB144 D-FGBB144 significantly lower than in the worst case presented significantly in Figurelower 10(a). lower than than in the in the w Then, Figures 16(b)-(e) show the result of applying Then, Then, S-FGBB Figures or D- 16(b)-(e) show show th FGBB with 0.9 FGBB with different numbers of cells, to reduce leakage FGBBat with constant different numbers of Time Time leakage power (a) (c) leakage power leakage leakage ncy versus leakage power for a batch of 200 chips at usual T and load conditions. 4 D-FGBB144 (b) (d) leakage power (c) (e) Constant Frequency

20 Outline Two solutions: Runtime system variation tolerance Microarchitecture variation reduction Circuits Dynamic fine-grain body biasing Variation aware scheduling and power management [ISCA 08] Evaluation Future work 19

21 Motivation Large CMPs will have significant core-to-core variation We model a 20-core CMP, 32nm C1 C2 C3 C4 C5 L2 Cache fastest C2 Frequency Leakage power Total power C6 C7 C8 C9 C10 vs. 30% 2X 40% C11 C12 C13 C14 C15 slowest C20 L2 Cache C16 C17 C18 C19 C20 Design-identical cores will have significantly different properties 20

22 How can we exploit this variation? Current CMPs run at the frequency of the slowest core We can run each core at the maximum frequency it can achieve C1 C2 C3 C4 C5 L2 Cache 15% average frequency increase Heterogeneous system Variation-aware scheduling C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 L2 Cache C16 C17 C18 C19 C20 Variation-aware power management 21

23 Variation-aware scheduling Applications Variation in core frequency and power Application behavior dynamic power consumption instructions per cycle (IPC) C1 C2 C3 C4 C5 L2 Cache System goals: reduce power improve performance C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 L2 Cache C16 C17 C18 C19 C20 22

24 Variation-aware scheduling Variation-aware scheduling algorithms: Reduce power: Assign applications with high dynamic power to low power cores (VarPower) High IPC C1 C2 C3 C4 C5 L2 Cache Improve performance: Assign high IPC applications to high frequency cores (VarPerf) Low IPC C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 L2 Cache C16 C17 C18 C19 C20 23

25 Variation-aware power management Dynamic voltage and frequency scaling (DVFS) Core-level control over voltage and frequency The challenge: Find optimal (V,F) for each core Variation makes the problem more difficult V,F C1 V,F C2 V,F C3 V,F C4 V,F C5 L2 Cache V,F C6 V,F C7 V,F C8 V,F C9 V,F C10 V,F C11 V,F C12 V,F C13 V,F C14 V,F C15 L2 Cache V,F C16 V,F C17 V,F C18 V,F C19 V,F C20 24

26 DVFS under variation Total power Vdd=0.6-1V 0.6V 0.6V 0.85V 0.7V 1V 0.8V Vdd=1V 0.9V Frequency 25

V Optimization problem Given a mapping of threads to cores

V,F V,F V,F L2 Cache C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 FIND!

C19 C20 V,F V,F V,F V,F V,F Goal: maximize system throughput

27 V Optimization problem Given a mapping of threads to cores (VarPerf): C1 C2 C3 C4 C5 best (Vi,Fi) of each core V,F V,F V,F V,F V,F L2 Cache C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 FIND! V,F V,F V,F V,F V,F V,F V,F V,F V,F V,F L2 Cache C16 C17 C18 C19 C20 V,F V,F V,F V,F V,F Goal: maximize system throughput (MIPS) Constraint: keep total power below budget 50W 75W 100W 26

28 V Optimization problem Given a mapping of threads to cores (VarPerf): C1 C2 C3 C4 C5 best (Vi,Fi) of each core V,F V,F V,F V,F V,F L2 Cache C6 C7 C8 C9 C10 C11 C12 C13 C14 C15? FIND! V,F V,F V,F V,F V,F V,F V,F V,F V,F V,F L2 Cache C16 C17 C18 C19 C20 V,F V,F V,F V,F V,F Goal: maximize system throughput (MIPS) Constraint: keep total power below budget 50W 75W 100W 26

29 Possible solutions LinOpt FIND? Exhaustive search: too expensive Simulated annealing (SAnn) not practical at runtime Linear programming (LinOpt) simpler, faster requires some approximations 27

30 LinOpt problem definition Linear programming: Maximize objective function: f(x1,...,xn), with x1,...,xn independent Subject to constraints such as: g(x1,...,xn) < C f,g are linear functions Variables: voltages V1,...,Vn for all cores Objective function: maximize throughput Throughput (MIPS) = Frequency X IPC = f(v1,...,vn) Constraint: keep power under Ptarget Power = g(v) 28

31 LinOpt implementation LinOpt works together with the OS scheduler OS scheduler maps applications to cores (e.g. VarPerf) LinOpt then finds (V,F) settings for each core LinOpt runs periodically as a system process C1 C2 C3 C4 C5 on a spare core Power management unit (PMU) on-chip microcontroller (Foxton) LinOpt uses profile information as input L2 Cache C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 PMU L2 Cache C16 C17 C18 C19 C20 29

32 LinOpt implementation Post-manufacturing profiling Each core: frequency, static power Dynamic profiling Each app: dynamic power, IPC Power target LinOpt Goal best (Vi,Fi) of each core V,F V,F V,F V,F V,F V,F V,F V,F V,F V,F V,F V,F V,F V,F V,F V,F V,F V,F V,F V,F LinOpt 10ms OS scheduling interval Time 30

33 Outline Two solutions: Runtime system variation tolerance Microarchitecture variation reduction Circuits Dynamic fine-grain body biasing Variation aware scheduling and power management Evaluation Future work 31

34 Evaluation infrastructure Process variation model - VARIUS [IEEE TSM 08] Monte Carlo simulations for 200 chips SESC - cycle accurate microarchitectural simulator HotLeakage, SPICE model - leakage power Hotspot - temperature estimation Mix of SPECint and SPECfp benchmarks 32

35 Dynamic fine-grain body biasing C1 C3 C2 C4 4-core CMP 45nm technology, 4GHz We evaluate FGBB at different granularities (1-144 cells) FGBB16 FGBB64 FGBB144 33

36 D-FGBB Standard 1.15 Frequency D-FGBB144 D-FGBB64 D-FGBB16 D-FGBB1 Leakage reduction 42% 28% S-FGBB144 S-FGBB64 S-FGBB16 S-FGBB1 NoBB More BB cells result in higher frequency and lower leakage Leakage 34

37 Other environments D-FGBB High Performance: 7-10% frequency increase compared to S-FGBB D-FGBB Low Power % leakage reduction compared to S-FGBB 35

38 Variation-aware scheduling and power management C1 C2 C3 C4 C5 L2 Cache 20-core CMP 32nm technology, 4GHz C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 L2 Cache C16 C17 C18 C19 C20 Multiprogrammed workload: 1-20 applications from a pool of SPECint and SPECfp benchmarks 36

39 Power management schemes Goal: - maximize throughput Constraint: - keep power below budget (75W) Foxton+: baseline VarPerf+LinOpt: proposed scheme VarPerf+SAnn: approximate upper bound 37

40 Throughput improvements % 17% 16% 12% MIPS Threads 8 Threads 16 Threads 20 Threads Foxton+ VarPerf+LinOpt VarPerf+SAnn VarPerf+LinOpt: 12-17% over Foxton+ LinOpt: within 2% of SAnn 38

41 To sum up... How much of the performance/power have we recovered? dynamic fine-grain body biasing variation-aware scheduling and power management Frequency Leakage Power 0.9 Throughput No Variation WID Variation D-FGBB Standard D-FGBB HiPerf 0.5 No Variation WID Variation D-FGBB Standard D-FGBB LowPower 0.5 No Variation WID Variation VarPerf+LinOpt 39

42 To sum up... How much of the performance/power have we recovered? dynamic fine-grain body biasing variation-aware scheduling and power management Frequency Both techniques recover most of the losses caused by process variation Leakage Power 0.9 Throughput No Variation WID Variation D-FGBB Standard D-FGBB HiPerf 0.5 No Variation WID Variation D-FGBB Standard D-FGBB LowPower 0.5 No Variation WID Variation VarPerf+LinOpt 39

43 Outline Two solutions: Dynamic fine-grain body biasing Variation aware scheduling and power management Evaluation Intel 80-core Polaris Future work 40

44 Future work Semiconductor roadmaps predict: 11nm billion transistor chips Hundreds of cores on a die Reliability problems will get worse some cores will fail immediately others over time 41

45 Future work Integrated approach to system reliability application hardening Software migration, adaptation Compiler detection, correction environment sensing Operating system Microarchitecture Circuits timing errors 42

key to tackling the Compiler daunting reliability challenges of future

46 Future work Integrated approach to system reliability application hardening Software migration, adaptation detection, correction Integrated solutions - key to tackling the Compiler daunting reliability challenges of future systems. Operating system Microarchitecture environment sensing Circuits timing errors 42

47 Other work Hardware support for on-line software debugging Prototype of a processor with fast, software controlled checkpointing and rollback, in FPGA [FCCM 05][WCED 05] [BUGS 05][Micro Magazine 06] Hardware implementation of a data race detection algorithm [HPCA 07] Log-based architectures for lightweight monitoring of production code [ASID 06] 43

48 Helping Moore s Law: Architectural Techniques to Address Parameter Variation Computer Science Department University of Illinois at Urbana-Champaign

UTBB FD-SOI: The Technology for Extreme Power Efficient SOCs

UTBB FD-SOI: The Technology for Extreme Power Efficient SOCs Philippe Flatresse Technology R&D Bulk transistor is reaching its limits FD-SOI = 2D Limited body bias capability Gate gate Gate oxide stack