Solution-processed carbon nanotube thin-film complementary static random access memory

Transcription

1 Solution-processed carbon nanotube thin-film complementary static random access memory Michael L. Geier, Julian J. McMorrow, Weichao Xu, Jian Zhu, Chris H. Kim, Tobin J. Marks, and Mark C. Hersam * *Corresponding Author: m-hersam@northwestern.edu NATURE NANOTECHNOLOGY 1

2 1. Characterization of Semiconducting SWCNTs The SWCNT purity is determined by UV-vis-NIR spectra through an established method of comparing the area of the S22 peak to that of the M11 peak (Supplementary Fig. 1). Nominally 99% pure semiconducting SWCNTs are used in this study. Supplementary Fig. 1. SWCNT purity characterization. UV-vis-NIR optical absorbance spectra for both sorted and as-received raw SWCNTs in solution. 2 NATURE NANOTECHNOLOGY

3 SUPPLEMENTARY INFORMATION 2. Characterization of SWCNT TFTs As-fabricated SWCNT TFTs are tested for dielectric leakage current, with a typical leakage profile given in Supplementary Fig. 2a. To measure the capacitance of the SWCNT channel and gate structure, source/drain contact probes are shorted externally and voltage was applied to the gate. The capacitance values of the resulting metal-insulator-semiconductor capacitors are measured at 10 khz with an AC amplitude of 50 mv, and show the appropriate accumulation and depletion regimes for both p-type and n-type SWCNT TFTs (Supplementary Fig. 2b). Typical SWCNT TFT output characteristics are shown in Supplementary Fig. 2c for both p-type (V GS varied from V to 0 V in 0.25 V steps) and n-type (V GS varied from 1.75 V to 0 V in 0.25 V steps). a b c Supplementary Fig. 2. SWCNT TFT characterization. (a) SWCNT TFT gate leakage current as a function of V GS. (b) Capacitance-voltage measurement for p-type (blue) and n-type (green) SWCNT TFTs. (c) TFT output characteristics (I DS -V DS ) for a p-type SWCNT TFT (left axis) from V GS = to 0 V in 0.25 V increments and for a n-type SWCNT TFT (right axis) from V GS = 1.75 V to 0 V in 0.25 V steps. NATURE NANOTECHNOLOGY 3

4 3. Time-Dependent Testing For unencapsulated p-type device testing, no dopant or encapsulation fabrication steps are applied. The as-fabricated TFTs (after O 2 RIE) are transferred to a nitrogen atmosphere glove box and annealed in vacuum (30 mtorr) at 230 ºC for 1 h. The substrate is then removed from the nitrogen glove box and electrical testing begins within 1 min of exposure to ambient atmosphere. Devices are then tested by the semi-automatic probe station for an extended period of time to capture changes in the transfer characteristics. For encapsulated devices, both dopant and encapsulation steps are applied, and SWCNT TFTs are measured after the encapsulation step. Consistent time-dependent changes in electronic properties are observed for both individual devices measured repeatedly (Fig. 2) and for multiple devices measured once (Fig. 3 and Supplementary Fig. 3) over the same elapsed testing times as unencapsulated devices. All properties shown in Supplementary Fig. 3 are calculated averages and standard deviations of multiple devices (~50 TFTs) measured once over a similar time period after initial atmospheric exposure. 4 NATURE NANOTECHNOLOGY

5 a b SUPPLEMENTARY INFORMATION c d e f Supplementary Fig. 3. Large sample SWCNT TFT time-dependent electronic transport properties. (a)-(b) Log 10 (I ON /I OFF ) of encapsulated (purple) and unencapsulated (black) (a) p- type and (b) n-type SWCNT TFTs. (c) Subthreshold swing for encapsulated (purple) and unencapsulated (black) p-type SWCNT TFTs. (d) Log 10 (I DS ) values when V GS = 0 V for encapsulated (purple) and unencapsulated (black) n-type SWCNT TFTs. Threshold voltage distributions for encapsulated (purple) and unencapsulated (black) (e) p-type and (f) n-type SWCNT TFTs. NATURE NANOTECHNOLOGY 5

6 4. SWCNT TFT Modelling For circuit simulations, device modelling is used to estimate an approximate drain current in terms of device parameters and terminal voltages. This approach allows a circuit with multiple device parameters to be simulated and its electronic behaviour to be predicted without fabrication. This process can be extended to the simulation of any circuit made using our complementary SWCNT TFTs. In this simulation method, the design parameters, such as channel widths and lengths, can be adjusted to ensure functionality and optimize performance, thus informing the fabrication of an appropriate photolithography mask. The SRAM cell schematic was drawn in Cadence Virtuoso schematic editor (Supplementary Fig. 4a), an integral part of modern integrated circuit design platforms. This design environment allows rapid empirical parameter alterations, design verification, and circuit netlist exporting for simulation. The p-type SWCNT TFTs and n-type SWCNT TFTs were parameter-fitted into a HSPICE level 49 MOSFET model. These models were then used to simulate SRAM circuit operations to verify optimal hold operation, read margin, and write margin performance. The SRAM cell simulated read margin (0.52 V) and write margin (0.73 V) results are shown in Supplementary Fig. 4b and Fig.4c, and are produced using HSPICE based on voltage biases that are applied in the actual SRAM cell measurements. 6 NATURE NANOTECHNOLOGY

7 SUPPLEMENTARY INFORMATION a b c Supplementary Fig. 4. SRAM model and results. (a) Transistor-level SRAM circuit schematic used for simulations. (b) Read margin simulation result. (c) Write margin simulation result. NATURE NANOTECHNOLOGY 7

8 5. Static Random Access Memory Circuit Characteristics SRAM circuits are characterized individually using a semi-automatic probe station, a custom Keithley 4200-SCS user test module, and three external Keithley 2400 units to apply different voltage conditions. The hold margin is tested when the wordline (WL) voltage is set to V DD (1.75 V). The hold operation during the read margin measurement is also known as the static noise margin, and is shown in Supplementary Fig. 5a (purple). The hold operation during the write margin measurement (Supplementary Fig. 5b) shows no write event (purple). The largest static noise margin and smallest write margin (0 V) is observed for the hold condition and is given in Supplementary Fig. 5c. The read and write margins are then measured for various WL voltages from 1.75 V to 0 V and characteristic voltage transfer curves for read and write operations are shown in Supplementary Fig. 5 for all different WL voltages. The measured read margins and write margins are plotted as a function of WL voltage in Supplementary Fig. 5c, showing that the optimal WL voltage is ~1.25 V. 8 NATURE NANOTECHNOLOGY

9 SUPPLEMENTARY INFORMATION a b c Supplementary Fig. 5. SRAM characteristics. (a) Read margin measurement for varying wordline voltages: 0 V (red) to 1.75 V (purple). (b) Write margin for varying wordline voltages: 0 V (red) to 1.75 V (purple). (c) Read margin and write margin as a function of wordline voltage. NATURE NANOTECHNOLOGY 9