Design-Technology Co-Optimization for 5nm Node and Beyond

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1 Design-Technology Co-Optimization for 5 Node and Beyond Semicon West 26 Victor Moroz July 2, 26

2 Why Scaling? When What scales? When does it end? Moore s Law (Fairchild): Double transistor density every couple of years Claasen s Law (Philips CEO): Usefulness = log(technology), or: Technology = exp(usefulness) Koomey s Law (Stanford Professor): "at a fixed computing load, the amount of battery you need will fall by a factor of two every year and a half. By 243, there will be atom per transistor But you can go up (3D IC) Great for planning and aligning the industry Forever? By the second law of thermodynamics and Landauer's principle, irreversible computing cannot continue to be made more energy efficient forever. As of 2, computers have a computing efficiency of about.%. The Landauer bound will be reached in 248. Thus, after 248, the law could no longer hold. With reversible computing, however, Landauer's principle is not applicable. With reversible computing, though, computational efficiency is still bounded by the Margolus Levitin theorem. By the theorem, Koomey's law has the potential to be valid for about 25 years. 26 Synopsys, Inc. 2

3 Scaling Capacitance Transistor strength 26 Synopsys, Inc. 3

4 bad good bad Existing Early Design Rule Evaluation DR DR DR 2 Fin pitch MG ext GDS: Maxwell or Laker Litho: Sentaurus Spac er 7 6 Design rule 26 Synopsys, Inc. 4

5 bad good bad Existing Early Design Rule Evaluation DR DR DR 2 Missing process proximity effects outside of litho Fin pitch MG ext. Spac er GDS: Maxwell or Laker Litho: Sentaurus Missing process interaction with design Gives design window, but no guidance within the window Design rule 26 Synopsys, Inc. 5

bad good bad Process condition Process condition Proposed DTCO: Pre-Si P ower P erformance A rea Evaluation Process T Time Etch Process 48 C 25 min 2 Process2 475 C 23 min 3 DR DR DR 2

6 bad good bad Process condition Process condition Proposed DTCO: Pre-Si P ower P erformance A rea Evaluation Process T Time Etch Process 48 C 25 min 2 Process2 475 C 23 min 3 DR DR DR 2 Fin pitch MG ext GDS: Maxwell or Laker Litho: Sentaurus 3D structure: Process Explorer Switching behavior: TCAD Spac er 7 6 Design rule Design rule Design rule 26 Synopsys, Inc. 6

7 bad good bad Process condition Process condition Proposed DTCO: Pre-Si P ower P erformance A rea Evaluation Process T Time Etch Process 48 C 25 min 2 Process2 475 C 23 min 3 DR DR DR 2 Fin pitch MG ext GDS: Maxwell or Laker Litho: Sentaurus 3D structure: Process Explorer Switching behavior: TCAD Spac er 7 6 Design rule Design rule Design rule 26 Synopsys, Inc. 7

8 bad good bad Process condition Process condition Proposed DTCO: Pre-Si P ower P erformance A rea Evaluation Process T Time Etch Process 48 C 25 min 2 DR Fin pitch MG ext. DR 24 5 DR GDS: Maxwell or Laker Process2 475 C 23 min 3 Litho: Sentaurus 3D structure: Process Explorer Provides quick PPA estimate Includes process effects Switching Enables process-design feedback behavior: Reasonable TAT TCAD Spac er 7 6 Design rule Design rule Design rule 26 Synopsys, Inc. 8

9 2-Input NAND Standard Library Cell 2-input NAND library cell with a load of: A B Q C load Fan-out of 2 Metal wire that is 7 metal pitches long C load = 2*C pin + C wire C wire =.34 ff Typical C load is ff to 2 ff 26 Synopsys, Inc. 9

10 9 Metal Pitches tall Layout: 5 2-NAND Cell, 9 Tracks Tall GP = 32 MP = 24 FP = 8 Dummy gate M2 (PWR) fins PMOS gates M Via2 S/D contact NMOS Via Gate contact M2 (GND) 26 Synopsys, Inc. 3 Gate Pitches wide

11 3D Library Cell in Process Explorer M2 M M Transistors 26 Synopsys, Inc.

Potential, V Power-Performance-Area Evaluation in TCAD.7.6.5.

12 Potential, V Power-Performance-Area Evaluation in TCAD Transient analysis of the switching behavior in Sentaurus-Device Time delay is the averaged pull-up and pull-down delays Rigorous current flow analysis in the 3D structure.3.2 Input Output Low_R. -. 2E- 4E- 6E- 8E- E- Time, s 3D current crowding 26 Synopsys, Inc. 2

13 Energy per switch, fj 5 Technology Evaluation: P ower P erformance A 2-NAND logic cell 2.5 FF 2x FF 2x, low MG R Reference 2-fin FF cell Load: Fan-out of 2 plus 7 pitches long BEOL wire 3D current flow in TCAD FF x NW 2x2 NW 2x.5 NW x Switching delay, ps 26 Synopsys, Inc. 3

14 Energy per switch, fj 5 Technology Evaluation: P ower P erformance A 2-NAND logic cell 2.5 FF 2x FF 2x, low MG R FF x % Low MG resistance: % power reduction Load: Fan-out of 2 plus 7 pitches long BEOL wire 3D current flow in TCAD NW 2x2 NW 2x.5 NW x Switching delay, ps 26 Synopsys, Inc. 4

even more delay Insight Into Metal Gate Resistance Effect Electrostatic potential map

cell 2D cut across the gate NMOS fins NMOS Gate PMOS Gate Input signal arrives here

time This is a new effect, due to the lack of space inside MG for tungsten fill, so MG

15 even more delay Insight Into Metal Gate Resistance Effect Electrostatic potential map delay Due to metal resistance, the input signal takes time to get to the fins 2-NAND cell 2D cut across the gate NMOS fins NMOS Gate PMOS Gate Input signal arrives here first PMOS fins Different parts of the gate experience different biases at any given time This is a new effect, due to the lack of space inside MG for tungsten fill, so MG resistivity increases from ~2 mw. cm to ~2 mw. cm It gets worse for 3 and 4 fins 26 Synopsys, Inc. 5

16 Energy per switch, fj 5 Technology Evaluation: P ower P erformance A 2-NAND logic cell 2.5 FF 2x FF 2x, low MG R FF x % 3% Load: Fan-out of 2 plus 7 pitches long BEOL wire 3D current flow in TCAD NW 2x2 Fin depopulation from 2 to : 3% power reduction NW 2x.5 NW x Switching delay, ps 26 Synopsys, Inc. 6

17 Energy per switch, fj 5 Technology Evaluation: P ower P erformance A 2-NAND logic cell 2.5 FF 2x FF 2x, low MG R FF x % 3% Load: Fan-out of 2 plus 7 pitches long BEOL wire 3D current flow in TCAD NW 2x2 44% NW 2x Nano-wires: 44% better.5 NW x Switching delay, ps 26 Synopsys, Inc. 7

18 Energy per switch, fj 5 Technology Evaluation: P ower P erformance A 2-NAND logic cell 2.5 FF 2x FF 2x, low MG R FF x % 3% Load: Fan-out of 2 plus 7 pitches long BEOL wire 3D current flow in TCAD NW 2x2 44% 5% NW 2x.5 NW x2 Nano-wire depopulation: 5% power reduction Switching delay, ps 26 Synopsys, Inc. 8

19 Energy per switch, fj 5 Technology Evaluation: P ower P erformance A 2.5 FF 2x FF 2x, low MG R FF x 2 fins % 3% FinFET 2-NAND logic cell Load: Fan-out of 2 plus 7 pitches long BEOL wire 3D current flow in TCAD NW 2x2 44% 5% NW.5 NW 2x NW x2 fin Switching delay, ps 26 Synopsys, Inc. 9

20 Energy per switch, fj 5 Technology Evaluation: P ower P erformance A 2.5 FF 2x FF 2x, low MG R FF x 2 fins % 3% FinFET 2-NAND logic cell Load: Fan-out of 2 plus 7 pitches long BEOL wire 3D current flow in TCAD.5 NW 2x2 NW 2x NW x2 44% 5% fin NW Cpin, ff Ion, normalized Switching delay, ps. FF 2x FF x NW 2x2 NW 2x NW x2 26 Synopsys, Inc. 2

21 Energy per switch, fj 5 Technology Evaluation: P ower P erformance A 2.5 FF 2x FF 2x, low MG R FF x 2 fins % 3% FinFET 2-NAND logic cell Load: Fan-out of 2 plus 7 pitches long BEOL wire 3D current flow in TCAD.5 NW 2x2 NW 2x NW x2 44% 5% fin NW % 4% Cpin, ff Ion, normalized Switching delay, ps. FF 2x FF x NW 2x2 NW 2x NW x2 26 Synopsys, Inc. 2

22 Energy per switch, fj 5 Technology Evaluation: P ower P erformance A 2.5 FF 2x FF 2x, low MG R FF x 2 fins % 3% FinFET 2-NAND logic cell Load: Fan-out of 2 plus 7 pitches long BEOL wire 3D current flow in TCAD ~CV 2.5 NW 2x2 NW 2x NW x2 44% 5% fin NW % 4% Cpin, ff Ion, normalized.54 ~CV/I Switching delay, ps.2. FF 2x FF x NW 2x2 NW 2x NW x2 26 Synopsys, Inc. 22

.368.364.495.54.796 Energy per switch, fj 5 Technology Evaluation: P ower P erformance A rea @TCAD 2.5 ~CV 2.

23 Energy per switch, fj 5 Technology Evaluation: P ower P erformance A 2.5 ~CV 2.5 FF 2x FF 2x, low MG R FF x NW 2x2 NW 2x NW x2 2 fins % 3% 44% fin ~CV/I 5% FinFET NW Switching delay, ps MOL 2-NAND logic cell capacitance engineering.2 rules! FF 2x Load: Fan-out of 2 plus 7 pitches long BEOL wire FF x.5 NW 2x2.9 NW 2x NW x2 Cpin, ff 3D current flow in TCAD Ion, normalized 26 Synopsys, Inc. 23

24 Why Variability is Important # Performance A Design spec: Nominal 3s Nominal Technology A What matters is nominal 3s Therefore variability affects chip area I on 26 Synopsys, Inc. 24

25 Why Variability is Important # Performance A Design spec: Nominal 3s Nominal Nominal Technology A Technology B What matters is nominal 3s Therefore variability affects chip area Performance B There is no good enough variability the target is zero! I on 26 Synopsys, Inc. 25

26 Fin Depopulation Adds Pressure to Variability Scaling 4 s Vt ~ / sqrt(# of fins) Synopsys, Inc. 26

27 Fin Depopulation Adds Pressure to Variability Scaling 4 s Vt ~ / sqrt(# of fins) 7 Other considerations: Electromigration Power density Fin pitch 5 26 Synopsys, Inc. 27

28 Sigma Vt, mv Variability Evolution: Planar to FinFET RDF p RDF n n-poly HKMG L CD&LER W CD&LER fin height Encouraging trend Several reset buttons There is nothing that can be done to eliminate RDF, so it kept getting worse for planar 2 sigma pvt sigma nvt The FinFETs are more sensitive to geometry, which can be better controlled by the equipment V. Moroz, WMED Synopsys, Inc. 28

Sigma Vt, mv Variability Evolution: Planar to FinFET 7 6 5 4 3 2 RDF p

values here are due to low Vt process sigma pvt sigma nvt Measured

29 Sigma Vt, mv Variability Evolution: Planar to FinFET RDF p RDF n n-poly HKMG L CD&LER W CD&LER fin The height lower Sigma Vt values here are due to low Vt process sigma pvt sigma nvt Measured data from S. Natarajan et al., IEDM 24 V. Moroz, WMED Synopsys, Inc. 29

Sigma Vt, mv Planar to FinFET Transition Variability Evolution 6 22 Total FinFETs improve variability 5 4 65 Planar MOSFETs

30 Sigma Vt, mv Planar to FinFET Transition Variability Evolution 6 22 Total FinFETs improve variability Planar MOSFETs suffered from RDF Planar FinFET NW FinFETs are insensitive to channel doping RDF Technology node, 26 Synopsys, Inc. 3

31 Sigma Vt, mv HKMG Grains Introduce Gate Workfunction Variation Variability Evolution Total HKMG At and 7 nodes, HKMG becomes the dominant variability mechanism Introduction of amorphous MG at 7 would solve this issue Technology node, 26 Synopsys, Inc. 3

32 Sigma Vt, mv Geometry Variability Evolution Total 6 5 HKMG Geometry Planar MOSFETs are insensitive to geometry FinFETs and NW are more sensitive to geometry NW are less sensitive to L than FinFET, but more sensitive to W Technology node, This data is based on geometry sigma staying at 5% of CD 26 Synopsys, Inc. 32

33 Sigma Vt, mv RDF (Random Dopant Fluctuations) 6 5 Variability Evolution Total HKMG RDF Geometry Planar MOSFETs suffered from RDF 4 FinFETs are insensitive to channel doping RDF 3 2 Technology node, 26 Synopsys, Inc. 33

Sigma Vt, mv FinFET to Nanowire Transition: Counting Particles 6 5 Variability Evolution 3 Total HKMG RDF Geometry KMC 4 3 2

34 Sigma Vt, mv FinFET to Nanowire Transition: Counting Particles 6 5 Variability Evolution 3 Total HKMG RDF Geometry KMC NW variability depends on how many S/D dopants get into the channel 2 dopant dopants Technology node, S D 26 Synopsys, Inc. 34

35 Summary 5 technology has multiple trade-offs in transistor architecture and MOL RC that require holistic engineering Ideal variability is zero, and fin depopulation adds even more pressure Several key factors suggest fin depopulation towards fin and beyond (i.e. fractional fins a.k.a. nano-wires): PPA MOL RC Electrostatics (DIBL) Electromigration and power density 26 Synopsys, Inc. 35

Material Engineering for 7nm FinFETs

Material Engineering for 7nm FinFETs Victor Moroz 2014 Synopsys. All rights reserved. 1 July 10, JTG Semicon West 2014, San Francisco Outline 2014 Synopsys. All rights reserved. 2 Outline 2014 Synopsys.