Material Engineering for 7nm FinFETs
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1 Material Engineering for 7nm FinFETs Victor Moroz 2014 Synopsys. All rights reserved. 1 July 10, JTG Semicon West 2014, San Francisco
2 Outline 2014 Synopsys. All rights reserved. 2
3 Outline 2014 Synopsys. All rights reserved. 3
4 Size, nm Evolution of Transistor Scaling Leff L=Node 10 1 L used to be in sync with technology node L quickly accelerated then saturated Will fall behind 2014 Synopsys. All rights reserved. 4
5 Intel Investor Meeting, Nov. 21, Synopsys. All rights reserved. 5
6 2014 Synopsys. All rights reserved. 6
7 Expected Design Rules Node Gate pitch L Spacer Fin width Fin height Fin pitch Contact size EOT Synopsys. All rights reserved. 7 All sizes are in nm
8 Stress Engineering at 14 nm Node NMOS: Low Stress PMOS: High Stress Junct ion Si Si Main stress source is SiGe PMOS source/drain epitaxy 2014 Synopsys. All rights reserved. 8
9 Common SRB Epi for NMOS & PMOS Wafer before fin patterning Standard cell row Another cell row Ge SiGeSn channel PMOS NMOS PMOS SiGe SRB SiGe SRB Si wafer Si wafer Considering cell heights (pitches) of 360 nm, it is impractical to have separate SRB s for NMOS and PMOS 2014 Synopsys. All rights reserved. 9
10 7nm Stress Engineering: SRB + S/D Epi Si channel SiGe channel Ge channel NMOS Si Si 15% Ge 50% Ge 30% Ge Ge +1.5 GPa 25% Ge 50% Ge 75% Ge PMOS -1.5 GPa 70% Ge Si 85% Ge 50% Ge Ge Ge 25% Ge 50% Ge 75% Ge 2014 Synopsys. All rights reserved. 10 Stress analysis in S-Process
11 Ballistic Ratio Ballistic Transport Evolution Relaxed 2 GPa Ballistic transport is currently ~64% Is expected to rise to ~84% at 7nm node nm 0.41 Even higher for Ge and InGaAs nm nm 5nm technology node Channel Length, nm Therefore, ballistic transport approximation is reasonable for 7nm node Si NMOS FinFET with 6nm wide fin 2014 Synopsys. All rights reserved. 11 Calculated in Sentaurus Monte Carlo
12 Outline 2014 Synopsys. All rights reserved. 12
13 Drain current, A/um Stress Free SiGe: IdVg Curves Vdd = 0.7 V in this project BTBT model calibrated by IMEC Ge Higher Ge % Si Gate bias, V 2014 Synopsys. All rights reserved. 13 3D analysis in S-Device
14 Ion, ua/um Strained SiGe: 2 GPa Tensile Stress 3000 SiGe (2GPa) LP SiGe (2GPa) SP SiGe (2GPa) HP , ,900 2,003 1,902 HP: 100 na/um (Servers) ,233 1,310 1, SP: 1 na/um (Laptops) LP: 50 pa/um (Mobile) Germanium mole fraction 2014 Synopsys. All rights reserved. 14 7nm NMOS FinFET
15 Ion, ua/um Strained SiGe: 2 GPa Tensile Stress SiGe (2GPa) LP SiGe (2GPa) SP SiGe (2GPa) HP Flat Dip 2,429 Best ,900 2,003 1,902 HP: 100 na/um ,233 1, Gone 1,054 SP: 1 na/um LP: 50 pa/um 0 Germanium mole fraction 2014 Synopsys. All rights reserved. 15 7nm NMOS FinFET
16 Inversion charge, 1/cm2 Injection velocityj, cm/s Strained SiGe: N inv and V inj 1.2E+13 SiGe (2GPa) LP SiGe (2GPa) SP SiGe (2GPa) HP 3.E+07 SiGe (2GPa) LP SiGe (2GPa) SP SiGe (2GPa) HP 1.0E E+12 2.E E E+12 1.E E E+00 Germanium mole fraction 0.E+00 Germanium mole fraction 2014 Synopsys. All rights reserved. 16 7nm NMOS FinFET
17 Valley occupancy % Ninv (1/cm2) Delta & Lambda Valley Population 100% 2.0E+12 80% X 1.5E+12 Absolute 60% Relative 1.0E+12 X L 40% 20% L 5.0E+11 0% 0.0E+00 Germanium mole fraction Germanium mole fraction Here, Vgs = 0.7 V and gate WF is adjusted to have min Ioff at Vgs = 0 There are too few electrons at 80% to 90% Ge mole fractions 2014 Synopsys. All rights reserved. 17 S-Band
18 Ion, ua/um Strained SiGe: LP, SP & HP Champions 3000 SiGe (2GPa) LP SiGe (2GPa) SP SiGe (2GPa) HP ,900 2,003 1,902 2,429 HP: Ge ,233 1, ,054 SP: Mid-range SiGe LP: Si 0 Germanium mole fraction 2014 Synopsys. All rights reserved. 18 7nm NMOS FinFET
19 Ion, ua/um Strained SiGe: Combination Champion 3000 SiGe (2GPa) LP SiGe (2GPa) SP SiGe (2GPa) HP 2, ,003 1,900 1, ,233 1,310 1, Germanium mole fraction Better NMOS s Only Si and SiGe with low Ge % can match LP spec HP performance penalty to pure Ge is ~20% The choice between pure Si vs SiGe with low Ge % can be made based on PMOS/NMOS stress trade-off Better PMOS s 2014 Synopsys. All rights reserved. 19 7nm NMOS FinFET
20 Outline 2014 Synopsys. All rights reserved. 20
21 IdVg After Work-Function Adjustment BTBT InAs BTBT model calibrated by IMEC Vdd = 0.7 V GaAs 2014 Synopsys. All rights reserved. 21 3D analysis in S-Device
22 Leakage Patterns InAs BTBT is spread along junction GaAs GIDL happens at the fin top 2014 Synopsys. All rights reserved. 22 Vgs = -0.3 V
23 Bandgap, ev stress Bandgap, ev confinement confinement Band Gap Widening and Narrowing SiGe InGaAs Bulk Strained narrow fin Stress-free narrow fin Bulk Narrow fin Germanium mole fraction Gallium mole fraction For SiGe, 6nm wide fin widens bandgap by 40 mv to 50 mv Tensile uniaxial 2 GPa stress pushes it down by 70 mv to 100 mv For GaAs, the widening is 155 mv, and for InAs it grows to 340 mv 2014 Synopsys. All rights reserved. 23 7nm NMOS FinFET
24 Bandgap, ev stress Bandgap, ev confinement confinement Band Gap Widening and Narrowing LP Ioff spec 1.1 SiGe InGaAs Bulk Strained narrow fin Stress-free narrow fin Bulk Narrow fin Germanium mole fraction Gallium mole fraction High mobility materials need to have bandgap wider than silicon! 2014 Synopsys. All rights reserved. 24 7nm NMOS FinFET
25 Valley occupancy % Valley occupancy % Gamma, Delta & Lambda Valleys 100% 80% X 100% 80% G 60% 40% SiGe 60% 40% InGaAs 20% L 20% L 0% Germanium mole fraction 0% Gallium mole fraction 2014 Synopsys. All rights reserved. 25 7nm NMOS FinFET
26 Inversion charge, 1/cm2 Injection velocityj, cm/s Group IV vs III-V: N inv and V inj InGaAs LP InGaAs SP InGaAs HP SiGe (2GPa) LP SiGe (2GPa) SP SiGe (2GPa) HP 1.2E+13 6.E E+13 5.E E+12 4.E E+12 3.E E+12 2.E E+12 1.E E+00 0.E+00 Mole fraction (Germanium or Gallium) Mole fraction (Germanium or Gallium) 2014 Synopsys. All rights reserved. 26 7nm NMOS FinFET
27 Ion, ua/um Group IV vs III-V InGaAs LP InGaAs SP InGaAs HP SiGe (2GPa) LP SiGe (2GPa) SP SiGe (2GPa) HP 2,612 2,589 2,449 2, ,900 2,003 1,977 1, ,233 1, , Mole fraction (Germanium or Gallium) Synopsys. All rights reserved. 27 7nm NMOS FinFET
28 Ion, ua/um Group IV vs III-V: LP, SP & HP Champions InGaAs LP InGaAs SP InGaAs HP 3000 SiGe (2GPa) LP SiGe (2GPa) SP SiGe (2GPa) HP ,900 2,449 2,612 2,589 2,003 1,977 1,902 2,429 HP: Mid-range InGaAs 1500 SP: 30% In InGaAs 1,233 1, , LP: Si 0 Mole fraction (Germanium or Gallium) Synopsys. All rights reserved. 28 7nm NMOS FinFET
29 Ion, ua/um Group IV vs III-V: Combination Champion InGaAs LP InGaAs SP InGaAs HP SiGe (2GPa) LP SiGe (2GPa) SP SiGe (2GPa) HP 2,612 2,589 2,449 2,429 2,003 1,900 1,902 1,977 Only Si, low Ge SiGe, and GaAs can match LP spec InGaAs with 10% In has competitive performance, but is too sensitive to In content 1,233 1,310 1, Mole fraction (Germanium or Gallium) This would bring severe variability So, silicon looks the best SiGe with low Ge % can be used for stress engineering 2014 Synopsys. All rights reserved. 29 7nm NMOS FinFET
30 Ion, ua/um 0.5 V Vdd Instead of 0.7 V Vdd InGaAs LP InGaAs SP InGaAs HP SiGe (2GPa) LP SiGe (2GPa) SP SiGe (2GPa) HP 1,962 1,547 1,651 1,510 1,239 1,131 1,082 1,211 1,090 1,064 InGaAs with 30% In really shines at SP and HP specs Nobody can pull off LP at 0.5 V Vdd. Would you like your iphone to be ~30x slower? Mole fraction (Germanium or Gallium) To have 0.5 V Vdd, variability has to go down ~2x. That is a stretch. The best InGaAs composition has Silike bandgap 2014 Synopsys. All rights reserved. 30 7nm NMOS FinFET
31 Summary It is a close race, no clear winner The best choice depends on particular chip spec 2014 Synopsys. All rights reserved. 31 7nm NMOS FinFET
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