Attacking the Red Brick Walls of the International Technology Roadmap for Semiconductors (ITRS)

Transcription

1 Attacking the Red Brick Walls of the International Technology Roadmap for Semiconductors (ITRS) Dr. Paolo Gargini Chairman ITRS 2001 Edition Sept

2 What is the ITRS? A consensus reference document with a 15 year outlook on the requirements of the semiconductor industry Provides a reference document for Equipment, Materials and Software Suppliers on the Needs of the Semiconductor Industry and on Possible Solutions Provides a reference document for the researchers on the challenges of the semiconductor industry in the out years

3 Technology Needs Possible Solutions Detailed Solutions Implementation Technology Hierarchy Technology Roadmap Domain Technology Implementation Domain Example: Reduce Signal Propagation Delay of Interconnections Metal Potential Solution: Cu Metal Dielectric Potential Solution: Low K Dielectric Use: Cu CVD Seed Layer + Cu Plating+ CMP+Low K CVD Establish Supplier Infrastructure

4 Roadmap Editions ITRS Update 1994NTRS 1992NTRS 1997NTRS Japan Korea Taiwan USA 2001 Edition Europe 1999ITRS 2000ITRS Update 2001ITRS 1991 Micro Tech 2000 Workshop Report 1998ITRS Update

5 International and Domestic Timing Time Region A Region B 1Q Domestic Domestic 2Q Domestic Europe Domestic 3Q USA 4Q 2001 Korea Japan 1999, 2002 USA Taiwan 2000

6 2002 ITRS Update: December 4 th, 2002

7 Coordination among Associations Mission of ITRS IRC Policy Goals Schedule Coordination among ITWGs ESIA JEITA (STRJ) KSIA TWG TWG TWG Technology Needs Potential Solutions in near & long term FEP etc SIA TWG ITWG Test Design TSIA TWG

8 International Technology Working ITWG Groups Cross ITWG Assembly & Packaging Design Factory Integration Front End Process Interconnect Lithography PIDS, Emerging Devices Test Environment, Safety, Health Metrology Modeling and Simulation Yield Enhancement * PIDS=Process Integration and Device Structures

9 Interconnect ITRS Framework Design Factory Integration ESH Yield Enhancement Metrology Modeling Lithography PIDS FEP Isolation Channel Source / Drain - Extension Wells Starting Material Contacts 2001 Edition QFP Assembly BGA Printed Wiring Board Test PGA

10 Chapters of ITRS 2001 ORTC Glossary 12 ITWGs : Design to Modeling & Simulation -Scope - Difficult Challenges - Technology Requirement - Potential Solutions System Drivers Difficult Challenges Grand Challenges Introduction

11 Contact Information for the ITRS For general questions or information regarding ITRS publications and public forums visit the ITRS web site [note that there is no www in our web site address.]. To order a Roadmap through , use the ITRS address technology.roadmap@sematech.org or access the ITRS web site. Other questions or comments? call Linda Wilson ITRS Information Manager Sarah Mangum ITRS Webmaster ITRS Book and CD sales $25 for CDs, $35 for CDs shipped outside the U.S.A $50 for Books, $65 for ITRS books shipped outside the U.S.A. Back issues of the ITRS are available while quantities last (1999, 1997, 1994)!!

12 Composition of the Technology Working Group (ITWG) in 2001 TWG Members by Regions Korea 64 8% Japan USA % 39% TWG Members by Affiliations Research Inst. / Consortia / University % Other 1% 10 54% 19% Taiwan 161 8% Europe 68 22% Equipment / Materials Suppliers 185 Chip Makers 445

13 Applied Materials KLA-Tencor Tokyo Electron America SEMI Novellus Systems Wacker Siltronic Corp. Agilent Technologies Winbond Electronics Corp. Axcelis Technologies, Inc. Komatsu Silicon MEMC Canon Inc. DuPont Company Silicon Valley Group, Inc ION Systems M+W Zandar Nanya Technology Co. Compaq Computer Corp Asyst Technologies, Inc. Sumitomo Sitix Corp. Varian Air Products & Chemicals Etec Systems, Inc. n-line Corporation K&S CamLine Ebara Rohm Sanyo FSI International Genus Ibis Technology Okmetic Ltd. SiGen Soitec Tokin Corp BOC Edwards Dow Chemical Micronix ASM Lithography Nikon Corporation Photronics, Inc. Shipley Company, Inc. Episil Technologies Metrology Edge Therma-Wave Oki Electric Ind. Co., Ltd. THANK YOU!!! Advantest LogicVision Teradyne Air Liquide Metara, Inc. Millipore Nortel Networks Cadence Intransa UBC ATMI Cabot Corporation E4 Technologies Praxair, Inc. SONY URS Corporation

14 DETAILED SOLUTIONS And IMPLEMENTATION

15 From Strategy to Implementation ITRS Technology Needs Possible Solutions Consortia Researchers Suppliers Detailed Solutions Suppliers IC Makers Implementation OEM

16 Use of ITRS as a Global Planning Tool Internal R&D External R&D Consortia Suppliers SRC Natl Lab ISMT IMEC LETI MEDEA MIRAI ASET Selete

17 Consortia Locations MARCO JR i IRAI PR

18

19 ITRS GUIDING PRINCIPLE

20 R R Transistors Shipped per Year Units '68 '70 '72 '74 '76 '78 '80 '82 '84 '86 '88 '90 '92 '94 '96 '98 '00 '02 Source: WSTS/Dataquest/Intel, 8/02

21 R R Worldwide Semiconductor Revenues $B '68 70 '72 '74 '76 '78 '80 '82 '84 '86 '88 90 '92 '94 '96 '98 '00 '02 Source: Intel/WSTS, 8/02

22 R R Average Transistor Price $ by Year '68 '70 '72 '74 '76 '78 '80 '82 '84 '86 '88 '90 '92 '94 '96 '98 '00 '02 Source: WSTS/Dataquest/Intel, 8/02

23 ITRS GUIDING PRINCIPLE 50% TRANSISTOR AREA READUCION GENERATION TO GENERATION => 30% LINEAR FEATURE REDUCTION 50%

24 Intel s Process Technology Basic Feature Size in microns 0.8µ 0.6µ 0.35µ 0.25µ 0.18µ 0.13µ Pentium Processor Pentium Pro Processor In 26 years, the number of transistors on a chip has increased more than 18,000 times, from 2,300 on the 4004 in 1971 to 42 million on the Pentium 4 processor. Pentium II Processor Pentium III Processor Pentium 4 Processor

25 DEFINITIONS And TIMING

26 Technology Node Definition One half of the smallest pitch in the technology, Typically represented by the first metal layer of DRAM

27 Half Pitch (=Pitch/2) Definition Metal Pitch Poly Pitch (Typical DRAM) (Typical MPU/ASIC)

28 MOS Transistor Scaling (1974 to present) S=0.7 [0.5x per 2 nodes] Pitch Gate

29 1994 NTRS Roadmap Year: NTRS 94 1/2 pitch* * Dimensions for minimum half pitch and isolated line in nm Source: National Technology Roadmap for Semiconductors ITRS 10 ITRS

30

31 WAS Technology Nodes (nm) X IS Actual IRC

32 Year of Production 1999 ITRS Timing Year of Production DRAM ½ Pitch MPU/ASIC ½ Pitch MPU Pr Gate Length MPU Ph Gate Length DRAM ½ Pitch (nm) MPU Gate Length (nm) MPU / ASIC ½ Pitch (nm) ASIC Gate Length (nm) ITRS Timing

33 Production Ramp-up Model and Technology Node Volume (Parts/Month) 100M 10M 1M 100K 10K 1K Development Alpha Tool Beta Tool Production Tool First Conf. Papers Production First Two Companies Reaching Production 200K 20K 2K Volume (Wafers/Month) Source: 2001 ITRS - Exec. Summary 0 Months 12 24

34 3-year cycle 3-year cycle (1977~1995) Innovation 1.4X 4X/3 Years Technology 2X Manufacturing 1.4X

35 10,000 DRAM Chip Size Trend 1.4X/3-years 1T Chip Size (mm 2 ) M 38mm 2 1G 75mm 2 150mm mm 2 800mm 2 ~2X X die growth in 6 years Max Litho Field (4X)

36 3-year -> 2-year cycle (~ ) 3-year cycle Innovation 1.4X 4X/3 Years Technology 2X ->2.8X 1.4X Manufacturing 1.4X ->1.0X

37 10,000 DRAM Chip Size Trend 1.4X/3-years 1T Chip Size (mm 2 ) M 38mm 2 1G 75mm 2 150mm mm 2 800mm 2 ~2X X die growth in 6 years

38 TABLES And WALLS

39 Table s Structure All tables are divided in two parts: Near Term Six year outlook (e.g., ) All values are reported on a yearly basis Long Term Nine year outlook (e.g., ) Values are reported at 3 year interval

40 Tables Color Scheme Solutions Exist White Solutions Being Pursued Yellow No Known Solutions Red A new category will be introduced starting with 2002ITRS Update

41 A Rainbow of Tables DRAM Short Term Requirements YEAR OF INTRODUCTION nm nm nm Table 46b MPUInterconnect Technology Requirements Long Term YEAR TECHNOLOGY NODE 70 nm 50 nm 35 nm MPU½pitch MPUgate length (nm) TECHNOLOGY NODE DRAM pitch YEAR Number of metal DRIVER levels Number of metal levels TECHNOLOGY NODE 70 nm 50 nm 35 nm Number of optional levels ground planes/capacitors Contact A/R s tacked [1] 8.5DRAM ½ 9.0 Pitch (nm) Jmax (A/cm 2 ) wire (at 105 C) 2.1E6 3.7E6 4.6E6 capacitor [2] MPU Gate Length (nm) Imax (ma) via (at 105 C) Local wiring pitch (nm) noncontacted [3] MPU / ASIC ½ Pitch (nm) Table Local 46a wiring pitch MPU (nm) Interconnect Technology Requirements Near Term Specific contact resistance 6E-7 3E-7 Local A/R(for YEAR Cu) [4] ASIC Gate 2E-7 Length (nm) (Ω-cm 2 ) TECHNOLOGY Cu local dishing (nm), NODE 180 nm 130 nm 100 Table 28a Memory and Logic Technology Requirements Near Term 5% height [5] Minimum logic V Specific via resistance 7E-9 2E-9 1E-9 dd (V) (desktop) M Gate MPU ½ Intermediate pitch wiring pitch (nm) YEAR (Ω-cm 2 ) DRIVER [6] T ox equivalent (nm) M Gate MPU gate Intermediate length wiring (nm) dual damascene A/R(Cu 140 wire/via) / / / TECHNOLOGY Metal NODE effective resistivity 180 nm nm nm [7] 3.3Nominal I on 2.2 at 25 C (µa/µm) [NMOS/PMOS] 750/ / /350 M Gate Number of metal levels (µω-cm) high performance Cu intermediate wiring dishing (nm), 15 micron wide wire, 1 DRAM½ Pitch (nm) Number of DRAM Long Term Requirements optional height levels Interlevel metal insulator [8] Maximum 2. 5 I- 3.0 ground planes/capacitors 2 MPU Gate Length effective (nm) dielectric constant off at 25 C (na/µm) M Gate (For minimum L device) high-performance Jmax (A/cm Dielectric ) wire erosion (at 105 C) (nm), intermediate wiring 5.8E5 7.1E E E E6 1.3E MPU / ASIC ½ (nm) (κ) TE 2014 Table 46a MPU Interconnect [9] Gate delay Technology metric CV/I Requirements Near (ps) high-performance Term Imax YEAR (ma) via 2.4Minimumglobal OF INTRODUCTION (at 105 C) wiring pitch (nm) CHNOLOGY NODE [10] Percent static power reduction necessary due to Local wiring 98 Global pitch wiring (nm) M Gate 4 ASIC Gate Length (nm) dual damascene A/R(Cu wire/via) / / / nm nm 35 nm YEAR innovative circuit/system design M & A ½ Local wiring A/R (for Al) DRAM pitch 70 ** 50 ** 5 Minimum logic Vdd 35 (V) (desktop) Solutions Exist Solutions Being Pursued M GATE TECHNOLOGY No Known NODESolutions 180 nm 130 nm 100 Cu global wiring dishing (nm), 15 micron wide wire, [11] Nominal I on at 25 C (µa/µm) [NMOS/PMOS] low 490/ /230 Local 490/230 wiring A/R (for Cu) A Gate Number of metal 10% height 6 levels T Cu local dishing (nm), 5% height ox equivalent (nm) MPU ½ pitch power M GATE MPU gate length (nm) [12] Maximum 140I Intermediate Conductor wiring effective pitch resistivity (nm) (µω-cm) Cu wiring < < Contact A/R stacked capacitor Nominal I on at 25 C (µa/µm) 750/ /35 750/ / /35 750/ /350 off at C (pa/µm) A Gate M GATE Intermediate Barrier/cladding wiring A/R thickness (Al) (nm) ** ** [NMOS/PMOS] high-performance 0 0 Number of metal levels (For minimum 6-7 L device) 6 7 low power Interconnect/7-8-99/CCase Work Number in Progress of optional --- levels Not for Publication [13] Gate delay 0 metric CV/I 0 (ps) low 0power Local wiring Intermediate 3.7 pitch wiring (nm) dual non-contacted damascene A/R 2.0/ / / / / / / Interlevel metal insulator effective dielectric constant (κ) <1.5 <1.5 Maximum I (Cu wire/via) off at 25 C (na/µm) ground M GATE planes/capacitors [14] Percent static power reduction necessary due to A Gate Specific contact resistance (Ω-cm 2 Table ) 28a Memory and Logic Technology Requirements Near 8E-8 3E-8 Term 2E-8 (For minimum L device) high performance Solutions Exist Table 46b MPUInterconnect Solutions Being Technology Pursued Requirements Long No Known Solutions Term Jmax (A/cm 2 ) wire (at 105 C) innovative 5.8E5 circuit/system 7.1E5 design 8.0E5 9.6E5 1.1E6 1.3E6 1.4 Cu intermediate dishing M &(nm), A ½ Gate delay metric CV/I (ps) high-performance Imax (ma) via (at 105 C) [15] V T 3s variation 0.36 (±mv) 0.36 (For minimum 0.33 L device) YEAR YEAR Local wiring pitch (nm) 10 Percent static power reduction necessary due to 0 M GATE [16] S/D extension 500 junction 450 depth, 405 nominal (µm) wiring, % areal density, M Gate 10% height TECHNOLOGY NODE Metal effective resistivity (µω-cm) TECHNOLOGY NODE 70 nm 50 nm 180 nm 35 nm nm nm 2.2 innovative circuit/system design Local wiring A/R (for Al) ** ** M & A ½ Minimum global wiring pitch (nm) Local wiring A/R (for Cu) 1 DRAM½ Pitch (nm) 180 YEAR DRIVER Interlevel metal insulator MPU½pitch - effective dielectric constant 80(k) Global wiring A/R (Al) ** ** Nominal I on at 25 C (µa/µm) 490/ /23 490/ / /23 490/ /230 Cu A local GATE dishing (nm), 5% height TECHNOLOGY NODE 70 nm 50 nm 35 nm Global wiring dual damascene A/R (Cu 2 MPU Gate 2.2/2.4Length 2.3/2.6 (nm) 2.4/ / / / / [NMOS/PMOS] low power 0 0 MPUgate length (nm) Intermediate wiring pitch (nm) wire/via) [1] DRAM ½ Pitch (nm) Solutions Exist 3 MPU / Solutions ASIC ½ Being (nm) Pursued No Known 160 Solutions Maximum Ioff at 25 C (pa/µm) Intermediate A GATE wiring A/R (Al) ** ** Cu global wiring Number dishing of metal (nm), levels [2] MPU Gate Length (nm) micron wide wire, 10% height (For minimum L device) low power Intermediate wiring dual damascene A/R 2.0/ / / / / / / Number of optional levels 4ground ASIC planes/capacitors Gate Length (nm) micron wide wire, 10% height Specific DRAMinterconnect via resistance 17 technology M (Ω-cm Gate 2 Dielectric erosion (nm), intermediate ) E E E-10 DRIVER (Cu wire/via) Conductor effective resistivity ** ** 13 Gate delay [3] metric MPU CV/I /(ps) ASIC low power ½ Pitch (nm) Minimum logic Vdd (V) (desktop) (µω-cm) Al wiring Jmax (A/cm M GATE [4] ASIC Gate Length (nm) No Known Conductor effective Solutions ) wire (at 105 C) 2.1E6 3.7E6 4.6E6 Cu intermediate dishing (nm), Percent static power reduction necessary due to micron wide wire, 10% height resistivity 6to A/R A T ox equivalent 2.2 (nm) GATE Imax (ma) via (at 105 C) M GATE innovative circuit/system design Dielectric erosion (nm), intermediate (µω-cm) Cu wiring* M & A ½ Local wiring pitch (nm) [5] Minimum logic V dd (V) (desktop) wiring, 50% areal density, 10% M height Gate Barrier/cladding thickness Nominal I [6] T ox equivalent (nm) M Gate High κ materials may provide on 17at 25 C (µa/µm) / / / / / / /350 M GATE 15 V [NMOS/PMOS] high-performance some relief 0 0 T 3σ variation (±mv) Minimum M GATE global wiring pitch (nm) Local A/R(for Cu) (For minimum L device) Global wiring A/R (Al) ** ** Interlevel metal insulator [7] Nominal I on at 25 C (µa/µm) [NMOS/PMOS] 750/ / /350 M Gate Cu local dishing (nm), 5% 8height Maximum I off at 25 C (na/µm) M GATE effective dielectric constant (κ) 16 S/D extension junction high performance depth, nominal (µm) Global (For minimum L device) high performance M GATE wiring dual damascene A/R (Cu 2.2/ / / / / / / wire/via) * Intermediate Assumes wiring a conformal pitch (nm) barrier/ nucleation layer [8] Maximum I off at 25 C (na/µm) M Gate ** This technology is 9 not expected Gate delay to metric extend CV/I to (ps) this high-performance node Cu global wiring dishing (nm), Solutions Exist *** Intermediate Calculated wiring for dual a conformal damascene A/R(Cu layer in wire/via) local wiring to 2.5/2.3 meet minimum 2.7/2.4 effective 2.9/2.5 conductor (For minimum L device) Solutions high-performance Being Pursued No Known Solutions 15 micron wide wire, 10% height resistivity 10 Percent static power reduction necessary due to 0 Interconnect/7-8-99/CCase Cu intermediate wiring dishing (nm), 15 micron wide wire, 30 Work 22 in Progress Not for Publication M GATE [9] Gate delay metric CV/I (ps) high-performance Conductor effective 2.4 resistivity ** ** innovative circuit/system design Solutions Exist Solutions Being Pursued No Known 33 Solutions M & A ½ [10] Percent static power reduction necessary due to (µω-cm) Al wiring 10% height M Gate 11 innovative circuit/system design Conductor effective resistivity M & A ½ Dielectric erosion (nm), intermediate Nominal wiring I on at 25 C (µa/µm) / /23 490/ / /23 490/ /230 A GATE (µω-cm) Cu wiring* [NMOS/PMOS] low power 0 0 [11] Nominal I on at 25 C (µa/µm) [NMOS/PMOS] low Minimumglobal wiring pitch (nm) / / /230 A Gate Barrier/cladding thickness power 12 Maximum Ioff at 25 C (pa/µm) A GATE (for Cu wiring) (nm)*** Global wiring dual damascene A/R(Cu wire/via) 2.8/ / /3.1 [12] Maximum I off at 25 C (pa/µm) Interlevel metal 160 insulator A Gate Cu global wiring dishing (nm), 15 (For micron minimum wide wire, L device) low power (For minimum L device) low power effective dielectric constant (κ) 10% height 13 Gate delay metric CV/I (ps) low power [13] Gate delay metric CV/I (ps) low power * 3.7Assumes a conformal barrier/ nucleation layer ** This technology is not expected to extend to this node Conductor effective resistivity 14 (µω-cm) Percent Cu static wiring power reduction necessary 1.8 due to<1.8 0 < A GATE [14] Percent static power reduction necessary due to *** 99Calculated for A a Gate conformal layer in local wiring to meet minimum effective conductor innovative circuit/system design innovative circuit/system design resistivity M & A ½ Barrier/cladding thickness (nm) M & A ½ [15] V T 3s variation (±mv) (For minimum L device) 25 Solutions 17 Exist 17 M Gate Solutions Being Pursued No Known Solutions Interlevel metal insulator effective 15 V T 3σ dielectric variation constant (±mv) (κ) 1.5 < < M GATE [16] S/D extension junction depth, nominal (µm) M Gate Solutions Exist (For minimum L device) Solutions Being Pursued No Known Solutions DRAMinterconnect technology 16 S/D extension junction depth, nominal (µm) M GATE Solutions Exist Solutions Being Pursued No Known Solutions

42 What is a Red Brick Wall? The Red Brick Wall is not used in the ITRS The concept has been introduced in presentations to separate and to highlight a region in a table that is mostly RED beyond a certain year The Red Brick Wall is a good instrument to highlight problem areas

43 Approaching a Red Brick Wall 1999 Results Challenges/Opportunities for Semiconductor R&D Year of Production: DRAM Half-Pitch [nm]: Overlay Accuracy [nm]: MPU Gate Length [nm]: CD Control [nm]: T OX (equivalent) [nm]: Junction Depth [nm]: Metal Cladding [nm]: Inter-Metal Dielectric Κ: <1.5 <1.5

44

45 Attacking the Red Brick Wall 15nm 25 nm Drain Current (µa/µm) Intel s 15nm NMOS Vg =0.8V 0.7V 0.6V 0.5V 0.4V 0.3V Drain Voltage (V)

46 Red Brick Wall becoming permeable 2001 Results Challenges/Opportunities for Semiconductor R&D Year of Production: DRAM Half-Pitch [nm]: Overlay Accuracy [nm]: MPU Gate Length [nm]: CD Control [nm]: T OX (equivalent) [nm]: Junction Depth [nm]: Metal Cladding [nm]: Inter-Metal Dielectric Κ:

47 Roadmap Acceleration and Deceleration 2001 versus 1999 Results Year of Production: DRAM Half-Pitch [nm]: Overlay Accuracy [nm]: MPU Gate Length [nm]: CD Control [nm]: T OX (equivalent) [nm]: Junction Depth [nm]: Metal Cladding [nm]: Inter-Metal Dielectric Κ:

48 CLASSICAL CMOS And BEYOND

49 MOS Transistor Scaling (1974 to present) S=0.7 [0.5x per 2 nodes] Pitch Gate

50 The Incredible Shrinking Silicon Technology Salicide Gate Spacer Salicide Salicide Gate Spacer Salicide 0.35 µ 0.25 µ Salicide Gate Spacer 0.18µ Salicide

51 Material Evolution in MOS 2000 s Al-Cu Al-Cu W 60 s 70 s 80 s 90 s Al-Cu Al-Si Ti/TiN Ti/TiN Al-Cu W Low K Ti/TiN W Cu ELK Ti/TiN Al Poly WSi2/Poly TiSi2/Poly TiSi2/Poly XSi?/Poly SiO2 SiO2 SiO2 SiO2 SiO2 SiO2/SiN Silicon Silicon Silicon Silicon Silicon Silicon

52 Material Evolution in MOS Material Additions Material Replacements 70 s Al-Si Poly SiO2 90 s Al-Cu SiO2 W Ti/TiN TiSi2/Poly SiO Cu/New New/Voids New New New

53 Bulk-Si MOSFET Gate Leakage Source Substrate Gate Drain Channel Leakage Gate Dielectric Scaling Tox equivalent (nm) Monolayers 12 Primary barriers to MOSFET scaling are: High I on /I off ratio (I off = Channel leakage current) Low Standby leakage current (Gate + Channel leakage) Low channel leakage current (Electrostatic scaling) Low gate leakage current

54 Is There Any Oxide Left? Gate oxide less than 3 atomic layers thick PolySi 20 nanometer transistor Atomic structures Silicon

55 Bulk CMOS Scaling Challenges Table 2a High Performance Logic Technology Requirements 2001 ITRS CALENDAR YEAR TECHNOLOGY NODE 130NM 90NM 65NM 45NM 32NM 22NM MPU GATE LENGTH Gate Dielectric Equivalent Oxide Thickness (EOT) (nm) [1] Electrical Thickness Adjustment Factor (Gate Depletion and Quantum Effects) (nm) [2] Tox Electrical Equivalent (nm) [3] Vdd (V) [4] Sub-Threshold C (ua/um) [5] (ua/um) [6] Required "Technology 0% 0% 0% 0% 0% 0% 0% 30% 70% 100% Improvement" (SOI/Low- Temp/High-mobility) [7] Rsd Percent of Ideal Channel 16% 16% 17% 18% 19% 19% 20% 25% 30% 35% Resistance (Vdd/IdNMOS with no RSD) [8] Parasitic Capacitance 19% 22% 25% 27% 29% 29% 27% 31% 35% 42% Percent of Cgate [9] Intrinsic Frequency (1/Tau) (GHz) [10] Relative Device Performance [11] Relative Device Switching Energy [12]

56 but Leakage Keeps Increasing 1.E+03 I Off (A/µm) 1.E-04 1.E-06 1.E-08 1.E-10 Intel 15nm transistor Intel 20nm transistor Jox Inversion 1.E+02 1.E+01 1.E+00 1.E-01 Research data in literature ( ) 1.E-02 1.E-03 1.E-04 1.E-05 Production data in literature ( ) SiO2 Gate Leakage (from literature) 1.E Physical Tox (Å) 1.E-12 Intel 30nm transistor 1.E Physical Gate Length (nm)

57 High-K K Dielectrics

58 Interconnect Grand Challenges Near Term ( ) Enhancing Performance Introduction of New Materials : High Conductivity and Low k Dielectric Integration of New Processes and Structures : High Complexity Long Term ( ) Enhancing Performance Identify Solutions which address Global Wiring Scaling: Beyond Copper and Low k Material Innovation to accelerate Design, Package and Interconnect

59 Interconnect and Dielectric Materials Start Resistivity (µohm.cm) 3 2 Cu 1 End Aluminum Copper Air Relative Dielectric Constant K

60 Assembly & PKG Grand Challenges Chip Package Near Term ( ) Cost-effective Manufacturing Coordinated Design Tools and Simulators : Mix Signal Co-design and Simulation Transient Thermal Analysis Tool QFP BGA Printed Wiring Board PGA Thermal Mechanical Analysis Tool Electrical Analysis Tool -Power Disturbs -EMI -High Frequency / Current and Lower Voltage Switching

61 Emerging Research Devices

62 Traditional Scaling CMOS Future Directions 70%/2-3year Features % / 2-3year Equivalent Scaling Integrated Solutions 2X Performance/2-3year XX New Devices??/2-3year 7/11/1998

63 The Ideal MOS Transistor Metal Gate Insulator Source Drain Fully Surrounding Metal Electrode Fully Enclosed, Depleted Semiconductor High-K Gate Insulator Band Engineered Semiconductor Low Resistance Source/Drain

64 Emerging Research Devices Pursuing CMOS Scaling to the End Bulk CMOS Conventional bulk (SiO2, poly gate, etc..) Introduction of new materials (high-k gate, metal gate electrode,high mobility channel, etc.) Non Classical CMOS Structures Ultra thin channel (SOI) Channel engineered structures Double gate MOSFETs

65 2001 ITRS New Transistor Definitions Source Drain Gate Source Drain BOX Si fin - Body! Ultra-Thin Body SOI Vertical Transistor FinFET Band Engineered Transistor Double Gate Transistor

66 and beyond Nanotube CNN Molecular SRT QD RTD SET

67 Emerging Technology Sequence Emerging Technology Vectors QCA Defect Tolerant Molecular CNN Quantum computing Architecture 3D Integration RTD-FET SET RSFQ QCA Molecular Logic Magnetic RAM FD SOI Phase Change Nano FG SET Molecular Memory Strained Si Vertical Transistor FinFET Planar double gate Non- Classical CMOS Time

68 Conclusions The ITRS has become a common reference document for the Semiconductor Community CMOS will remain the device of choice for the foreseeable future (>10yrs) Introduction of Non-classical CMOS in manufacturing will occur within this decade (~5years) Many new materials will be necessary->back to basics Design, Silicon Process, Package and System interaction will continue to increase-> Need integrated design methodology Innovation in: Architecture, Logic, Memory and Devices is marking the Renaissance of the Semiconductor Industry Economical challenges are exceeding the resources of any individual company or consortium-> Cooperation is a must Red Brick Walls represent an efficient way of identifying and attacking industry wide challenges

69 SUPPORT THE ITRS!!!! IT IS A MATERIAL WORLD!!!!