IME TSI Consortium Industry Forum

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1 Institute of Microelectronics IME TSI Consortium Industry Forum 2.5D Heterogeneous Integration on Through Silicon Interposers 17 th August

2 IME Industry Forum on 2.5D Through Si Interposer (TSI) Consortium Registration Agenda Schedule 9:30AM Welcome note, Overview of IME 2.5D TSI Consortium Industry Guest Presentations: Robert Patti, Tezzaron Semiconductor Anwar Mohammed, Huawei US R&D 300mm Fab Tour, Lunch Technical Proposals for 2.5D TSI Consortium Electrical Design of 2.5D Functional Test Vehicle 300mm Fabrication flow for 2.5D TSI Assembly flow, Thin Wafer Handling for 2.5DTSI Vehicle PDK for Design Enablement of 2.5D TSI, Cost Modeling Thermo-mechanical issues, Thermal solution for 2.5D TSI Vehicle Re-cap, Follow-up Communications 10:00AM - 10:30AM 10:30AM - 11:30AM 11:30AM - 1:00PM 1:00PM - 3:00 PM 3:00PM - 3:15PM Q&A, open discussion 3:15PM Industry Forum Conclusion 4:00PM 2

Cost Solutions - MEMS- ASIC Integration Low Cost, small size, highreliable module packaging Reduced parasitics for higher efficiency Integrated thermal management solution Sensors Actuators and

5D/3DIC Advanced Packaging at IME Green Electronics Nanowire Integration Heterogeneous integration (MEMs, Logic, Memory, Analog/RF, Photonics) Si Photonics Ruggedized Electronics Bio Electronics

3 IME s Advanced Packaging, 2.5D/3D IC Strategic Focus Chip on Flexible Substrate Biocompatible Encapsulation for long term implantation Flip Chip for MEMS structure Vacuum/Hermetic WLP with TSV Thin Film Encapsulation Low Cost Solutions - MEMS- ASIC Integration Low Cost, small size, highreliable module packaging Reduced parasitics for higher efficiency Integrated thermal management solution Sensors Actuators and Microsystems 2.5D Heterogeneous integration (Logic, Memory, Analog/RF, Photonics) on TSI 3D multi-chip stacking Miniaturized Medical Devices GaN on Si Power Electronics 2.5D/3DIC Advanced Packaging at IME Green Electronics Nanowire Integration Heterogeneous integration (MEMs, Logic, Memory, Analog/RF, Photonics) Si Photonics Ruggedized Electronics Bio Electronics Integrated Fiber Coupling Low-Cost MEMS-assisted Passive/Active Packaging & Assembly Flip-Chip, micro-bumping & 2.5D Platform for O/E IC Thermal aware Packaging Innovation Biosensor packaging Microfluidics-integrated biosensor array TSV biosensor array Over 300 o C / 30 kpsi reliability Novel interconnection and encapsulation materials >300 o C MEMS sensor hermetic sealing for harsh environment 3

4 Advanced Interconnect/Packaging Consortia EMWLP High Perf. Materials Fine Pitch Flip Chip with Cu Pillar Cu Wirebond 3D-TSV 2.5D TSI TSV-TSI 12 Engineering Line 4

5 Market for Interposers Expected to be Strong Market driven by Heterogeneous Integration: Logic-Logic, Logic + Memory, MEMS & Sensors. To address the growing market, a strong design, and manufacturing ecosystem is needed. 5

6 Bandwidth, Power-efficiency of Logic-Memory Systems Driving 2.5D IC Landscape High Performance Tablets 2015 Data-center Infrastructure 2009 FPGA + Memory (IME) FPGA + Memory + Optics I/O (IME) SiXiS FPGA (Xilinx) Requirements Data communication systems, and High Performance MobileTablets Higher IO counts to support Wide Bus Architecture Lower Power, Higher Memory Bandwidth(access), Advantages from System Partitioning through Heterogeneous Integration 6

2.5D TSI Solves Wiring Density and Power Constraint.

This allows Wide I/O bus and higher bandwidth.

7 2.5D TSI Solves Wiring Density and Power Constraint. DRAM 3D DRAM bare die Logic DRAM Logic bare Die PKG/SUBS PCB DRAM DRAM 2.5D PCB PKG/SUBS TSI Conventional 2.5D TSI Wiring Density Constraint: Solved by Tight pitch interconnects on TSI. This allows Wide I/O bus and higher bandwidth. DRAM Power-Bandwidth Constraint: Solved by using unbuffered LVCMOS IO Bare Die on TSI, with Wide bus architecture. Heterogeneous Integration: Bare dies are manufactured in their own optimized Silicon technology. IME s TSI Consortium addresses Technology, Manufacturing, and Design challenges encountered by 2.5D TSI industry ecosytem. 7

8 2.5D TSI Challenges: TSI Fabrication, and 2.5D Assembly Flow TSI Fabrication - Large area for Heterogeneous Integration (lithography challenge) - RDL, BEOL cost optimization, Low cost IPD, - TSI Electrical Testing 2.5D TSI Assembly - Chip-to-wafer Bonding. - Temporary Bonding/Debonding (TBDB), - Carrierless Alternative to TBDB for lower cost TSI Cost - Development of 2.5D TSI relative cost-model. - Understanding of critical factors impacting TSI cost. 8

9 2.5D TSI Challenges: Design EDA Flow, Modeling Thermo-Mechanical Modeling, Thermal Solution - Warpage, Solder joint reliability Model for large area TSI, fully assembled 2.5D module - Thermal solution for 2.5D TSI PDK, Electrical Models, EDA Flow - Accurate electrical models and PDK for TSI - Open PDK for members to begin prototyping in TSI platform. TSI Design Challenges for Heterogeneous integration - TSI Wiring Density vs. Performance tradeoff. - Metal Stack Optimization - Signal, Power Integrity - System Design on TSI (vs. PCB) 9

10 IME 2.5D TSI Consortium IME 300mm, 200mm Fab, Assembly Modeling and characterization TSI Process integration Package Design Assembly process optimization Demonstration Vehicle design Reliability, FA Member Companies Product Roadmap Technology, Design Requirements Performance, Reliability requirements Manufacturing Ramp Schedule TSI Consortium Goals TSI Technology Platform Indepth understanding of 2.5D IC manufacturing. Silicon Proven PDK Design, manufacturing flow for TSI products. Cost optimization Functional Vehicle Stronger Manufacturing Ecosystem, 2.5D TSI Consortium addresses technology, manufacturing, design challenges faced by industry. 10

What IME 2.5D TSI Consortium Offers Highlights Technology Platform for Heterogeneous Integration on 2.5D TSI - TSI Fabrication - 2.5D TSI Assembly flow Design Enablement for 2.

11 What IME 2.5D TSI Consortium Offers Highlights Technology Platform for Heterogeneous Integration on 2.5D TSI - TSI Fabrication - 2.5D TSI Assembly flow Design Enablement for 2.5D TSI - PDK, EDA Flow - Thermo-mechanical, Thermal Models Demonstration Functional Vehicle for Heterogeneous Integration - Benefits of 2.5D TSI - Optimization of overall design/manufacturing flow 11

12 IME TSI Consortium Key Deliverables Large area TSI to support rich Heterogeneous Integration 26x44mm 2 TSI die size Up to 52x44mm 2 using double reticle Integrated Passive Devices (IPD) 2.5D TSI Assembly Flow Chip to wafer bonding optimization for Heterogeneous Integration Address 2.5D TSI Assembly flow Challenges TSI PDK on Industry Standard EDA Tools for faster Prototyping Early availability of PDK to consortium members (PEX/DRC/LVS etc) Electrical models for TSI interconnect components and IPD Silicon validation using Functional Vehicle. Time to Market MPW Capability for TSI prototyping by 2013 Relative cost models for TSI 12

13 IME TSI Consortium Key Deliverables Alternative approach to TBDB Carrierless alternative to thin wafer handling Improved Manufacturability compared to TBDB Lower Cost Thermo-mechanical Models Wafer level and package-level thermo-mechanical models. Warpage prediction for large area TSI Solder joint reliability. Thermal Solution Air cooled with heat sink on electrical module. Thermal Solution for FPGA + 3D DRAM 2.5D IC High Performance Vehicle to demonstrate, optimize 2.5D Integration FPGA + 3D DRAM functional system for Tb/s applications Measurement of electrical performance: SI/PI, Speed, Power, Latency Reliability Assessment 13

Vehicles TSV formation, (TSV Via size/tsv depth 10μm/100μm) - Si etch - TSV liner - Barrier/Seed PVD, Cu ECP, CMP.

Cu pillar + SnAg Micro-Bump (30μm pitch) Multi-layer RDL processing C2W & C2C bonding Wafer thinning (50μm),

Schematic/simulation with 3D Full wave solver - Signal/Power Integrity.

spice models) - Parasitic extraction Standard cells: TSV, BEOL & FS/BS via/wires, Inductors, Metal Resistance, Bonds

14 IME s Manufacturing Capability for 2.5D ICs 200mm/300mm fabrication RDL, Bumping, PKG Assembly Modeling, Simulation Process Design Kit (PDK) Applications, Vehicles TSV formation, (TSV Via size/tsv depth 10μm/100μm) - Si etch - TSV liner - Barrier/Seed PVD, Cu ECP, CMP. BEOL process with Cu Interconnects Integrated passives: Resistor, Capacitor, Inductor. Cu pillar + SnAg Micro-Bump (30μm pitch) Multi-layer RDL processing C2W & C2C bonding Wafer thinning (50μm), under-filling and Molding Thin wafer handling for 12 TSV wafer (50μm) Mechanical - Stress & warpage analysis - Solder joint rel. & life prediction Thermal - Cooling solutions to extract heat from the 3D - Passive cooling design Electrical - Schematic/simulation with 3D Full wave solver - Signal/Power Integrity. Design Rules Manual (DRM) EDA design kit - Design rule checking - LVS in EDA tool (inc. spice models) - Parasitic extraction Standard cells: TSV, BEOL & FS/BS via/wires, Inductors, Metal Resistance, Bonds (ubps,c4 Bps, Solder balls) I/O library: To be implemented in EDA Design kit Heterogeneous 2.5D FPGA + 3D Memory Cu BEOL interconnect Integrated Passive Devices (IPD) Low Cost RDL for front-side interconnect. Reduce Organic substrate layers to reduce cost. Litho DRIE CVD Temporally Bond/Debond Backside Via Revealing Cu + solder Microbumping Wafer level Underfilling PVD ECP CMP Wafer Thinning RDL Wafer molding C2W & C2C 14

TSI Process Design Kit (PDK) IME s TSI PDK

Substrate PCB Process Design Kit (PDK): A key

15 TSI Process Design Kit (PDK) IME s TSI PDK Silicon-proven by FPGA+3D DRAM Demonstration Vehicle 3D Mem Metal lid + thermal interface FPGA Through Si Interposer +TSV Organic Substrate PCB Process Design Kit (PDK): A key design enabler for 2.5D, 3D IC design and implementation. 15

Integration of Design and Manufacturing Flow for 2.

constraints early during IC integration on TSI platform

Thermo-mechanical and SI/PI analysis within TSI and Package

16 Integration of Design and Manufacturing Flow for 2.5D TSI TSI Reference flow allows for addressing critical design constraints early during IC integration on TSI platform Optimization for reducing board/package/tsi level parasitics Thermo-mechanical and SI/PI analysis within TSI and Package (Co-design) TSI Warpage Thermo-Mechanical Effects (Warpage, Solder-joint Reliability) IME 2.5D Models 3D Memory and Logic on TSI Physical Implementation using IME PDK on EDA platform Electrical (SI/PI,power,latency) TSI Package Implementation 16

17 TSI Consortium Project Flow Members inputs Finalize project scope, TSI Technology, Test Vehicle Specs. 300mm TSI Fabrication Flow TSI Assembly Process Flow Development Electrical Char., PDK development Thermomechanical, Thermal Models Test Vehicle Design, Signoff 2.5D TSI Fabrication and Assembly Flow Ready Silicon Verified PDK TSI Tapeout 2.5D Test vehicle Fabrication, Assembly Performance, Reliability Assessment 17

18 Consortium Preparation Consortium Duration: 24 months: Nov 2012 through Oct

19 Membership Structure Core membership is S$150,000/= Associate membership is S$80,000/= 19

20 Project Execution Execution - A project team will be formed with member companies - The members in the project review meeting will direct the consortium efforts to meet the project targets & review its progress. - The members will have the choice to directly participate in the experiments and contribute to the success of the project. Communication - Conference calls every 8 weeks (local members can attend in person) - Half-yearly on-site meetings at IME - Periodic Reports and, conf. call Minutes. - Member-company inputs on project steering a key ingredient to project success. 20

21 IME Responsibility of IME & Consortium Members - To conduct research on the Project with the participation of the Consortium members - To co-ordinate activities relating to the Project, including organising the Consortium meetings for the purpose of updating members on a regular basis - To report on the findings of the research work and to keep the Consortium members informed Consortium members - To actively participate in the Project as and when required by the Consortium for the purpose of carrying out and completing the Project - To assist in contacting material suppliers as and when required by the Consortium to carry out the Project - To provide inputs that are required for the formulation of the Project work scope and for the purpose of carrying out the Project 21

22 Before conclusion of today s industry forum, please complete the hard copy of the feedback form (provided to you) and hand it to IME staff. Feedback for Today s Industry Forum feedback form 22

23 Provisional TSI Consortium Membership Reply Slip Attention: Surya Bhattacharya Tel: (65) Fax: (65) Institute of Microelectronics 11, Science Park Road Science Park II Singapore D Through Silicon Interposer (TSI) Consortium Membership Reply Slip Please indicate your interest in the consortium by completing this reply slip and faxing OR sending us a scanned copy We will send you the official agreement for review. The aim is to formally start the project by 1 st Oct 2012 (Monday). Your participation in this consortium will only be confirmed upon the signing of the official agreement. by 14 th Sept 2012 (Friday). We agree to participate in the 2.5D TSI Consortium under the name of (Registered Company Name) at a fee of S$150,000/= for core-membership S$80,000 for associate membership Our participation is conditioned on our review, acceptance, and signature of the member legal agreement. Our only obligation to this project, if any, will be the terms and conditions contained in the member agreement which we sign. Signed by for and on behalf of, Company : Signature : Name : Tel : Fax : Title : Date : Address : 23

24 Thank You Thank You. 24

Future Trends in Microelectronic Device Packaging. Ziglioli Federico

Future Trends in Microelectronic Device Packaging Ziglioli Federico What is Packaging for a Silicon Chip? 2 A CARRIER A thermal dissipator An electrical Connection Packaging by Assy Techology 3 Technology