Siemens HYB39S64800AT-8 64M SDRAM Cell Analysis Report

Transcription

1 February 25, 2000 Siemens HYB39S64800AT-8 64M SDRAM Cell Analysis Report Abstract: The HYB39S64800AT-8 is manufactured in a triple metal 0.25µm CMOS technology. This process has been developed by the joint efforts of IBM, Siemens and Toshiba for their 256M DRAM generation. With a remarkably small die size of 61.92mm 2, and cell size of 0.58µm 2, this device is the smallest 64M SDRAM die that Chipworks has seen to date. This report contains device summary sheets, a die photograph, die markings, package and x-ray photographs, and a microstructural analysis of the memory cell including horizontal and vertical dimensions and FESEM planar and cross-sectional micrographs showing the details of the memory cell structure. SIMS and EDS analyses were also performed of the dopants and materials in the device. For questions, comments, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Elizabeth Jagodzinska at Chipworks, Inc. Telephone (613) Facsimile (613) F3.0

2 Some of the information in this report may be covered by patents, mask and/or copyright protection. This report should not be taken as an inducement to infringe on these rights Chipworks Incorporated This report is provided exclusively for the use of the purchasing organization. It can be freely copied and distributed within the purchasing organization, conditional upon the accompanying Chipworks accreditation remaining attached. Distribution of the entire report outside of the purchasing organization is strictly forbidden. The use of portions of the document for the support of the purchasing organization's corporate interest (e.g., licensing or marketing activities) is permitted, as defined by the fair use provisions of the copyright act. Accreditation to Chipworks must be attached to any portion of the reproduced information.

3 Siemens HYB39S64800AT-8 2Mx8x4 SDRAM Contents: List of Figures...Page 1 Introduction...Page 3 Device Summary Sheet...Page 5 Memory Cell Structure...Page 8 Horizontal and Vertical Dimensions Measurements...Page 11 FESEM Plan View Micrographs...Tab 1 FESEM Cross-Sectional Micrographs Along Wordline Axis...Tab 2 FESEM Cross-Sectional Micrographs Along Bitline Axis...Tab 3 Cell Fabrication Process Flow...Tab 4 SIMS Analyses of Dopants in Memory Array...Tab 5 EDS Analyses of Materials in Cell Structure...Tab 6 Rev /20/99 12:04 PM Y:\Sr\Siemens\64mSDRAM\Cell\PDF\Report\toc.doc

4 Siemens HYB39S64800AT-8 2Mx8x4 SDRAM Page 1 List of Figures Package Markings Package X-Ray Die Markings Die Photograph Annotated Die Photograph Die Architecture FESEM Cross-Sectional Micrographs of Cell Array Illustrating Levels of Plan View Images FESEM Plan View Micrographs of Cell Array at Bitline and Wordline Levels FESEM Plan View Micrographs of Cell Array at Active Region Level FESEM Plan View Micrographs of Cell Array at Shallow Trench Isolation Level FESEM Plan View Micrographs of Cell Array at P-Well Level FESEM Plan View Micrographs of Cell Array at Cell Plate Level FESEM Plan View Micrographs of Cell Array Illustrating Positions of Cross- Sectional Images FESEM Cross-Sectional Micrographs of Cell Array Through Opposite Edges of Wordline FESEM Cross-Sectional Micrographs of Cell Array Through Access Transistor (close-up) FESEM Cross-Sectional Micrographs of Cell Array Through Access Transistor FESEM Cross-Sectional Micrographs of Cell Array Through Bitline Contacts FESEM Cross-Sectional Micrographs of Cell Array Showing Column Access Signal Line (top) and Wordline Strap (bottom) FESEM Cross-Sectional Micrographs of Cell Array Showing Metallization (top) and Trench Structure (bottom) FESEM Cross-Sectional Micrographs of Cell Array Illustrating Positions of Cross-Sectional Images FESEM Cross-Sectional Micrographs of Cell Array Through Access Transistors FESEM Cross-Sectional Micrographs of Cell Array Through Trench Capacitor FESEM Cross-Sectional Micrographs of Cell Array Through Opposite Edges of Bitline Composite FESEM Cross-Sectional Micrograph of Cell Array Showing Trench Capacitors FESEM Cross-Sectional Micrographs of Cell Array (wide angle view) Rev July 20, :06 PM Y:\Sr\Siemens\64mSDRAM\Cell\PDF\Report\figlist.doc

5 Siemens HYB39S64800AT-8 2Mx8x4 SDRAM Page Memory Cell Cross-Sectional Sketch Cell Fabrication Process Steps (1) Cell Fabrication Process Steps (2) Cell Fabrication Process Steps (3) Cell Fabrication Process Steps (4) Mask Sequence SIMS Profile of Boron in Array Area SIMS Profile of Arsenic in Array Area SIMS Profile of Phosphorus in Array Area SIMS Profile of Arsenic (Well Contact) and Phosphorus in Peripheral N- Well SIMS Profile of Boron in Peripheral P-Well SIMS Profile of Boron in Source/Drain Areas of Peripheral PMOS Transistor SIMS Profile of Arsenic and Phosphorus in Source/Drain Areas of Peripheral NMOS Transistor EDS Spectrum of Shallow Trench Isolation Dielectric EDS Spectrum of Wordline EDS Spectrum of Wordline Cap Dielectric EDS Spectrum of Dielectric Between Wordlines EDS Spectrum of Area of Bitline Contact EDS Spectrum of Metal EDS Spectrum of Intermetal Dielectric Between Metal 1 and Metal EDS Spectrum of Metal EDS Spectrum of Interlayer Dielectric Between Metal 2 and Metal EDS Spectrum of Metal 3 Barrier Layer EDS Spectrum of Metal EDS Spectrum of Anti-reflecting Cap on Metal EDS Spectrum of Lower Passivation Dielectric EDS Spectrum of Top Passivation Dielectric Rev July 20, :06 PM Y:\Sr\Siemens\64mSDRAM\Cell\PDF\Report\figlist.doc