ReRAM Technology, Versatility, and Readiness

Transcription

1 ReRAM Technology, Versatility, and Readiness Hagop Nazarian VP of Engineering & Cofounder Santa Clara, CA 1

2 Introduction to ReRAM ReRAM Technology Attributes Scalability Ease of integration with CMOS Architectural Flexibility Energy reduction 40nm ReRAM Product results Performance Endurance Retention Status & Conclusion Santa Clara, CA 2

3 Filamentary ReRAM technologies leads to a simple yet powerful non-volatile technology Top Electrode (Select) Top Electrode Select Switching Medium Top Electrode Switching Medium Switching Medium Bottom Electrode Bottom Electrode Santa Clara, CA 3

4 Normalized Current Normalized Current Normalized Current Wide range of applications with ReRAM Crossbar ReRAM Cell Crossbar Selector Crossbar SR Cell R + = S R S Suited for low latency, high speed embedded memory Santa Clara, CA 4 Suited for high density high performance NAND or SCM memory

5 ReRAM Technology Attributes Santa Clara, CA 5

6 ReRAM performance improves with scaling Roff Ron Scaling ReRAM device Roff 1 Cell Area Ron Stays nearly constant Roff/Ron ratio improves Sensing window improves Improves BER r = 40nm r=20nm r = 10nm Ioff=1uA, Roff=1MΩ, Ron=10KΩ Roff/Ron=100 Ioff=0.25uA, Roff=4MΩ, Ron=10KΩ, Roff/Ron=400 Ioff=62nA, Roff=16MΩ,Ron=10KΩ, Roff/Ron=1600 Santa Clara, CA 6

7 Ease of integration with CMOS Back-end process No impact to CMOS transistors ReRAM located between metal layers Adds only 1 to 2 masks & 8 processing steps 32% lower cost Smaller die size 1T1R ReRAM 1P9M Santa Clara, CA 7

8 ReRAM enabling scalability, performance, monolithic integration Conventional Flash ReRAM Architectural Advantages 4 terminal device D/G/S/Substrate 2 terminal device Smaller device Simpler to operate Common substrate Has no common terminal Allows Byte alterability Byte Write Front-end Impacts CMOS transistors Back-end Area efficiency No impact on CMOS transistors Requires additional HV transistors Scaling Limitations or Degradations No HV transistors needed No Scaling limitations or Degradations Much easier to design and integrate with CMOS and uses 1 or 2 masks Well Suited for advanced nodes Monolithic integration with CMOS Santa Clara, CA 8

9 Major system energy reduction with ReRam Energy consumption ratio NAND/ReRAM based on SSD & NVDIMM-P Write Amplification NAND based SSD (nj) SSD 512B Write ReRAM(nJ) ReRAM Energy Reduction Santa Clara, CA 9 NAND based NVDIMM-P(nJ) NVDIMM-P 64B Write ReRAM(nJ) ReRAM Energy Reduction X X X X X X X X ReRAM based SSD provides 2X to 5X energy reduction ReRAM based NVDIMM provides 20X to 40X energy reduction

10 ReRAM Product Array Results Performance Endurance Retention Santa Clara, CA 10

11 Stable performance across VCC and wide temp range Superior Speed stability across temperature and VCC is established Santa Clara, CA 11

12 Problems with aging Flash technology Off On Vt Flash distributions widens Flash distribution gap closes increasing BER Santa Clara, CA 12

13 300K endurance cycles with no degradation 32Kb Endurance Cycling 100% Cycle 0 90% Cycle 10 80% Cycle % Cycle 1K 60% Cycle 10K 50% Cycle 50K 40% Cycle 100K 30% Cycle 200K 20% Cycle 300K 10% 0% Cell Current (ua) % 10% 8% 6% 4% 2% Cycle 0 Cycle 10 Cycle 100 Cycle 1K Cycle 10K Cycle 50K 32Kb Endurance Cycling Cycle 100K Cycle 200K Cycle 300K NAND NOR Flash 0% Cell Current (ua) ReRAM On and Off Distribution width stayed the same!!! ReRAM On and Off Distribution gap increased!!! Santa Clara, CA 13

14 ReRAM vs. Flash Distribution over endurance & retention Off On Off FLASH Vt Off ReRAM On I ReRAM Distribution gap & width does not close or widen!! Santa Clara, CA 14

15 ReRAM distribution is unchanged after 5X solder reflow retention test 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 0% Reflow Retention Pre Reflow 5X Cell Current (ua) 10% 9% 8% 7% 6% 5% 4% 3% 2% 1% 0% Reflow Retention Pre Reflow 5X Cell Current (ua) Santa Clara, CA 15

16 ReRAM retention post 10K cycles is solid No changes 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 0% 32Kb Data Retention (Post 10K Cycle) Pre Bake Bake Cell Current (ua) 12% 10% 8% 6% 4% 2% 0% 32Kb Data Retention (Post 10K Cycle) Pre Bake Bake Cell Current (ua) Santa Clara, CA 16

17 ReRAM retention post 300K cycles is solid No changes 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 0% 32Kb Data Retention (Post 300K Cycle) Pre Bake Bake Cell Current (ua) 14% 12% 10% Santa Clara, CA 17 8% 6% 4% 2% 0% 32Kb Data Retention (Post 300K Cycle) Pre Bake Bake Cell Current (ua)

18 ReRAM is here and ready for the future Impressive reliability with robust retention post 10K & 300K endurance cycles ReRAM distributions remain stable post 5X Solder reflow Consistent ReRAM array performance across temperature (-40, 125C) and VCC range Starting production with SMIC for ReRAM customer designs 2X node ReRAM integration in progress Already started 1X node ReRAM design with customer Santa Clara, CA 18