DARE+ DARE+ Design Against Radiation Effects (Digital) Cell Libraries. Jupiter Icy Moons Explorer (JUICE) Instruments Workshop 9 November 2011
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1 DARE+ Design Against Radiation Effects (Digital) Cell Libraries Jupiter Icy Moons Explorer (JUICE) Instruments Workshop 9 November 2011
2 Objectives (1/2) Provide a suitable and mixed-signal capable microelectronic technology for platform and payload elements of S/C on Jovian missions. Increase and demonstrate the maturity of the existing DARE 180 nm library for applications in very harsh radiation environments up to 1 Mrad TID (Si).
3 Objectives (2/2) - Create currently missing library elements. - Fix known issues. - Create standard packaging solutions. - Design, manufacture and evaluate a test vehicle. - Design, manufacture and evaluate a representative ASIC.
4 DARE Design Against Radiation Effects (Digital) Cell Libraries
5 Space ASICs in Europe: Old & Recent challenges LOW VOLUMES: no big profits with space ASICs EXPENSIVE SPACE QUAL CONTROL (rad effects, reliability make more design and tests necessary; Agencies periodic audits) PACKAGING: still to be qualified for space: flip-chip and column/short pin packages for high pin counts. Also PCB mounting. Space ASICs tend to be large Big Uncertainties on EU ASIC Fabs future: - ATMEL(F) is selling its last plant in Europe (Rousset), after selling plants in France (MHS), UK and Germany. The whole ASIC Business Unit might be sold as well. Sales declines forced to temporary foundry shuts. - E2V(F) is restructuring internally due to revenue decline. Temporary shuts. - XFAB fab in UK closing - LFOUNDRY (D) fab in Landshut is closed. Future of Rousset plant (see above) is uncertain.
6 Why DARE was created - late 90 s ASIC Foundries used for space components were scarce, expensive and were discontinuing rad hard processes (ABB-HAFO & SOS). The dependence on commercial, high volume ASIC processes was evident : First Technology Research Programme (TRP) funds were dedicated to Harden-by-Design ASIC libraries based on a commercial technology: UMC 180nm available on Europractice MPW /2001After 1st proof of concept, new contracts launched to improve and add library elements, and develop a 1st customer design (DROM) /07 new contracts launched to do a second customer design (LEON3), including ESCC evaluation and a maintenance contract, to start porting DARE to 90nm. :
7 Dare Activities DARE+ Closed: 14177/99/NL/FM GSTP-2 Proof of concept 14932/00/NL/DS NSGU Main Library Development 15852/01/NL/FM TRP Radiation Hardening by Design (RHBD) 3 On-going: 19916/06/NL/JD GSTP ASICs for Space Fabricated with RHBD Library 20896/07/NL/JD TRP DARE Maintenance and Porting 4000Xxxxxxx TRP DARE+ Related: 21855/09/NL/JK TRP Radiation Effects on Deep Sub Micron CMOS Technologies
8 Integrated Circuits
9 Building Blocks set A D S Q Memory B C clk R Q Register Adder reset Adder Flip-Flop
10 a Inverter NOR NAND T2 T1 a T1 b x T2 T3 z x T2 T3 z T1 y T4 y T4
11 Layout (part of XDFF)
12 ASIC Flow: Design, Manufacture and Test DARE+ Detailed Requirements Specification Front-End Design VHDL, Schematics, Constraints Back-End Design ASIC Layout (GDSII) Foundry Q Evaluation Assembly Wafers Components
13 ASIC Flow: Design Kits DARE+ Detailed Requirements Specification Front-End Design VHDL, Schematics, Constraints Back-End Design ASIC Layout (GDSII) Digital Design Kit Digital Library Design Analogue Design Kit Foundry Q Evaluation Assembly Wafers Components
14 ASIC Flow: ATMEL DARE+ Detailed Requirements Specification VHDL, Constraints ASIC Layout (GDSII) Front-End Design Back-End Design Digital Design Kit Digital Library Design Analogue Design Kit ATMEL Q Evaluation Assembly Wafers Components
15 ASIC Flow: DARE 180 nm / 90 nm DARE+ Detailed Requirements Specification Front-End Design VHDL, Schematics, Constraints Back-End Design ASIC Layout (GDSII) Digital Design Kit Digital Library Design Analogue Design Kit UMC IMEC Q Evaluation Assembly Wafers Assembly and Test House
16 TID test (1/2) Following ESCC22900 Icc stand-by of the core : Stable until 100 krad(si) Iccsb Core (1,8V) SN125-REF SN003 SN087 SN089 SN122 Increase until 500 krad (Si) SN138 To decrease until 1 Mrad (Si) Fully recovery & functional after accelerated ageing at 100 C I (ma) Iccsb IO (3,3V) Dose (krad (Si)) h annealing h annealing h annealing h ageing I (ma) SN125-REF SN003 SN087 SN089 SN122 SN138 Icc stand-by of the IO : q Dominated by the LVDS buffers consumptions q No significant evolution during the irradiation Dose (krad (Si)) h annealing h annealing h annealing h ageing
17 TID test (2/2) 2,6 Ring Osc Frequency Timing drift : Measure of an embedded ring oscillator No significant variations during and after irradiation F (Mhz) 2,55 2,5 2,45 2,4 2,35 2,3 2,25 2,2 2,15 SN125-REF SN003 SN087 SN089 SN122 SN Dose (krad (Si)) h annealing h annealing h annealing h ageing
18 DARE + Design Against Radiation Effects (Digital) Cell Libraries for Harsh Space Environments
19 DARE+ Core Library Clock gating 3.3 V flavor RAM compiler Problem fix Dual port PLL Full characterization Re-characterization for mixed-mode technology flavor I/O Library 5V tolerant Pull-up / pull-down Improved LVDS Improved ESD protection Multi fan-out IBIS Models 3.3 V -> 1.8 V voltage regulator Demonstration ASIC (DSP)
20 PLL
21 SRAM (Compiler)
22 5V Tolerant I/O
23 Output Pads w/ Slew Control
24 Output Pads w/ New Drive Strengths DARE+
25 Schmitt Trigger (2.5 / 3.3 V)
26 Integrated Clock Gating
27 Voltage Regulator
28 I LVDS Receiver ESD Update IBIS Models Dual Port SRAM Compiler 8ch Analogue Multiplexer
29 Analogue Design Kit Layout PCell for ELT transistors LVS deck that recognizes ELT transistors and computes proper L and W An excel sheet to compute W/L given ELT layout dimensions Further development will target: Cleaned-up the SKILL code (sklint) Support for custom symbol (CDF) with TID parameter for simulation Support for LVT transistors
30 Test Vehicles (1/2) (1) Analogue Characterization Contains active and passive devices for characterization, including radiation tolerance (2) Digital Characterization Contains all new or modified digital cell elements for (re-) characterization, including radiation tolerance
31 Devices Test Vehicle
32 Library Test Vehicle
33 Test Vehicles (2/2) (3) DSP - Xentium VLIW DSP Core - Network on chip - SpaceWire I/F w/ RMAP - Bridges for external ADC/DAC Demonstration of Development Flow and tool compatibility
34 Questions?
35 DARE+ Design Against Radiation Effects (Digital) Cell Libraries Jupiter Icy Moons Explorer (JUICE) Instruments Workshop 9 November 2011
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