MB86R01 Jade PCB Design Guide

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1 Application Note MB86R01 Jade PCB Design Guide Fujitsu Microelectronics Europe GmbH History Date Author Version Comment AvT 1.0 Draft version AvT 2.0 Updated using Japanese Guide 2.0. Changed R1/R2 values in Vref Considerations. Changed capacitor recommendations. 1

2 Warranty and Disclaimer To the maximum extent permitted by applicable law, Fujitsu Microelectronics GmbH restricts its warranties and its liability for all products delivered free of charge (e.g. software include or header files, application examples, Application Notes, target boards, evaluation boards, engineering samples of IC s etc.), its performance and any consequential damages, on the use of the Product in accordance with (i) the terms of the License Agreement and the Sale and Purchase Agreement under which agreements the Product has been delivered, (ii) the technical descriptions and (iii) all accompanying written materials. In addition, to the maximum extent permitted by applicable law, Fujitsu Microelectronics GmbH disclaims all warranties and liabilities for the performance of the Product and any consequential damages in cases of unauthorised decompiling and/or reverse engineering and/or disassembling. Note, all these products are intended and must only be used in an evaluation laboratory environment. 1. Fujitsu Microelectronics GmbH warrants that the Product will perform substantially in accordance with the accompanying written materials for a period of 90 days form the date of receipt by the customer. Concerning the hardware components of the Product, Fujitsu Microelectronics GmbH warrants that the Product will be free from defects in material and workmanship under use and service as specified in the accompanying written materials for a duration of 1 year from the date of receipt by the customer. 2. Should a Product turn out to be defect, Fujitsu Microelectronics GmbH s entire liability and the customer s exclusive remedy shall be, at Fujitsu Microelectronics GmbH s sole discretion, either return of the purchase price and the license fee, or replacement of the Product or parts thereof, if the Product is returned to Fujitsu Microelectronics GmbH in original packing and without further defects resulting from the customer s use or the transport. However, this warranty is excluded if the defect has resulted from an accident not attributable to Fujitsu Microelectronics GmbH, or abuse or misapplication attributable to the customer or any other third party not relating to Fujitsu Microelectronics GmbH. 3. To the maximum extent permitted by applicable law Fujitsu Microelectronics GmbH disclaims all other warranties, whether expressed or implied, in particular, but not limited to, warranties of merchantability and fitness for a particular purpose for which the Product is not designated. 4. To the maximum extent permitted by applicable law, Fujitsu Microelectronics GmbH s and its suppliers liability is restricted to intention and gross negligence. NO LIABILITY FOR CONSEQUENTIAL DAMAGES To the maximum extent permitted by applicable law, in no event shall Fujitsu Microelectronics GmbH and its suppliers be liable for any damages whatsoever (including but without limitation, consequential and/or indirect damages for personal injury, assets of substantial value, loss of profits, interruption of business operation, loss of information, or any other monetary or pecuniary loss) arising from the use of the Product. Should one of the above stipulations be or become invalid and/or unenforceable, the remaining stipulations shall stay in full effect. 2

3 Table of Contents 0 Introduction External Interface Orientation Power Net Design Capacitor Recommendation Vref Considerations Power wiring Recommended Power ON/OFF Sequence Power ON Reset PCB Laminating Recommended DDR Memories Memory Interface Recommendations Signal Grouping Resistors Wiring Distances Differential Impedance Wiring Topology Spice Simulation Results CLK Group DQS0-3 Group DATA0-3 Group CMD Group

0 Introduction This design guide describes design restrictions and recommendations regarding signal wiring (especially to external memory devices) and the electrical power system of the Graphic

4 0 Introduction This design guide describes design restrictions and recommendations regarding signal wiring (especially to external memory devices) and the electrical power system of the Graphic Controller MB86R01 Jade. For more details about the device features and it s relevant settings, please refer to the MB86R01 Hardware Manual. When designing, please consider the specifications of your memory device supplier. 1 External Interface Orientation External connections from and to the Jade are roughly oriented as shown in the following diagram. Note that the recommended signal lengths for the DDR connections should be symmetrical. 4

5 2 Power Net Design 2.1 Capacitor Recommendation The power net structure of Jade consists of separate nets for 1.2V (Core), 1.8V (DDR-IO) and 3.3V (other IO). The following table indicates how to buffer the nets sufficiently. Net Voltage No of Recommended Capacitors Comment pins 100uF 10uF 1uF 0.1uF VSS 0V VDDI 1.2V VDDE 3.3V DDRVDE 1.8V For DDR VREF0,1 0.9V 1 each Refer to 'Vref Considerations' section below Place the 0.1uF and 1uF caps as close as possible to the PowerGND pins. The placement of the 10uF and 100uF capacitors is more liberal. For the 0.1uF and 1uF capacitors, we recommend the use of ceramic capacitors of size 1005 (1.0mm 0.5mm). Where board assembly conditions make the use of 1005 sized capacitors difficult, we recommend the use of 1608 sized components. In addition, use small ESL (Equivalent Series Inductance) devices where possible in order to decrease noise. You should verify your board design by simulations and measurements if you can not mount the number of capacitors as mentioned above Vref Considerations The general design of the Vref circuit should take the following points into consideration. 2.2 Power wiring If the overall noise conditions in the core power net are poor, the Jade device can malfunction. For optimal high frequency noise removal, please follow the guidelines in the following section for the best configuration of core power nets (using 0.1uF and 1uF components). The inductance value due to 5

6 wiring will be kept to a minimum and noise influences are avoided if the power nets are connected close to GND pins as shown. 2.3 Recommended Power ON/OFF Sequence Follow the power ON/OFF sequence as shown below: <ON>: VDDI (including internal, PLLVDD) > DDRVDE (external) > VDDE (external) > Signal <OFF>: Signal > VDDE (external) > DDRVDE (external) > VDDI (including internal, PLLVDD) Recommended Power ON/OFF Sequence (1) There is no limitation on the sequence of the power ON/OFF of VDDI, VDDE, and DDRVDE if the following condition is met. (Fig 1 2) Do not apply VDDE and DDRVDE (external) more than a second continuously when VDDI (internal) is OFF. 6

7 Recommended Power ON/OFF Sequence (2) Perform power ON/OFF for VREF according to the DDR2-SDRAM regulation. Perform power ON/OFF so that power for PLLVDD (PLL) does not exceed VDDI. Turn ON all powers. Turning some powers ON is prohibited. The CMOS IC is unstable immediately after power ON. Perform a reset immediately. Set the reset pins (XTRST, XRST) to Low when power ON. Input a clock to CLK pin immediately after power ON. It requires at least 100 clocks of CLK pin (PLL reference clock) for the reset signal L applied to the XRST pin to be transmitted to all the internal circuits. 2.4 Power ON Reset Follow the power ON/OFF sequence as shown below: Recommended Power ON Sequence Input the XTRST, XRST, pins to Low when power ON. Keep the XTRST and XRST pins High after inputting Low level for 2 us or more. Access the registers other or memory controller after PLL LockUp Time. 7

8 3 PCB Laminating The following tables show recommended laminating conditions of the PCB at a signal impedance of 50 Ohms. The recommended conditions for 6 and 8-layers are shown. Please take crosstalk (Xtalk) into consideration when selecting the laminate. 6 layer base plate: Layer Material Thickness µm L1 L2 Copper foil + plating prepreg (preimpregnated fibres) Copper foil core material Classification Zo Ohm (*1) Xtalk % (*2) Tpd ps/cm SIG. 55Ω 8% 65ps/cm V/G L3 Copper foil prepreg (*3) SIG. 54Ω 8% 69ps/cm L4 Copper foil core material SIG. 54Ω 8% 69ps/cm L5 Copper foil prepeg V/G L6 Copper foil + plating SIG. 55Ω 8% 65ps/cm Total = 1844 µm 8 layer base plate: Layer Material Thickness µm L1 Copper foil + plating prepreg 100 Classification Zo Xtalk Tpd Ohm *1 % *2 ps/cm SIG. 55Ω 8% 65ps/cm L2 Copper foil core material V/G L3 Copper foil prepreg (*3) SIG. 53Ω 6% 69ps/cm L4 Copper foil core material V/G L5 Copper foil prepeg (*3) SIG 54Ω 7% 69ps/cm L6 Copper foil core material SIG. 54Ω 7% 69ps/cm L7 Copper foil prepeg V/G L8 Copper foil + plating SIG. 55Ω 8% 65ps/cm Total = 2014 µm 8

9 Notes The thickness of the copper foil is 35µm but 18µm can also be used without problems. Note however, that in the case of 18µm, Zo will increase by about 2-3 Ohms and crosstalk will be reduced by about 1%. *1: Based on a pattern spacing of 100µm and base plate material FR-4 (Er=4.3) *2: Based on pattern spacing of 100µm and base plate material FR-4 (Er=4.3) and in connection with pattern spacing of 400um the crosstalk saturation is doubled *3: Change the board thickness in this case. Increase the spacing to more than 400um between L3 and L4. If the spacing is under 400um between L3 and L4, try to avoid parallel wiring! 4 Recommended DDR Memories This section lists some DDR memory devices which can be used for Jade s DDR interface. Other similar types can of course be used as well if the interface is identical and other relevant parameters for the application (e.g. temperature range, speed grade etc.) are fulfilled. Note that the devices marked with * are memory types which are recommended and used for simulation in this guideline. Elpida Corporation: EDE5116AFSE (32M words x 16 bits and FBGA-84 Lead-free RoHS compliant) Please refer to the DRAM manufacturer s specifications for details on the listed device (for example temperature specifications etc.). 9

10 5 Memory Interface Recommendations 5.1 Signal Grouping The following table lists the IO connections of the Jade DDR memory. The DDR Interface is classified in the following 10 groups for simplification purposes. Signal Group Group Name IO pin names 1 CLK MCKN MCKP 2 DQS0 MDQSN[0] MDQSP[0] 3 DQS1 MDQSN[1] MDQSP[1] 4 DQS2 MDQSN[2] MDQSP[2] 5 DQS3 MDQSN[3] MDQSP[3] 6 DATA0 MDQ[0]-[7] MDM[0] 7 DATA1 MDQ[8]-[15] MDM[1] 8 DATA2 MDQ[16]-[23] MDM[2] 9 DATA3 MDQ[24]-[31] MDM[3] 10 CMD MA0-13 MWE MBA0-1 MCKE MRAS MCS MCAS Signal impedance of wiring should be 50 Ω. In case of the layer constitution which is shown, wiring width is 100µm. Connections to Vcc/GND plates should be able to guarantee sufficient current. For the differential signals of the CLK and DQS0-3 groups, please use parallel wiring. In addition, also take care that the position and number of layer vias is the same. Try to keep the number of layer vias as low as possible. Signal wiring is recommended in the inner layer in order to decrease EMI and crosstalk (especially for the CLK group). The recommended conditions and the simulation ripple mark which are shown later in this document are valid under the above-mentioned conditions. If big differences to the above-mentioned conditions occur, please examine your wiring precisely. 5.2 Resistors The E12 resistor series should be used for the selection of resistors used in your design. For those (higher precision) resistor values that are not available in the E12 series, use components from the E24 series. E12 factor line: 10, 12, 15, 18, 22, 27, 33, 39, 47, 56, 68, 82 E24 factor line: 10, 11, 12, 13, 15, 16, 18, 20, 22, 24, 27, 30, 33, 36, 39, 43, 47, 51, 56, 62, 68, 75, 82, 91 For resistor tolerances, please select components that generally match as follows: Damping resistance: Below ±5% Terminal resistance: Below ±5% Termination voltage VTT and the division resistance for VREF: Below ±1% 10

11 Terminal Resistors The use of terminal resistors is recommended, but a design without terminal resistances can also be achieved if enough experience is available. Please refer to the following table for resistance values in each case. The listed values are calculated to match the wiring impedance. Signal Group Group Name Terminal resistance on PCB Damping value of resistance Rd Length of wire to Jade output (SDRAM input) Approved length of wire inside group variation 1 CLK 200 Ω 0 Ω 20 ~ 50 mm - 2 DQS0-22 Ω 20 ~ 50 mm - 3 DQS1-22 Ω 20 ~ 50 mm - 4 DQS2-22 Ω 20 ~ 50 mm - 5 DQS3-22 Ω 20 ~ 50 mm - 6 DATA0-22 Ω 20 ~ 50 mm 5 mm 7 DATA1-22 Ω 20 ~ 50 mm 5 mm 8 DATA2-22 Ω 20 ~ 50 mm 5 mm 9 DATA3-22 Ω 20 ~ 50 mm 5 mm 10 CMD - 22 Ω 20 ~ 50 mm 10 mm Overview of damping value of resistance / length of wire Number Group Name Approved length of wire dispersion between groups 1 DQS0 to DATA0 group 5 mm 2 DQS1 to DATA1 group 5 mm 3 DQS2 to DATA2 group 5 mm 4 DQS3 to DATA3 group 5 mm Approved length of wire dispersion between groups 5.3 Wiring Distances In order to avoid too much crosstalk between the memory signals and to avoid consequent data corruption, the below design conditions are recommended for the Jade to DDR connection. Distance of all signals within the same group excluding the CLK and DQS0-3 groups should be > 300µm Distance of signals of the other groups should be > 500µm 11

12 The distance of CLK and DQS0-3 groups to other signals should be > 1000µm. Where it is difficult to guarantee a gap over 1000um, separate these signals from others using GND areas (however, please take the decrease of the wiring impedance into consideration). Notes: Crosstalk may occur between different layers if these use wiring which runs in parallel, especially between the top and bottom layers. Please avoid this at all costs. Be cautious when wiring impedance is higher than 50 Ohms as crosstalk noise increases substantially. Then it is necessary to increase the wiring pitch shown in the description. 5.4 Differential Impedance A differential impedance Zdiff=100Ω is recommended for differential signal groups CLK and DQS0-3. The below diagram shows the relevant conditions. 12

13 5.5 Wiring Topology The signal wiring topologies for the different configurations are illustrated below. CLK Group: Using 2 DDR devices without terminal resistors: DSQ0-3 Group: 13

14 DATA0-3 Group: CMD Group: 14

5.6 Spice Simulation Results Based on the DDR interface recommendation in this design guide, a SPICE ripple simulation is shown for some signals as reference.

15 5.6 Spice Simulation Results Based on the DDR interface recommendation in this design guide, a SPICE ripple simulation is shown for some signals as reference. Concerning process, temperature and voltage everything was conducted with typical values. The diagrams show DDR pin edge ripple marks (DDR pin side) CLK Group CLK Group simulation ripple mark Max condition Green: Length of wire 20mm before divergence Red: Length of wire 30mm before the divergence Blue: Length of wire 40mm before the divergence After divergence all 20mm fixing 15

16 CLK Group simulation ripple mark Typ condition Green: Length of wire 20mm before divergence Red: Length of wire 30mm before the divergence Blue: Length of wire 40mm before the divergence After divergence all 20mm fixing CLK Group simulation ripple mark Min condition 16

Green: Length of wire 20mm before divergence Red: Length of wire 30mm before the divergence Blue: Length of wire 40mm before the divergence After divergence all 20mm fixing 5.6.

17 Green: Length of wire 20mm before divergence Red: Length of wire 30mm before the divergence Blue: Length of wire 40mm before the divergence After divergence all 20mm fixing DQS0-3 Group DQS0-3_Group Write simulation ripple mark Max condition Green: Length of wire 20mm to of damping resistance ~DDR Red: Length of wire 30mm to of damping resistance ~DDR Blue: Length of wire 40mm to of damping resistance ~DDR (As for length of wire to JADE~ damping resistance 10mm fixing) 17

18 DQS0-3_Group Write simulation ripple mark Typ condition Green: Length of wire 20mm to of damping resistance ~DDR Red: Length of wire 30mm to of damping resistance ~DDR Blue: Length of wire 40mm to of damping resistance ~DDR (As for length of wire to JADE~ damping resistance 10mm fixing) DQS0-3_Group Write simulation ripple mark Min condition Green: Length of wire 20mm to of damping resistance ~DDR Red: Length of wire 30mm to of damping resistance ~DDR Blue: Length of wire 40mm to of damping resistance ~DDR (As for length of wire to JADE~ damping resistance 10mm fixing) 18

19 DQS0-3_Group Read simulation ripple mark Max condition Green: Length of wire 20mm to of damping resistance ~DDR Red: Length of wire 30mm to of damping resistance ~DDR Blue: Length of wire 40mm to of damping resistance ~DDR (As for length of wire to JADE~ damping resistance 10mm fixing) DQS0-3_Group Read simulation ripple mark Typ condition Green: Length of wire 20mm to of damping resistance ~DDR Red: Length of wire 30mm to of damping resistance ~DDR Blue: Length of wire 40mm to of damping resistance ~DDR 19

(As for length of wire to JADE~ damping resistance 10mm fixing) DQS0-3_Group Read simulation ripple mark Min condition Green: Length of wire 20mm to of damping resistance ~DDR Red:

20 (As for length of wire to JADE~ damping resistance 10mm fixing) DQS0-3_Group Read simulation ripple mark Min condition Green: Length of wire 20mm to of damping resistance ~DDR Red: Length of wire 30mm to of damping resistance ~DDR Blue: Length of wire 40mm to of damping resistance ~DDR (As for length of wire to JADE~ damping resistance 10mm fixing) DATA0-3 Group 20

21 DATA0-3_Group Write simulation ripple mark Max condition Green: Length of wire 20mm to of damping resistance ~DDR Red: Length of wire 30mm to of damping resistance ~DDR Blue: Length of wire 40mm to of damping resistance ~DDR (As for length of wire to of damping resistance ~DDR all 20mm fixing) DATA0-3_Group Write simulation ripple mark Typ condition Green: Length of wire 20mm to of damping resistance ~DDR 21

22 Red: Length of wire 30mm to of damping resistance ~DDR Blue: Length of wire 40mm to of damping resistance ~DDR (As for length of wire to of damping resistance ~DDR all 20mm fixing) DATA0-3_Group Write simulation ripple mark Min condition Green: Length of wire 20mm to of damping resistance ~DDR Red: Length of wire 30mm to of damping resistance ~DDR Blue: Length of wire 40mm to of damping resistance ~DDR (As for length of wire to of damping resistance ~DDR all 20mm fixing) 22

23 DATA0-3_Group Read simulation ripple mark Max condition Green: Length of wire 20mm to of damping resistance ~DDR Red: Length of wire 30mm to of damping resistance ~DDR Blue: Length of wire 40mm to of damping resistance ~DDR (As for length of wire to of damping resistance ~DDR all 20mm fixing) DATA0-3_Group Read simulation ripple mark Typ condition Green: Length of wire 20mm to of damping resistance ~DDR Red: Length of wire 30mm to of damping resistance ~DDR Blue: Length of wire 40mm to of damping resistance ~DDR (As for length of wire to of damping resistance ~DDR all 20mm fixing) 23

24 DATA0-3_Group Read simulation ripple mark Min condition Green: Length of wire 20mm to of damping resistance ~DDR Red: Length of wire 30mm to of damping resistance ~DDR Blue: Length of wire 40mm to of damping resistance ~DDR (As for length of wire to of damping resistance ~DDR all 20mm fixing) CMD Group CMD Group simulation ripple mark Max condition 24

25 Green: To damping resistant ~ turning point, length of wire 20mm to of turning point ~DDR Red: To damping resistant ~ turning point, length of wire 30mm to of turning point ~DDR Blue: To damping resistant ~ turning point, length of wire 40mm to of turning point ~DDR (As for the length of wire to JADE~DDR all 10mm fixing) CMD Group simulation ripple mark Typ condition Green: To damping resistant ~ turning point, length of wire 20mm to of turning point ~DDR Red: To damping resistant ~ turning point, length of wire 30mm to of turning point ~DDR Blue: To damping resistant ~ turning point, length of wire 40mm to of turning point ~DDR (As for the length of wire to JADE~DDR all 10mm fixing) 25

26 CMD Group simulation ripple mark Min condition Green: To damping resistant ~ turning point, length of wire 20mm to of turning point ~DDR Red: To damping resistant ~ turning point, length of wire 30mm to of turning point ~DDR Blue: To damping resistant ~ turning point, length of wire 40mm to of turning point ~DDR (As for the length of wire to JADE~DDR all 10mm fixing) 26

Manufacturing Facility is ISO9001:2000. Welded Steel Pipe Conform to ASTM A53. Threads Conform to ASME B1.20.1

STEEL NIPPLES S40 & S80 Steel Nipple Product Specifications Manufacturing Facility is ISO9001:2000 Welded Steel Pipe Conform to ASTM A53 Threads Conform to ASME B1.20.1 800-678-2544 800-678-0857 www.msi-products.com