Field Programmable Gate Arrays a Case Study

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1 Designing an Application for Field Programmable Gate Arrays a Case Study Bernd Däne Bernd.Daene@tu-ilmenau.de de Technische Universität Ilmenau

2 Topics 1. Introduction and Goals 2. Project and Methods 3. Modeling Process 4. Transforming and Logic Synthesis 5. Results 6. Conclusion This work has been supported by German Research Foundation (Deutsche Forschungsgemeinschaft, DFG) under grant SFB 622. Some figures are taken from Matlab/Simulink (The MathWorks Incorporated) and Quartus II (Altera Corporation). Designing an Application for Field Programmable Gate Arrays a Case Study 2

3 1. Introduction and Goals FPGA (Field Programmable Gate Array) application Model Based Design: High and low modeling levels Using commercial tools in combination Case study within a large research project Contribution to more general design methodology Designing an Application for Field Programmable Gate Arrays a Case Study 3

4 2. Project and Methods Fast communication system for multiple DSP (Digital Signal Processors) Communication managed by FPGA (one per node) Fast serial communication principle: LVDS (Low Voltage Differential Signaling) Frame based routing protocol Topology: actually three-node unidirectional ring Designing an Application for Field Programmable Gate Arrays a Case Study 4

5 General System Structure Designing an Application for Field Programmable Gate Arrays a Case Study 5

6 Tools and Design Flow Higher levels: Matlab/Simulink Transformation: Simulink HDL Coder Lower levels: Altera Quartus II Additional validation: Mentor Graphics ModelSim Target devices: Altera Cyclone II family (EP2C8) Some names are registered as trademarks. Designing an Application for Field Programmable Gate Arrays a Case Study 6

7 3. Modeling Process Highest level resembles system structure Additional resources for simulation: Stimuli: Data generators, general timing Measurement: Data checkers Other: Channel error models Designing an Application for Field Programmable Gate Arrays a Case Study 7

8 Top Level System (simplified) Designing an Application for Field Programmable Gate Arrays a Case Study 8

9 Node model Node functionality defined and refined in Simulink model Combines structural models and statecharts Includes resources such as RAM blocks Uses a subset of Simulink blocks only (limitation of transformation component) Some interface parts will be added later Designing an Application for Field Programmable Gate Arrays a Case Study 9

10 Structure of one FPGA Node EMIF: External Memory Interface (local DSP bus) Designing an Application for Field Programmable Gate Arrays a Case Study 10

11 Data Buffer Detail Figure from Matlab/Simulink model, partly shown. Designing an Application for Field Programmable Gate Arrays a Case Study 11

12 4. Transforming and Logic Synthesis Logic synthesis: Device manufacturer s tool (Quartus II) Transfer format: VHDL (Very High Speed Integrated Circuit Hardware Description Language) Important function: Module inference E.g. using prebuilt RAM blocks Designing an Application for Field Programmable Gate Arrays a Case Study 12

13 Limitations and Human Intervention Module inference: Clock configuration details may prevent detection Solution: user-generated control files Interfaces: Manual completion needed Pin assignments and clock sources LVDS circuitry Bidirectional busses Subject to methodical improvement Designing an Application for Field Programmable Gate Arrays a Case Study 13

14 FPGA to EMIF Interface Detail Figure from Quartus II model, partly shown. Designing an Application for Field Programmable Gate Arrays a Case Study 14

15 5Results 5. Simulation results at high level, single node: Protocol validation Bus cycle timings Full system: Packet routing Error detection and correction Massive load situations Designing an Application for Field Programmable Gate Arrays a Case Study 15

16 Simulation Output Examples EMIF Write Cycle EMIF Read Cycle Figures from Matlab/Simulink output. Designing an Application for Field Programmable Gate Arrays a Case Study 16

17 Simulation Frame Error Statistics Statistics for bit error rate 0.1%. Correctable errors are not shown. Frame characteristics Per hop count 1 hop 2 hops Total Frames total Frames with detected errors Frames with nondetected errors Header frames Data frames Header frames Data frames Header frames Data frames Designing an Application for Field Programmable Gate Arrays a Case Study 17

18 Simulation at lower levels Quartus simulation component: Checking manually added interface functions Checking final timing constraints Full system simulation not practical at this level ModelSim: Checking VHDL transfer files for occasional losses and other transfer problems Designing an Application for Field Programmable Gate Arrays a Case Study 18

19 6Conclusion 6. Case study for a complex design process Evaluation of tool interaction Issues that require human intervention Problems for automated design processes identified Designing an Application for Field Programmable Gate Arrays a Case Study 19

20 Further Work Hardware implementation (in preparation) More nodes, other topologies Higher communication protocol levels Design methodology improvements: Rules Tools Strategies addressing critical points Designing an Application for Field Programmable Gate Arrays a Case Study 20

21 Thank you for your attention. Designing an Application for Field Programmable Gate Arrays a Case Study 21

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