ICTP Latin-American Advanced Course on FPGADesign for Scientific Instrumentation. 19 November - 7 December, 2012

Transcription

1 ICTP Latin-American Advanced Course on FPGADesign for Scientific Instrumentation 19 November - 7 December, 2012 Clock domains multiple FPGA design KLUGE Alexander PH ESE FE Division CERN 385, rte Meyrin, CH-1211 Geneva 23 SWITZERLAND

2 Clock domains multiple FPGA design

3 Clock distribution: multiple FPGAs clk fpga0 fpga1 T clocktooutput < T period/2 different loading on clock drivers T setup < T period/2 Main board daughter board

4 Clock distribution clk_main_fpga clk_fpga_int0 clk_board1 clk fpga0 fpga1 clk_board0 Main board clk_daughter clk_fpga_int1 data_main_daughter daughter board

5 clock distribution/t co & t s /board 0-> 1 clk clk_board0 clk_main_fpga clk_fpga_int0 clk_daughter clk_board1 clk_fpga_int1 data_main_daughter0 t clocktooutput t setup

6 Clock distribution clk_main_fpga clk_fpga_int0 clk_board1 clk fpga0 fpga1 clk_board0 Main board clk_daughter clk_fpga_int1 data_daughter_main daughter board

7 clock distribution/t co & t s /board 1-> 0 clk clk_board0 clk_main_fpga clk_fpga_int0 clk_daughter clk_board1 clk_fpga_int1 data_main_daughter0 t clocktooutput t setup

8 Clock distribution clk_main_fpga clk_fpga_int0 clk_board1 clk fpga0 fpga1 clk_board0 Main board clk_daughter clk_fpga_int1 data_main_daughter daughter board

9 clock distribution/slow output board 0->1 clk clk_board0 clk_main_fpga clk_fpga_int0 clk_daughter clk_board1 clk_fpga_int1 data_main_daughter t clocktooutput t setup t hold

10 clock distribution/fast output board 0->1 clk clk_board0 clk_main_fpga clk_fpga_int0 clk_daughter clk_board1 clk_fpga_int1 data_main_daughter t clocktooutput

11 Clock distribution clk_main_fpga clk_fpga_int0 clk_board1 clk fpga0 fpga1 clk_board0 Main board clk_daughter clk_fpga_int1 data_daughter_main daughter board

12 clock distribution/fast output board 1-> 0 clk clk_board0 clk_main_fpga clk_fpga_int0 clk_daughter clk_board1 clk_fpga_int1 data_daughter_main t clocktooutput t setup t hold

13 clock distribution/slow output board 1-> 0 clk clk_board0 clk_main_fpga clk_fpga_int0 clk_daughter clk_board1 clk_fpga_int1 data_daughter_main t clocktooutput

14 Constraints Fulfilling FPGA internal constraints is not sufficient. Perform system simulations Logic can be too fast

15 Data selection & delay

16 Data selection and delay collision particle detector electronics L0 Trigger 100 Tbyte/s Event builder L2 Trigger 100 Gbyte/s data storage 100 Mbyte/s

17 Data selection and delay Data (20 bits) every * 100 ns collision -> L0 (1µs) collision -> L2y or L2n (100 µs) data L0 L2yn datadelayed

18 Data selection and delay Data (20 bits) every * 100 ns collision -> L0 (1µs) collision -> L2y or L2n (100 µs) Options: Data pipeline until L2 with FIFO based on shift 10 MHz 20 bits * 100 µs / 100 ns 20 bits * 1000 = bits

19 Data selection and delay Data pipeline with FIFO with shift 10 MHz 20 bits * 1000 = bits bits in logic cells are used

20 Data selection and delay Data pipeline with FIFO based on dual port 10 MHz 20 bits * 1000 = bits counter +fifo_depth delay adder addr_in data_in dual port RAM addr_out data_out FPGAs have RAM cells in addition to logic blocks

21 Data selection and delay counter adder delay = 9 Data pipeline with 2 FIFOs based on dual port RAM@ 10 MHz: 20 bits * bits * 8 = 360 bits addr_in addr_out dual port RAM data_in data_out L0 L2 counter write_pointer addr_in addr_out write_enable dual port RAM read_enable data_in data_out counter read_pointer

22 Data selection and delay

23 Data selection and delay

24 Data selection and delay

25 Data selection and delay

26 Data selection and delay

27 Data selection and delay

28 Data selection and delay

29 Data selection and delay

30 Data selection and delay

31 Data selection and delay

32 Data selection and delay

33 Data selection and delay

34 Data selection and delay

35 Data selection and delay

36 Data selection and delay

37 System level simulation

38 6 x 10 6 x System level simulation 3 x 1 x 60 ASICs: simplified behavioral 40 ASICs: full behavioral 5 FPGA: full behavioral 7 SRAMs: full behavioral 4 PCBs

39 What happens if we have speed problems? Often because of inadequate logic architecture/coding style evaluate logic architecture rewrite HDL code to adapt structure to better data throughput insert pipeline structure - often one clock cycle more latency does not matter Understand the specifications look for systematics which can help to simplify logic adapt architecture and schematics/code only then optimize placing & routing

40 What happens if we have speed problems? Often because of components too small and routing congestion timing constraints Routing constraint - placement constraint Use bigger/faster component

41 Conclusion FPGA application at CERN data selection/trigger (muon track finder trigger) data processing (pixel detector) Design cycle Defining Specifications Clock domains Data delay

42 Additional slides