PPEP: ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK
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1 PPEP: ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK BO SU JUNLI GU LI SHEN WEI HUANG JOSEPH L. GREATHOUSE ZHIYING WANG NUDT AMD RESEARCH DECEMBER 17, 2014
2 BACKGROUND Dynamic Voltage and Frequency Scaling (DVFS) Widely employed Boost performance, lower power, and improve energy efficiency 2 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
3 BACKGROUND Dynamic Voltage and Frequency Scaling (DVFS) Widely employed Boost performance, lower power, and improve energy efficiency Good DVFS decisions require Accurate performance & power predictions across Voltage Frequency (VF) states 3 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
4 BACKGROUND Dynamic Voltage and Frequency Scaling (DVFS) Widely employed Boost performance, lower power, and improve energy efficiency Good DVFS decisions require Accurate performance & power predictions across Voltage Frequency (VF) states Challenges Brought by Modern Processors Cores and north bridge Different clock domains and power planes Off-chip Memory Own clock domain 4 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
5 TWO QUESTIONS Q1: How does the application s performance change with the VF state? Q2: How does the application s power change with the VF state? 5 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
6 EXPERIMENTAL SETUP PLATFORM & BENCHMARKS Processor: AMD FX nd Generation Family 15h Piledriver FX-8320 CPU 6 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
7 EXPERIMENTAL SETUP PLATFORM & BENCHMARKS CU CU Processor: AMD FX nd Generation Family 15h Piledriver 4 CUs (Compute Units) 2 Cores in a CU 5 VF (Voltage-Frequency) states FX-8320 CPU CU CU 7 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
8 EXPERIMENTAL SETUP PLATFORM & BENCHMARKS Processor: AMD FX nd Generation Family 15h Piledriver 4 CUs (Compute Units) 2 Cores in a CU 5 VF (Voltage-Frequency) states The NB (North Bridge) Shared by all CUs L3$ and memory controller CU North Bridge CU FX-8320 CPU CU CU 8 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
9 EXPERIMENTAL SETUP PLATFORM & BENCHMARKS Processor: AMD FX nd Generation Family 15h Piledriver 4 CUs (Compute Units) 2 Cores in a CU 5 VF (Voltage-Frequency) states The NB (North Bridge) Shared by all CUs L3$ and memory controller Power Measurement Pololu ACS711: Current sensor Power Supply CU North Bridge CU FX-8320 CPU ACS711 CU CU ASUS M5A97 9 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
10 EXPERIMENTAL SETUP PLATFORM & BENCHMARKS CU CU Processor: AMD FX nd Generation Family 15h Piledriver 4 CUs (Compute Units) 2 Cores in a CU 5 VF (Voltage-Frequency) states The NB (North Bridge) Shared by all CUs L3$ and memory controller Power Measurement Pololu ACS711: Current sensor Arduino: Power reading Power Supply North Bridge CU FX-8320 CPU ACS711 CU ASUS M5A97 Arduino 10 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
11 EXPERIMENTAL SETUP PLATFORM & BENCHMARKS CU CU Processor: AMD FX nd Generation Family 15h Piledriver 4 CUs (Compute Units) 2 Cores in a CU 5 VF (Voltage-Frequency) states The NB (North Bridge) Shared by all CUs L3$ and memory controller Power Measurement Pololu ACS711: Current sensor Arduino: Power reading Benchmark Suites Power Supply North Bridge FX-8320 CPU ACS711 SPEC CPU 2006, PARSEC, NAS Parallel Arduino Benchmarks CU CU ASUS M5A97 11 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
12 OUTLINE Background Experimental Setup Performance Prediction Across DVFS States Power Prediction Across DVFS States PPEP Framework Conclusion Q1: How does the application s performance change with the VF state? 12 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
13 Normalized CPI HOW CPI CHANGES WITH FREQUENCY (LOWER IS BETTER) Normalized Frequency 13 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
14 Normalized CPI HOW CPI CHANGES WITH FREQUENCY (LOWER IS BETTER) Estimate #1 CPI does not change when frequency increases Normalized Frequency bzip2 14 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
15 Normalized CPI HOW CPI CHANGES WITH FREQUENCY (LOWER IS BETTER) Estimate #1 Estimate #2 CPI does not change when frequency increases. CPI also increases when frequency increases mcf Normalized Frequency bzip2 15 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
16 Normalized CPI HOW CPI CHANGES WITH FREQUENCY (LOWER IS BETTER) Estimate #1 Estimate #2 CPI does not change when frequency increases. CPI also increases when frequency increases mcf Normalized Frequency GAP bzip2 16 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
17 WHAT MAKES THE CPI DIFFERENCE? bzip2 Core L3+DRAM Core clock cycles 17 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
18 WHAT MAKES THE CPI DIFFERENCE? bzip2 Core L3+DRAM Core clock cycles Cycles working in the CPU Core. Core Frequency doesn t matter. 18 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
19 WHAT MAKES THE CPI DIFFERENCE? bzip2 Core L3+DRAM mcf Core L3+DRAM Core clock cycles Cycles working in the CPU Core. Core Frequency doesn t matter. 19 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
20 WHAT MAKES THE CPI DIFFERENCE? bzip2 Core L3+DRAM mcf Core L3+DRAM Core clock cycles Cycles working in the CPU Core. Core Frequency doesn t matter. Cycles stalled on Memory Accessing. Scale with Core Frequency. 20 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
21 WHAT MAKES THE CPI DIFFERENCE? bzip2 Core L3+DRAM mcf Core L3+DRAM Core clock cycles Cycles working in the CPU Core. Core Frequency doesn t matter. Core Frequency: f -> f Cycles stalled on Memory Accessing. Scale with Core Frequency. 21 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
22 WHAT MAKES THE CPI DIFFERENCE? bzip2 Core L3+DRAM mcf Core L3+DRAM Core clock cycles Cycles working in the CPU Core. Core Frequency doesn t matter. Core Frequency: f -> f Does not scale. Does not scale. Cycles stalled on Memory Accessing. Scale with Core Frequency. 22 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
23 WHAT MAKES THE CPI DIFFERENCE? bzip2 Core L3+DRAM mcf Core L3+DRAM Core clock cycles Cycles working in the CPU Core. Core Frequency doesn t matter. Core Frequency: f -> f GAP Does not scale. Does not scale. Scales by f /f. Cycles stalled on Memory Accessing. Scale with Core Frequency. 23 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
24 WHAT MAKES THE CPI DIFFERENCE? bzip2 Core L3+DRAM mcf Core L3+DRAM Core clock cycles Cycles working in the CPU Core. Core Frequency doesn t matter. Core Frequency: f -> f GAP Does not scale. Does not scale. Scales by f /f. Cycles stalled on Memory Accessing. Scale with Core Frequency. Key: Memory Stall Cycles estimation 24 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
25 Core clock cycles Core L3+DRAM 25 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
26 Core clock cycles Core L3+DRAM 26 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
27 Core clock cycles Core L3+DRAM 27 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
28 Core clock cycles Core L3+DRAM 28 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
29 LEADING LOADS MEMORY TIME ESTIMATION [CF 10 Keramidas+], [TOC 10 Eyerman+], and [IGCC 11 Rountree+] Core clock cycles Core L3+DRAM 29 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
30 LEADING LOADS MEMORY TIME ESTIMATION [CF 10 Keramidas+], [TOC 10 Eyerman+], and [IGCC 11 Rountree+] Core clock cycles Core L3+DRAM Leading Load 30 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
31 LEADING LOADS MEMORY TIME ESTIMATION [CF 10 Keramidas+], [TOC 10 Eyerman+], and [IGCC 11 Rountree+] Core clock cycles Core L3+DRAM Leading Load Not Leading 31 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
32 LEADING LOADS MEMORY TIME ESTIMATION [CF 10 Keramidas+], [TOC 10 Eyerman+], and [IGCC 11 Rountree+] Core clock cycles Core L3+DRAM Leading Load Leading Load Not Leading 32 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
33 LEADING LOADS MEMORY TIME ESTIMATION [CF 10 Keramidas+], [TOC 10 Eyerman+], and [IGCC 11 Rountree+] Memory Stall Cycle Core clock cycles Memory Stall Cycles Core L3+DRAM Leading Load Leading Load Not Leading Leading Loads Model: Memory stall cycles = cycles that leading loads are active 33 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
34 LEADING LOADS MEMORY TIME ESTIMATION [CF 10 Keramidas+], [TOC 10 Eyerman+], and [IGCC 11 Rountree+] Memory Stall Cycle Core clock cycles Memory Stall Cycles Core L3+DRAM Leading Load Leading Load Not Leading Leading Loads Model: Memory stall cycles = cycles that leading loads are active AMD hardware has MAB0 performance counter which can estimate Leading Loads cycles. [USENIX-ATC 14 Su+] 34 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
35 CPI PREDICTOR 3 HW events Running Frequency = f Core L3 + DRAM # Code Event Name E1 0x76 CPU_Clocks_not_Halted E2 0xc0 Retired_Instructions E3 0x69 MAB0_Wait_Cycles MAB based Leading Loads Cycles Core clock cycles 35 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
36 CPI PREDICTOR 3 HW events Running Frequency = f Core L3 + DRAM # Code Event Name E1 0x76 CPU_Clocks_not_Halted E2 0xc0 Retired_Instructions E3 0x69 MAB0_Wait_Cycles MAB based Leading Loads Cycles Core clock cycles E1 36 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
37 CPI PREDICTOR 3 HW events Running Frequency = f Core L3 + DRAM # Code Event Name E1 0x76 CPU_Clocks_not_Halted E2 0xc0 Retired_Instructions E3 0x69 MAB0_Wait_Cycles MAB based Leading Loads Cycles Core clock cycles E3 E1 37 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
38 CPI PREDICTOR 3 HW events Running Frequency = f Core L3 + DRAM # Code Event Name E1 0x76 CPU_Clocks_not_Halted E2 0xc0 Retired_Instructions E3 0x69 MAB0_Wait_Cycles MAB based Leading Loads Cycles Core clock cycles E1-E3 E3 E1 38 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
39 CPI PREDICTOR 3 HW events Running Frequency = f Core L3 + DRAM # Code Event Name E1 0x76 CPU_Clocks_not_Halted E2 0xc0 Retired_Instructions E3 0x69 MAB0_Wait_Cycles MAB based Leading Loads Cycles Core clock cycles E1-E3 E3 Instruction number = E2 E1 39 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
40 CPI PREDICTOR 3 HW events Running Frequency = f Core L3 + DRAM # Code Event Name E1 0x76 CPU_Clocks_not_Halted E2 0xc0 Retired_Instructions E3 0x69 MAB0_Wait_Cycles MAB based Leading Loads Cycles Core clock cycles E1-E3 E3 Instruction number = E2 CPI(f) = E1/E2 E1 40 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
41 CPI PREDICTOR 3 HW events Running Frequency = f Core L3 + DRAM Another Frequency = f Core L3 + DRAM # Code Event Name E1 0x76 CPU_Clocks_not_Halted E2 0xc0 Retired_Instructions E3 0x69 MAB0_Wait_Cycles MAB based Leading Loads Cycles Core clock cycles E1-E3 E3 Instruction number = E2 CPI(f) = E1/E2 E1 41 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
42 CPI PREDICTOR 3 HW events Running Frequency = f Core L3 + DRAM Another Frequency = f Core L3 + DRAM # Code Event Name E1 0x76 CPU_Clocks_not_Halted E2 0xc0 Retired_Instructions E3 0x69 MAB0_Wait_Cycles MAB based Leading Loads Cycles Core clock cycles E1-E3 E3 Instruction number = E2 CPI(f) = E1/E2 E1 E1-E3 42 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
43 CPI PREDICTOR 3 HW events Running Frequency = f Core L3 + DRAM Another Frequency = f Core L3 + DRAM # Code Event Name E1 0x76 CPU_Clocks_not_Halted E2 0xc0 Retired_Instructions E3 0x69 MAB0_Wait_Cycles MAB based Leading Loads Cycles Core clock cycles E1-E3 E3 Instruction number = E2 CPI(f) = E1/E2 E1 E1-E3 E3*(f /f) 43 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
44 CPI PREDICTOR 3 HW events Running Frequency = f Core L3 + DRAM Another Frequency = f Core L3 + DRAM # Code Event Name E1 0x76 CPU_Clocks_not_Halted E2 0xc0 Retired_Instructions E3 0x69 MAB0_Wait_Cycles MAB based Leading Loads Cycles Core clock cycles E1-E3 E3 Instruction number = E2 CPI(f) = E1/E2 E1 E1-E3 E3*(f /f) E1+E3*(f /f - 1) 44 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
45 CPI PREDICTOR 3 HW events Running Frequency = f Core L3 + DRAM Another Frequency = f Core L3 + DRAM # Code Event Name E1 0x76 CPU_Clocks_not_Halted E2 0xc0 Retired_Instructions E3 0x69 MAB0_Wait_Cycles MAB based Leading Loads Cycles Core clock cycles E1-E3 E3 Instruction number = E2 CPI(f) = E1/E2 E1 E1-E3 E3*(f /f) Instruction number = E2 E1+E3*(f /f - 1) 45 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
46 CPI PREDICTOR 3 HW events Running Frequency = f Core L3 + DRAM Another Frequency = f Core L3 + DRAM # Code Event Name E1 0x76 CPU_Clocks_not_Halted E2 0xc0 Retired_Instructions E3 0x69 MAB0_Wait_Cycles MAB based Leading Loads Cycles Core clock cycles E1-E3 E3 Instruction number = E2 CPI(f) = E1/E2 E1 E1-E3 E3*(f /f) Instruction number = E2 CPI(f ) = (E1+E3*(f /f - 1))/E2 E1+E3*(f /f - 1) 46 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
47 CPI PREDICTOR 3 HW events Running Frequency = f Core L3 + DRAM Another Frequency = f Core L3 + DRAM # Code Event Name E1 0x76 CPU_Clocks_not_Halted E2 0xc0 Retired_Instructions E3 0x69 MAB0_Wait_Cycles MAB based Leading Loads Cycles Core clock cycles E1-E3 E3 E1 E1-E3 E3*(f /f) E1+E3*(f /f - 1) Instruction number = E2 CPI(f) = E1/E2 LL-MAB CPI Predictor Instruction number = E2 CPI(f ) = (E1+E3*(f /f - 1))/E2 47 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
48 CPI PREDICTOR 3 HW events Step=200ms Running Frequency = f Core L3 + DRAM Another Frequency = f Core L3 + DRAM # Code Event Name E1 0x76 CPU_Clocks_not_Halted E2 0xc0 Retired_Instructions E3 0x69 MAB0_Wait_Cycles MAB based Leading Loads Cycles Core clock cycles E1-E3 E3 E1 E1-E3 E3*(f /f) E1+E3*(f /f - 1) Instruction number = E2 CPI(f) = E1/E2 LL-MAB CPI Predictor Instruction number = E2 CPI(f ) = (E1+E3*(f /f - 1))/E2 48 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
49 CPI CPI PREDICTED CPI CURVE V.S. MEASURED CPI CURVE 1.7GHZ (VF2) -> 3.5GHZ (VF5) 5 Predicted CPI of 3.5GHz from Measurements Taken at 1.7 GHz (473.astar) % 5% 10% 15% 20% 25% 30% 35% 40% 45% 50% 55% 60% 65% 70% 75% 80% 85% 90% 95% 100% Executing Rate (Retired Instructions/Total Instructions) 5 Measured CPI of 3.5GHz (473.astar) % 5% 10% 15% 20% 25% 30% 35% 40% 45% 50% 55% 60% 65% 70% 75% 80% 85% 90% 95% 100% Executing Rate (Retired Instructions/Total Instructions) 49 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
50 CPI PREDICTION ERROR FX-8320 Processor All 52 benchmarks in SPEC, PARSEC, and NPB 1.7GHz (VF2) -> 3.5GHz (VF5) 10% 8% 1.7GHz->3.5GHz 15.5% 14.2% 6% 4% 3.0% 2% 0% 483.xalancbmk 482.sphinx3 481.wrf 473.astar 471.omnetpp 470.lbm 465.tonto 464.h264ref 462.libquantum 459.GemsFDTD 458.sjeng 456.hmmer 454.calculix 453.povray 450.soplex 447.dealII 445.gobmk 444.namd 437.leslie3d 436.cactusADM 435.gromacs 434.zeusmp 433.milc 429.mcf 416.gobmk 410.bwaves 403.gcc 401.bzip2 400.perlbench UA SP MG LU IS FT EP DC CG BT streamcluster dedup canneal x264 vips swaptions raytrace freqmine fluidanimate ferret facesim bodytrack blackscholes Average 50 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
51 OUTLINE Background Experimental Methodology Performance Prediction Across DVFS States Power Prediction Across DVFS States PPEP Framework Conclusion Q2: How does the application s power change with the VF state? 51 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
52 IDLE POWER MODEL + DYNAMIC POWER MODEL Cooling 52 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
53 Normalized Chip Power Temperature (K) IDLE POWER MODEL + DYNAMIC POWER MODEL Power (Sampled Point) Temperature Cooling Step (200ms) PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
54 Normalized Chip Power Temperature (K) IDLE POWER MODEL + DYNAMIC POWER MODEL Heating Power (Sampled Point) Temperature Cooling Step (200ms) PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
55 Normalized Chip Power Temperature (K) IDLE POWER MODEL + DYNAMIC POWER MODEL Heating Power (Sampled Point) Temperature Cooling Step (200ms) PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
56 Normalized Chip Power Temperature (K) IDLE POWER MODEL + DYNAMIC POWER MODEL Heating Power (Sampled Point) Temperature Cooling Step (200ms) PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
57 Normalized Chip Power Temperature (K) IDLE POWER MODEL + DYNAMIC POWER MODEL Heating Power (Sampled Point) Temperature Relationship? Cooling Step (200ms) PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
58 Normalized Chip Power Temperature (K) IDLE POWER MODEL + DYNAMIC POWER MODEL Heating Power (Sampled Point) Temperature Relationship? Cooling Step (200ms) VF State Voltage(V) Frequency(GHz) Error of P idle VF % VF % VF % VF % VF % 58 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
59 IDLE POWER MODEL + DYNAMIC POWER MODEL 59 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
60 IDLE POWER MODEL + DYNAMIC POWER MODEL # Event Code E4 Retired_uOPs 0xc1 E5 FPU_Pipe_Assignment 0x00 E6 L1I$_Fetches 0x80 E7 L1D$_Accesses 0x40 E8 L2$_Requests 0x7d E9 Retired_Branches 0xc2 E10 Retired_MisBranches 0xc3 E11 L2$_Misses 0x7e E12 Dispatch_Stalls 0xd1 (PS= Per-Second Count Value) 60 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
61 POWER MODEL VALIDATION EXPERIMENT Benchmark Combination Totally 152 combinations Thread number: 1, 2, 3, and 4 SPEC: single-/multi- programed PARSEC: single-/multi- threaded NPB: single-/multi- threaded Number SPEC PARSEC NPB Total 1-thread thread thread thread Total PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
62 POWER MODEL VALIDATION EXPERIMENT Benchmark Combination Totally 152 combinations Thread number: 1, 2, 3, and 4 SPEC: single-/multi- programed PARSEC: single-/multi- threaded NPB: single-/multi- threaded Number SPEC PARSEC NPB Total 1-thread thread thread thread Total fold cross validation Divide 152 benchmark combination in to 4 sets Train on all combinations of 3 sets Test on the remaining set 62 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
63 Validation Error of Chip Power POWER MODEL VALIDATION (LOWER IS BETTER) Error: 4.6% Standard Deviation: 2.8% 8% 7% 6% 5% 4% 3% 2% 1% Average Standard Deviation 0% ALL NPB PAR SPE ALL NPB PAR SPE ALL NPB PAR SPE ALL NPB PAR SPE ALL NPB PAR SPE VF5 VF4 VF3 VF2 VF1 63 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
64 PREDICTING POWER ACROSS VF STATES VF5 VF4 VF3 VF2 VF1 CPI(VF 5 ) 3 Events => CPI(VF 4 ) CPI(VF 3 ) CPI(VF 2 ) CPI(VF 1 ) LL-MAB T => P idle (VF 4 ) 9 Events => P dyn (VF 4 ) 64 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
65 PREDICTING POWER ACROSS VF STATES VF5 CPI(VF 5 ) P idle (VF 5 ) VF4 3 Events => CPI(VF 4 ) T => P idle (VF 4 ) 9 Events => P dyn (VF 4 ) VF3 CPI(VF 3 ) P idle (VF 3 ) VF2 CPI(VF 2 ) P idle (VF 2 ) VF1 CPI(VF 1 ) P idle (VF 1 ) LL-MAB 65 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
66 PREDICTING POWER ACROSS VF STATES VF5 CPI(VF 5 ) P idle (VF 5 ) VF4 3 Events => CPI(VF 4 ) T => P idle (VF 4 ) 9 Events => P dyn (VF 4 ) VF3 CPI(VF 3 ) P idle (VF 3 ) VF2 CPI(VF 2 ) P idle (VF 2 ) VF1 CPI(VF 1 ) P idle (VF 1 ) LL-MAB same T 66 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
67 PREDICTING POWER ACROSS VF STATES VF5 CPI(VF 5 ) P idle (VF 5 ) P dyn (VF 5 ) VF4 3 Events => CPI(VF 4 ) T => P idle (VF 4 ) 9 Events => P dyn (VF 4 ) VF3 CPI(VF 3 ) P idle (VF 3 ) P dyn (VF 3 ) VF2 CPI(VF 2 ) P idle (VF 2 ) P dyn (VF 2 ) VF1 CPI(VF 1 ) P idle (VF 1 ) P dyn (VF 1 ) LL-MAB same T 67 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
68 PREDICTING POWER ACROSS VF STATES VF5 VF4 VF3 VF2 VF1 CPI(VF 5 ) 3 Events => CPI(VF 4 ) P idle (VF 5 ) T => P idle (VF 4 ) P dyn (VF 5 ) 9 Events => P dyn (VF 4 ) CPI(VF 3 ) CPI(VF 2 ) CPI(VF 1 ) P idle (VF 3 ) P idle (VF 2 ) P idle (VF 1 ) P dyn (VF 3 ) P dyn (VF 2 ) P dyn (VF 1 ) LL-MAB same T HW event prediction? E PS(i) (VF5) E PS(i) (VF4) E PS(i) (VF3)? i=4,,12 E PS(i) (VF2) E PS(i) (VF1) 68 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
69 PREDICTING POWER ACROSS VF STATES VF5 VF4 VF3 VF2 VF1 CPI(VF 5 ) 3 Events => CPI(VF 4 ) P idle (VF 5 ) T => P idle (VF 4 ) P dyn (VF 5 ) 9 Events => P dyn (VF 4 ) CPI(VF 3 ) CPI(VF 2 ) CPI(VF 1 ) P idle (VF 3 ) P idle (VF 2 ) P idle (VF 1 ) P dyn (VF 3 ) P dyn (VF 2 ) P dyn (VF 1 ) LL-MAB same T HW event prediction? E PS(i) (VF5) E PS(i) (VF4) E PS(i) (VF3)? i=4,,12 E PS(i) (VF2) E PS(i) (VF1) 2 observations + LL-MAB CPI Predictor 69 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
70 OBSERVATION 1 + OBSERVATION 2 At any given point in the execution of a program, core-private HW event counts per instruction are independent of VF state. => To execute the same section of instructions in a program, the activities of core-private resources are independent of VF state. # Event Name E4 E5 E6 E7 E8 E9 E10 E11 Retired_uOPs FPU_Pipe_Assignment L1I$_Fetches L1D$_Accesses L2$_Requests Retired_Branches Retired_MisBranches L2$_Misses 70 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
71 OBSERVATION 1 + OBSERVATION 2 At any given point in the execution of a program, core-private HW event counts per instruction are independent of VF state. => To execute the same section of instructions in a program, the activities of core-private resources are independent of VF state. # Event Name E4 Retired_uOPs E5 FPU_Pipe_Assignment E6 L1I$_Fetches E7 L1D$_Accesses E8 L2$_Requests E9 Retired_Branches E10 Retired_MisBranches E11 L2$_Misses Error 0.6% 0.9% 0.7% 0.7% 5.0% 0.7% 1.3% 4.0% On FX-8320, between 3.5GHz (VF5) and 1.7GHz (VF2) 71 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
72 OBSERVATION 1 + OBSERVATION 2 # Event E1 CPU_Clock_not_Halted E12 Dispatch_Stalls 72 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
73 OBSERVATION 1 + OBSERVATION 2 # Event E1 CPU_Clock_not_Halted E12 Dispatch_Stalls Gap Error 1.7% On FX-8320, between3.5ghz (VF5) and 1.7GHz (VF2) 73 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
74 OBSERVATION 1 + OBSERVATION 2 # Event E1 CPU_Clock_not_Halted E12 Dispatch_Stalls Cycles retiring 4 instructions Cycles retiring 2 instructions Cycles without retiring Gap Error 1.7% Cycles retiring 3 instructions Cycles retiring 1 instruction On FX-8320, between3.5ghz (VF5) and 1.7GHz (VF2) 74 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
75 OBSERVATION 1 + OBSERVATION 2 Freq = f # Event E1 CPU_Clock_not_Halted E12 Dispatch_Stalls Cycles retiring 4 instructions Cycles retiring 2 instructions Cycles without retiring Gap Error 1.7% Cycles retiring 3 instructions Cycles retiring 1 instruction On FX-8320, between3.5ghz (VF5) and 1.7GHz (VF2) Start end Freq = f 75 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
76 OBSERVATION 1 + OBSERVATION 2 Freq = f # Event E1 CPU_Clock_not_Halted E12 Dispatch_Stalls Cycles retiring 4 instructions Cycles retiring 2 instructions Cycles without retiring Gap Error 1.7% Cycles retiring 3 instructions Cycles retiring 1 instruction On FX-8320, between3.5ghz (VF5) and 1.7GHz (VF2) Start Frequency Independent end Freq = f 76 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
77 OBSERVATION 1 + OBSERVATION 2 Freq = f # Event E1 CPU_Clock_not_Halted E12 Dispatch_Stalls Cycles retiring 4 instructions Cycles retiring 2 instructions Cycles without retiring Gap Error 1.7% On FX-8320, between3.5ghz (VF5) and 1.7GHz (VF2) Cycles retiring 3 instructions Cycles retiring 1 instruction Overheads of mispredicted branches and exceptions Start Frequency Independent end Freq = f 77 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
78 OBSERVATION 1 + OBSERVATION 2 Freq = f # Event E1 CPU_Clock_not_Halted E12 Dispatch_Stalls Cycles retiring 4 instructions Cycles retiring 2 instructions Cycles without retiring Gap Error 1.7% On FX-8320, between3.5ghz (VF5) and 1.7GHz (VF2) Cycles retiring 3 instructions Cycles retiring 1 instruction Overheads of mispredicted branches and exceptions Dispatch Stalls Start Frequency Independent end Freq = f 78 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
79 DYNAMIC POWER PREDICTION FLOW HW Events Prediction Flow (Bridge: LL-MAB + 2 OBs) # Event E1 CPU_Clock_not_Halted E2 Retired_Instructions E3 MAB0_Wait_Cycles E4 Retired_uOPs E5 FPU_Pipe_Assignment E6 L1I$_Fetches E7 L1D$_Accesses E8 L2$_Requests E9 Retired_Branches E10 Retired_MisBranches E11 L2$_Misses E12 Dispatch_Stalls PS=per-second PI=per-instruction 79 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
80 DYNAMIC POWER PREDICTION FLOW HW Events Prediction Flow (Bridge: LL-MAB + 2 OBs) # Event E1 CPU_Clock_not_Halted From PMC E2 Retired_Instructions E3 MAB0_Wait_Cycles E4 Retired_uOPs E5 FPU_Pipe_Assignment E6 L1I$_Fetches E7 L1D$_Accesses E8 L2$_Requests E9 Retired_Branches E10 Retired_MisBranches E11 L2$_Misses E12 Dispatch_Stalls PS=per-second PI=per-instruction 80 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
81 DYNAMIC POWER PREDICTION FLOW HW Events Prediction Flow (Bridge: LL-MAB + 2 OBs) # Event E1 CPU_Clock_not_Halted From PMC E2 Retired_Instructions E3 MAB0_Wait_Cycles E4 Retired_uOPs E5 FPU_Pipe_Assignment E6 L1I$_Fetches E7 L1D$_Accesses E8 L2$_Requests E9 Retired_Branches E10 Retired_MisBranches E11 L2$_Misses E12 Dispatch_Stalls PS=per-second PI=per-instruction 81 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
82 DYNAMIC POWER PREDICTION FLOW HW Events Prediction Flow (Bridge: LL-MAB + 2 OBs) # Event E1 CPU_Clock_not_Halted From PMC E2 Retired_Instructions LL-MAB E3 MAB0_Wait_Cycles E4 Retired_uOPs E5 FPU_Pipe_Assignment E6 L1I$_Fetches E7 L1D$_Accesses E8 L2$_Requests E9 Retired_Branches E10 Retired_MisBranches E11 L2$_Misses E12 Dispatch_Stalls PS=per-second PI=per-instruction 82 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
83 DYNAMIC POWER PREDICTION FLOW HW Events # Event E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 CPU_Clock_not_Halted Retired_Instructions MAB0_Wait_Cycles Retired_uOPs FPU_Pipe_Assignment L1I$_Fetches L1D$_Accesses L2$_Requests Retired_Branches Retired_MisBranches L2$_Misses Dispatch_Stalls PS=per-second PI=per-instruction Prediction Flow (Bridge: LL-MAB + 2 OBs) From PMC 83 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014 LL-MAB Observation 1 Observation 2
84 DYNAMIC POWER PREDICTION FLOW HW Events # Event E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 CPU_Clock_not_Halted Retired_Instructions MAB0_Wait_Cycles Retired_uOPs FPU_Pipe_Assignment L1I$_Fetches L1D$_Accesses L2$_Requests Retired_Branches Retired_MisBranches L2$_Misses Dispatch_Stalls PS=per-second PI=per-instruction Prediction Flow (Bridge: LL-MAB + 2 OBs) From PMC 84 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014 LL-MAB Observation 1 Observation 2
85 DYNAMIC POWER PREDICTION FLOW HW Events # Event E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 CPU_Clock_not_Halted Retired_Instructions MAB0_Wait_Cycles Retired_uOPs FPU_Pipe_Assignment L1I$_Fetches L1D$_Accesses L2$_Requests Retired_Branches Retired_MisBranches L2$_Misses Dispatch_Stalls PS=per-second PI=per-instruction Prediction Flow (Bridge: LL-MAB + 2 OBs) From PMC 85 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014 LL-MAB Observation 1 Observation 2
86 Chip Power Prediction Error Across VF States PREDICTING ERROR OF AVERAGE CHIP POWER LOWER IS BETTER Error: 4.2% Standard Deviation: 3.6% 8% 7% 6% 5% 4% 3% 2% 1% Average Standard Deviation 0% VF1->VF1 VF1->VF2 VF1->VF3 VF1->VF4 VF1->VF5 VF2->VF1 VF2->VF2 VF2->VF3 VF2->VF4 VF2->VF5 VF3->VF1 VF3->VF2 VF3->VF3 VF3->VF4 VF3->VF5 VF4->VF1 VF4->VF2 VF4->VF3 VF4->VF4 VF4->VF5 VF5->VF1 VF5->VF2 VF5->VF3 VF5->VF4 VF5->VF5 86 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
87 OUTLINE Background Experimental Methodology Performance Prediction Across DVFS States Power Prediction Across DVFS States PPEP Framework Conclusion Q1: How does the application s performance change with the VF state? Q2: How does the application s power change with the VF state? 87 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
88 OUTLINE Background Experimental Methodology Performance Prediction Across DVFS States Power Prediction Across DVFS States PPEP Framework Conclusion 88 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
89 PPEP FRAMEWORK PMC based User Daemon Periodically Running All-in-one: PPEP PMC, VF 1 CPIs at all VFs Performance Prediction Model 2 CPI at all VFs Core 1's PPE Core n's PPE Dynamic Info: PMC, VF, Temperature 4 PMC VF Temperature, VF PMC at other VFs H/W Events Predictor 3 Dynamic Power Model Idle Power Model Dynamic Power at all VFs Energy Prediction Idle Power at all VFs 5 Core 0's PPE DVFS Exploring Space: Energy -Delay Scaling, Power Capping, etc. 6 VF Regulator DVFS Decision 89 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
90 PPEP FRAMEWORK PMC based User Daemon Periodically Running Performance Online Power Energy Prediction Commercial Processors All-in-one: PPEP PMC, VF 1 CPIs at all VFs Performance Prediction Model 2 CPI at all VFs Core 1's PPE Core n's PPE Dynamic Info: PMC, VF, Temperature 4 PMC VF Temperature, VF PMC at other VFs H/W Events Predictor 3 Dynamic Power Model Idle Power Model Dynamic Power at all VFs Energy Prediction Idle Power at all VFs 5 Core 0's PPE DVFS Exploring Space: Energy -Delay Scaling, Power Capping, etc. 6 VF Regulator DVFS Decision 90 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
91 CONCLUSION On Commercial Processor Demonstrated an across-vf CPI predictor LL-MAB According to the Leading Loads theory Demonstrated an across-vf power predictor Through the LL-MAB CPI predictor and 2 observations Combining them together: PPEP Framework Supplies performance, power, and energy information SW method w/o requiring HW or OS modification 91 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
92 THANK YOU! Questions 92 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
93 DISCLAIMER & ATTRIBUTION The information presented in this document is for informational purposes only and may contain technical inaccuracies, omissions and typographical errors. The information contained herein is subject to change and may be rendered inaccurate for many reasons, including but not limited to product and roadmap changes, component and motherboard version changes, new model and/or product releases, product differences between differing manufacturers, software changes, BIOS flashes, firmware upgrades, or the like. AMD assumes no obligation to update or otherwise correct or revise this information. However, AMD reserves the right to revise this information and to make changes from time to time to the content hereof without obligation of AMD to notify any person of such revisions or changes. AMD MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE CONTENTS HEREOF AND ASSUMES NO RESPONSIBILITY FOR ANY INACCURACIES, ERRORS OR OMISSIONS THAT MAY APPEAR IN THIS INFORMATION. AMD SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. IN NO EVENT WILL AMD BE LIABLE TO ANY PERSON FOR ANY DIRECT, INDIRECT, SPECIAL OR OTHER CONSEQUENTIAL DAMAGES ARISING FROM THE USE OF ANY INFORMATION CONTAINED HEREIN, EVEN IF AMD IS EXPRESSLY ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. ATTRIBUTION 2014 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD Arrow logo and combinations thereof are trademarks of Advanced Micro Devices, Inc. in the United States and/or other jurisdictions. SPEC is a registered trademark of the Standard Performance Evaluation Corporation (SPEC). Other names are for informational purposes only and may be trademarks of their respective owners. 93 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
94 Backup Slides
95 PERFORMANCE & POWER PREDICTION Running VF state: VF4 Predicting performance, power of other VF states Core VF State Performance Power Higher VF 5 Running at: CPI(VF 5 ) Running at: Power(VF 5 ) VF 4 CPI(VF 4 ) Power(VF 4 ) VF 3 CPI(VF 3 ) Power(VF 3 ) VF 2 CPI(VF 2 ) Power(VF 2 ) Lower VF 1 Performance prediction? CPI(VF 1 ) CPU Power prediction? Power(VF 1 ) 95 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
96 EXPERIMENTAL METHODOLOGY SOFTWARE TOOLS Operating System Ubuntu LTS Desktop (kernel version ) Tools taskset: A2C mapping msr-tools: PMC control CPUFreq userspace governor: VF Scaling hwmon tree in sysfs: temperature measurement Benchmark Suites SPEC CPU 2006 v1.2 (29 benchmarks) PARSEC v2.1 (13 benchmarks) NAS Parallel Benchmarks v3.3.1 (10 benchmarks) 96 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
97 HOW TO ESTIMATE MEMORY STALL CYCLES? MODERN CORES MAKE THIS DIFFICULT Memory level parallelism Accesses overlap computation Variable latencies memory access counts do not estimate memory time accurately Core clock cycles Core Work L3+DRAM Variable Latencies Multiple Parallel Accesses Accesses Overlap Computation 97 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
98 LEADING LOADS ON AMD PROCESSORS L2 cache misses held in Miss Address Buffer (MAB) MAB entries have a static priority (e.g. MAB0 is highest priority) Highest priority empty MAB holds the miss until it returns from memory Core Clock Domain CPU Core & L1 Cache L2 Cache Miss Address Buffers MAB0 MAB1 MAB2 MABn NB and Memory Clock Domains L3 Cache & DRAM Performance event 0x69 allows SW to count # of cycles with filled MABs 98 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
99 LEADING LOADS ON AMD PROCESSORS L2 cache misses held in Miss Address Buffer (MAB) MAB entries have a static priority (e.g. MAB0 is highest priority) Highest priority empty MAB holds the miss until it returns from memory Core Clock Domain CPU Core & L1 Cache L2 Cache Miss Address Buffers MAB0 MAB1 MAB2 MABn NB and Memory Clock Domains L3 Cache & DRAM Performance event 0x69 allows SW to count # of cycles with filled MABs 99 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
100 LEADING LOADS ON AMD PROCESSORS L2 cache misses held in Miss Address Buffer (MAB) MAB entries have a static priority (e.g. MAB0 is highest priority) Highest priority empty MAB holds the miss until it returns from memory Core Clock Domain CPU Core & L1 Cache L2 Cache Miss Address Buffers MAB0 MAB1 MAB2 MABn NB and Memory Clock Domains L3 Cache & DRAM Performance event 0x69 allows SW to count # of cycles with filled MABs 100 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
101 LEADING LOADS ON AMD PROCESSORS L2 cache misses held in Miss Address Buffer (MAB) MAB entries have a static priority (e.g. MAB0 is highest priority) Highest priority empty MAB holds the miss until it returns from memory Core Clock Domain CPU Core & L1 Cache L2 Cache Miss Address Buffers MAB0 MAB1 MAB2 MABn NB and Memory Clock Domains L3 Cache & DRAM Performance event 0x69 allows SW to count # of cycles with filled MABs 101 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
102 LEADING LOADS ON AMD PROCESSORS L2 cache misses held in Miss Address Buffer (MAB) MAB entries have a static priority (e.g. MAB0 is highest priority) Highest priority empty MAB holds the miss until it returns from memory Core Clock Domain CPU Core & L1 Cache L2 Cache Miss Address Buffers MAB0 MAB1 MAB2 MABn NB and Memory Clock Domains L3 Cache & DRAM Performance event 0x69 allows SW to count # of cycles with filled MABs 102 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
103 LEADING LOADS ON AMD PROCESSORS L2 cache misses held in Miss Address Buffer (MAB) MAB entries have a static priority (e.g. MAB0 is highest priority) Highest priority empty MAB holds the miss until it returns from memory Core Clock Domain CPU Core & L1 Cache L2 Cache Miss Address Buffers MAB0 MAB1 MAB2 MABn NB and Memory Clock Domains L3 Cache & DRAM Performance event 0x69 allows SW to count # of cycles with filled MABs 103 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
104 LEADING LOADS ON AMD PROCESSORS L2 cache misses held in Miss Address Buffer (MAB) MAB entries have a static priority (e.g. MAB0 is highest priority) Highest priority empty MAB holds the miss until it returns from memory Core Clock Domain CPU Core & L1 Cache L2 Cache Miss Address Buffers MAB0 MAB1 MAB2 MABn NB and Memory Clock Domains L3 Cache & DRAM Performance event 0x69 allows SW to count # of cycles with filled MABs 104 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
105 LEADING LOADS ON AMD PROCESSORS L2 cache misses held in Miss Address Buffer (MAB) MAB entries have a static priority (e.g. MAB0 is highest priority) Highest priority empty MAB holds the miss until it returns from memory Core Clock Domain CPU Core & L1 Cache L2 Cache Miss Address Buffers MAB0 MAB1 MAB2 MABn NB and Memory Clock Domains L3 Cache & DRAM Performance event 0x69 allows SW to count # of cycles with filled MABs 105 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
106 LEADING LOADS ON AMD PROCESSORS L2 cache misses held in Miss Address Buffer (MAB) MAB entries have a static priority (e.g. MAB0 is highest priority) Highest priority empty MAB holds the miss until it returns from memory Core Clock Domain CPU Core & L1 Cache L2 Cache Miss Address Buffers MAB0 MAB1 MAB2 MABn NB and Memory Clock Domains L3 Cache & DRAM Performance event 0x69 allows SW to count # of cycles with filled MABs 106 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
107 MAB BASED LEADING LOADS MODEL: LL-MAB EXPERIMENT Benchmark Running on core 0. Manager Running on Core 7. Collects the counts every 200ms. CU 0 CU 1 CU 2 CU 3 Core 0 Core 1 Core 2 Core 3 Core 4 Core 5 Core 6 Core 7 Benchmark L2 Cache L2 Cache L2 Cache L2 Cache L3 Cache & Memory Controller Manager 200ms Core 0 Core 7 Measured CPI(f) CPI(f) CPI(f) CPI(f) CPI(f) CPI(f) CPI(f) CPI(f) Predicted CPI(f ) CPI(f ) CPI(f ) CPI(f ) CPI(f ) 107 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014 CPI(f ) CPI(f ) CPI(f )
108 CPI CPI PREDICTED CPI V.S. MEASURED CPI 1.7GHZ -> 3.5GHZ 5 Predicted CPI of 3.5GHz from Measurements Taken at 1.7 GHz (473.astar) % 5% 10% 15% 20% 25% 30% 35% 40% 45% 50% 55% 60% 65% 70% 75% 80% 85% 90% 95% 100% Executing Rate (Retired Instructions/Total Instructions) 5 Measured CPI of 3.5GHz (473.astar) % 5% 10% 15% 20% 25% 30% 35% 40% 45% 50% 55% 60% 65% 70% 75% 80% 85% 90% 95% 100% Executing Rate (Retired Instructions/Total Instructions) 108 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
109 CPI CPI PREDICTED CPI V.S. MEASURED CPI 1.7GHZ -> 3.5GHZ % 5% 10% 15% 20% 25% 30% 35% 40% 45% 50% 55% 60% 65% 70% 75% 80% 85% 90% 95% 100% Executing Rate (Retired Instructions/Total Instructions) Measured CPI of 3.5GHz (473.astar) a) Divide each curve into 20 segments; Predicted CPI of 3.5GHz from Measurements Taken at 1.7 GHz (473.astar) 0 0% 5% 10% 15% 20% 25% 30% 35% 40% 45% 50% 55% 60% 65% 70% 75% 80% 85% 90% 95% 100% Executing Rate (Retired Instructions/Total Instructions) 109 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014 b) Compare cycle numbers in each segment-pair; c) Average absolute error => CPI Prediction Error.
110 CPI CPI PREDICTED CPI V.S. MEASURED CPI 1.7GHZ -> 3.5GHZ % 5% 10% 15% 20% 25% 30% 35% 40% 45% 50% 55% 60% 65% 70% 75% 80% 85% 90% 95% 100% Executing Rate (Retired Instructions/Total Instructions) Measured CPI of 3.5GHz (473.astar) a) Divide each curve into 20 segments; Predicted CPI of 3.5GHz from Measurements Taken at 1.7 GHz (473.astar) 0 0% 5% 10% 15% 20% 25% 30% 35% 40% 45% 50% 55% 60% 65% 70% 75% 80% 85% 90% 95% 100% Executing Rate (Retired Instructions/Total Instructions) 110 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014 b) Compare cycle numbers in each segment-pair; c) Average absolute error => CPI Prediction Error.
111 CPI CPI PREDICTED CPI V.S. MEASURED CPI 1.7GHZ -> 3.5GHZ % 5% 10% 15% 20% 25% 30% 35% 40% 45% 50% 55% 60% 65% 70% 75% 80% 85% 90% 95% 100% Executing Rate (Retired Instructions/Total Instructions) Measured CPI of 3.5GHz (473.astar) a) Divide each curve into 20 segments; Predicted CPI of 3.5GHz from Measurements Taken at 1.7 GHz (473.astar) 0 0% 5% 10% 15% 20% 25% 30% 35% 40% 45% 50% 55% 60% 65% 70% 75% 80% 85% 90% 95% 100% Executing Rate (Retired Instructions/Total Instructions) 111 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014 b) Compare cycle numbers in each segment-pair; c) Average absolute error => CPI Prediction Error.
112 CPI Prediction Error CPI PREDICTION ERROR V.S. MEMORYBOUNDEDNESS 1.7GHZ -> 3.5GHZ 20% 15% 10% 5% 0% Memoryboundedness (Cycles of 3.5G/Cycles of 1.7G) 112 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
113 CHIP IDLE POWER MODEL MODEL AND ERROR 113 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
114 CHIP DYNAMIC POWER MODEL EXPERIMENT App threads mapping & Manager CU 0 CU 1 CU 2 CU 3 Core 0 Core 1 Core 2 Core 3 Core 4 Core 5 Core 6 Core 7 App thread App thread App thread App thread Manager L2 Cache L2 Cache L2 Cache L2 Cache L3 Cache & Memory Controller Time Step = 200ms 1st half-step (100ms) 2nd half-step (100ms) power-step (20ms) x10 Manager sleeping Manager working 114 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
115 Validation Error of Dynamic Power FITTING ERROR: DYNAMIC POWER MODEL (LOWER IS BETTER) Error: 10.6% Standard Deviation: 5.8% 18% 16% 14% 12% 10% 8% 6% 4% 2% 0% Average ALL NPB PAR SPE Standard Deviation ALL NPB PAR SPE ALL NPB PAR SPE ALL NPB PAR SPE ALL NPB PAR SPE VF5 VF4 VF3 VF2 VF1 115 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
116 Dynamic Power Prediction Error Across VF States (LOWER IS BETTER) Error: 8.3% Standard Deviation: 6.9% 16% 14% Average Standard Deviation 12% 10% 8% 6% 4% 2% 0% VF1->VF1 VF1->VF2 VF1->VF3 VF1->VF4 VF1->VF5 VF2->VF1 VF2->VF2 VF2->VF3 VF2->VF4 VF2->VF5 VF3->VF1 VF3->VF2 VF3->VF3 VF3->VF4 VF3->VF5 VF4->VF1 VF4->VF2 VF4->VF3 VF4->VF4 VF4->VF5 VF5->VF1 VF5->VF2 VF5->VF3 VF5->VF4 VF5->VF5 116 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
117 THE IMPACT OF POWER GATING 117 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
118 THE IMPACT OF POWER GATING Micro Benchmark: A Dataset is fitted in L1 data cache => No NB activity (dynamic power) N instances of A times the dynamic power of A by N A2C Mapping CU0 C0, C1 CU1 C2, C3 CU2 C4, C5 CU3 C6, C7 4CUs A, - A, - A, - A, - 3CUs A, - A, - A, - Idle 2CUs A, - A, - Idle Idle 1CU A, - Idle Idle Idle Idle Idle Idle Idle Idle 118 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
119 Normalized Chip Power THE IMPACT OF POWER GATING Micro Benchmark: A Dataset is fitted in L1 data cache => No NB activity (dynamic power) N instances of A times the dynamic power of A by N A2C Mapping CU0 C0, C1 CU1 C2, C3 CU2 C4, C5 CU3 C6, C7 4CUs A, - A, - A, - A, - 3CUs A, - A, - A, - Idle 2CUs A, - A, - Idle Idle 1CU A, - Idle Idle Idle Idle Idle Idle Idle Idle CUs 3CUs 2CUs 1CU idle Disable Power Gating Enable Power Gating 119 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
120 Normalized Chip Power THE IMPACT OF POWER GATING Micro Benchmark: A Dataset is fitted in L1 data cache => No NB activity (dynamic power) N instances of A times the dynamic power of A by N A2C Mapping CU0 C0, C1 CU1 C2, C3 CU2 C4, C5 CU3 C6, C7 4CUs A, - A, - A, - A, - 3CUs A, - A, - A, - Idle 2CUs A, - A, - Idle Idle 1CU A, - Idle Idle Idle Idle Idle Idle Idle Idle P dyn (A)+P idle (Chip) 4CUs 3CUs 2CUs 1CU idle Disable Power Gating Enable Power Gating 120 PPEP : ONLINE PERFORMANCE, POWER, AND ENERGY PREDICTION FRAMEWORK DECEMBER 17, 2014
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