ZC706 MIG Design Creation November 2015

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1 ZC706 MIG Design Creation November 2015 XTP244

2 Revision History Date Version Description 11/24/ Regenerated for /06/ Regenerated for /30/ Regenerated for /30/ Regenerated for /24/ Regenerated for /08/ Regenerated for /09/ Regenerated for /16/ Regenerated for /18/ Regenerated for /23/ Regenerated for /19/ Regenerated for Vivado /03/ Regenerated for /18/ Regenerated for /23/ Initial version. Copyright 2015 Xilinx, Inc. All Rights Reserved. XILINX, the Xilinx logo, the Brand Window and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners. NOTICE OF DISCLAIMER: The information disclosed to you hereunder (the Information ) is provided AS-IS with no warranty of any kind, express or implied. Xilinx does not assume any liability arising from your use of the Information. You are responsible for obtaining any rights you may require for your use of this Information. Xilinx reserves the right to make changes, at any time, to the Information without notice and at its sole discretion. Xilinx assumes no obligation to correct any errors contained in the Information or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE INFORMATION, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NONINFRINGEMENT OF THIRD-PARTY RIGHTS.

3 Note: This presentation applies to the ZC706 Overview ZC706 Board Software Requirements Generate MIG Example Design Modifications to Example Design Compile Example Design ZC706 Setup Run MIG Example Design Adjust Data Pattern using VIO Console References

4 Xilinx ZC706 Board

5 Vivado Software Requirements Xilinx Vivado Design Suite , Design Edition

6 Generate MIG Example Design Open Vivado Start All Programs Xilinx Design Tools Vivado Vivado Select Create New Project

7 Generate MIG Example Design Click Next

$Set the Project name and location to zc706_mig and C:\ Check Create project$

8 Note: Vivado generally requires forward slashes in paths Generate MIG Example Design Set the Project name and location to zc706_mig and C:\ Check Create project subdirectory

9 Generate MIG Example Design Select RTL Project Select Do not specify sources at this time

10 Generate MIG Example Design Select the ZC706 Board

11 Generate MIG Example Design Click Finish

12 Generate MIG Example Design Click on IP Catalog

13 Generate MIG Example Design Select MIG 7 Series, v2.4 under Memory Interface Generators

14 Generate MIG Example Design Right click on MIG 7 Series Select Customize IP

15 Generate MIG Example Design Leave this page as is Click Next

16 Generate MIG Example Design Leave this page as is Click Next

17 Generate MIG Example Design Leave this page as is Click Next

18 Generate MIG Example Design Select Memory Type DDR3 SDRAM Click Next

19 Generate MIG Example Design Select Clock Period: 1250 ps Type: SODIMMs Part: MT8JTF12864HZ- 1G6 Data Mask: Checked Click Next

20 Generate MIG Example Design Select: Input Clock Period: 5000 ps RTT: RZQ/6 Click Next

21 Generate MIG Example Design Select Reference Clock: Use System Clock System Reset: ACTIVE HIGH Debug: ON Click Next

22 Generate MIG Example Design Select DCI Cascade: Checked Click Next

23 Generate MIG Example Design Select Fixed Pin Out Click Next

24 Modifications to Example Design Open the ZC706 MIG Design Files ( C) ZIP file Available through Extract the file, example_top.xdc only to C:\zc706_mig Contains the XDC constraints needed for ZC706 MIG design This zip file will be needed later in the presentation

25 Generate MIG Example Design Select Read XDC/UCF Open the file: example_top.xdc

26 Generate MIG Example Design Once it finishes reading in the XDC, click Validate Click OK

27 Generate MIG Example Design The Next button is enabled once the pinout is validated. Click Next

28 Generate MIG Example Design Set sys_clk_p/n to H9/G9(CC_P/N) Click Next

29 Generate MIG Example Design Leave this page as is Click Next

30 Generate MIG Example Design Accept Simulation license, if desired Otherwise, Decline license Click Next

31 Generate MIG Example Design Leave this page as is Click Next

32 Generate MIG Example Design Click Generate

33 Generate MIG Example Design Click Generate

34 Generate MIG Example Design MIG design appears in Design Sources Wait until checkmark appears on mig_7series_0_synth_1

35 Compile Example Design Right click on mig_7series_0 and select Open IP Example Design

36 Compile Example Design Set the location to C:/zc706_mig and click OK

37 Note: The original project window can be closed Compile Example Design A new project is created

$4 C) ZIP file to your C:\zc706_mig directory Contains several changes needed to support Zynq 7000 devices with MIG Do this after$

38 Modifications to Example Design Unzip the ZC706 MIG Design Files ( C) ZIP file to your C:\zc706_mig directory Contains several changes needed to support Zynq 7000 devices with MIG Do this after creating the Example Design; changes only affect the Example Design

39 Modifications to Example Design Modifications to the example design Added RTL and XDC modifications to drive LEDs Added DCI Cascade constraints to XDC; for more information on using the DCI Cascade constraints for 7 Series refer to UG899 From the Tcl Console, run these commands: add_files -norecurse C:/zc706_mig/mig_7series_0_example/mig_7series_0_example.srcs/sour ces_1/imports/rtl/led_display_driver.v create_ip -name vio -vendor xilinx.com -library ip -version module_name vio_0 set_property -dict [list CONFIG.C_PROBE_IN0_WIDTH {4}] [get_ips vio_0]

40 Modifications to Example Design Press enter after entering Tcl commands

41 Modifications to Example Design Tcl commands completed successfully

42 Compile Example Design Click on Generate Bitstream

43 Compile Example Design Open and view the Implemented Design

44 ZC706 Setup Connect a USB Type-A to Micro-B cable to the USB JTAG (Digilent) connector on the ZC706 board Connect this cable to your PC Power on the ZC706 board

$cd C:\zc706_mig\ready_for_download run_mig_waveforms.$

45 Run MIG Example Design From a Command Prompt, type: cd C:\zc706_mig\ready_for_download run_mig_waveforms.bat

46 Run MIG Example Design Under Tcl script control, Vivado opens, loads the bitstream and generates a MIG waveform

47 Run MIG Example Design After bitstream loads, LED 0 (right most LED) will be lit, and LED1 will be blinking LED 3 will light and stay on This indicates Calibration has completed If an error occurs, LED 0 will go out and LED 2 will light CPU_RESET, SW13, is the reset

48 Run MIG Example Design Click and drag to the left to expand the waveform

49 Run MIG Example Design View waveforms Data is valid when dbg_rddata_valid_r is high

50 Run MIG Example Design Click and drag to the right to zoom in

51 Run MIG Example Design View waveform details

52 Adjust Data Pattern using VIO Console Select the hw_vios tab and open the Debug Probes

53 Adjust Data Pattern using VIO Console Select the vio_data_mode_value and vio_modify_enable probes Drag these probes to the hw_vios tab

54 Adjust Data Pattern using VIO Console Right click on vio_modify_enable and set to Toggle Button

55 Adjust Data Pattern using VIO Console Toggle the vio_modify_enable button to 1

56 Adjust Data Pattern using VIO Console Press and release the CPU RESET switch, SW13, after each change to vio_modify_enable or vio_data_mode_value

57 Adjust Data Pattern using VIO Console Select the hw_ila_1 tab Click Run Trigger Immediately

58 Adjust Data Pattern using VIO Console View PRBS data

59 References

60 References 7 Series Memory 7 Series FPGAs Memory Interface Solutions User Guide UG _7Series_MIS.pdf Vivado Programming and Debugging Vivado Design Suite Programming and Debugging User Guide UG908 ug908-vivado-programming-debugging.pdf

61 Documentation

62 Documentation Zynq-7000 Zynq-7000 All Programmable SoC ZC706 Documentation Zynq-7000 AP SoC ZC706 Evaluation Kit ZC706 Getting Started Guide UG961 ug961-zc706-gsg.pdf ZC706 User Guide UG954 ug954-zc706-eval-board-xc7z045-ap-soc.pdf

ZC706 MIG Design Creation November 2014

ZC706 MIG Design Creation November 2014 XTP244 Revision History Date Version Description 11/24/14 10.0 Regenerated for 2014.4. 10/08/14 9.0 Regenerated for 2014.3. 06/09/14 8.0 Regenerated for 2014.2.