Leopard (MPC5643L)TEST ELIMINATION REPORT

Transcription

1 Leopard (MPC5643L)TEST ELIMINATION REPORT 1. Objective This report describes the Leopard (MPC5643L) Room Final Test elimination plan and results. Current Final Test Flow: Cold Temp Testing Hot Temp Testing Room Temp Testing Sample In line Quality Assurance (QA GATE) Cold and Hot Testing Proposed Final Test Flow: Cold Temp Testing Hot Temp Testing Sample In Line Quality Assurance (QA GATE) Room, Cold, Hot Testing 2. General Information Product Family: Leopard (MPC5643L) Mask set: N89D Package(s): 144LQFP, 100LQFP, 257MAPBGA Test Site: Freescale Kuala Lumpur, Malaysia Test Platform: Teradyne J Qualification Plan The requirements and acceptance criteria were based on Freescale Test Elimination specification. Achieve zero test insert failures from at least 25,000 units tested to the standard production Final Test flow. Units must be sourced from at minimum of 12 wafer lots from the same fab, mask set, and processed over a minimum period of 9 weeks. 4. Correlation/Qualification Results: Page 1 of 6

2 4.1. Lots and Data Summary: The Test Elimination evaluation of 35,528 units resulted in 0 room rejects requiring test enhancement or guardband adjustments at Unit Probe and/or Final Test cold or hot. Confirmed, no room rejects. Final Test: Identify any initial rejects and containment actions Failing Test # of units Containment 1 None 0 None Required Lot summary. Lot Device Wafer Lot Test lot Lot Quantity 1 PPC5643LFF2MLQ1 DD C WEMHA1L69N PPC5643LFF2MLQ1 DD C WEMHA1L69N PPC5643LFF2MLQ1 DD C WEMHA1L69N PPC5643LFF2MLQ1 DD C WEMHA1L69N PPC5643LF0MLQ1A DD X WEMHA1J1E PPC5643LF0MLQ1A DD C WEMHA1J1EC PPC5643LFF2MLQ1 DD C WEMHA1L69N PPC5643LF0MMM1A DD X WEME006ED PPC5643LF0MMM1A DD X WEME006ED PPC5643LF0MMM1A DD X WEME006ED PPC5643LF0MLQ1A DD R WEMHA1J1EA PPC5643LFF2MLQ1 DE H ZLMHA1M2Z PPC5643LFF2MLQ1 DE H ZLMHA1M2Z MPXS2010VLQ120 DD N KLMHA1LMQP PPC5643LFF2MLQ1 DE H ZLMHA1M2Z PPC5643LFF2MMM1 DD C WEME006K2T MPXS2010VMM80 DD R KMMEA14KDM Page 2 of 6

3 18 PPC5643LFF2MLQ1 DD C WEMHA1M7X SPC5643LFF2MLQ1R DE X KLMHA1NFVH SPC5643LFF2MLQ1R DE X KLMHA1NFVG PPC5643LFF2MLL6 DE T WEMHA1MNPX PPC5643LFF2MLL6 DE X ZLMHA1N2PQ PPC5643LFF2MLL6 DE T WEMHA1MNPX SPC5643LFF2MLQ1R DD C KLMHA1N94T MPXS2010VMM120 DD R KMMEA14KDP SPC5643LFF2MLQ1 DE T KLMHA1N94R SPC5643LFF2MLQ1R DE N KLMHA1NFVL SPC5643LFF2MLQ1 DE X KLMHA1N94U SPC5643LF0MLQ1 DD N KLMHA1LXXQ SPC5643LF0MLQ1 DD N KLMHA1LXXQ SPC5643LFF2MLQ1R DE X KLMHA1NFVJ PPC5643LFF2MLL6 DE X ZLMHA1N2PR PPC5643LFF2MLL6 DE X ZLMHA1N2PP SPC5643LF0MLQ1 DD N KLMHA1LXXQ SPC5643LF0MLQ1 DD N KLMHA1LXXQ MPXS2010VLQ80 DD N KLMHA1LMQQ MPXS2005VLQ80 DD N KLMHA1LMQM SPC5643LF2MLQ1 DE N KLMHA1NHR MPXS2010VLQ80 DD N KLMHA1LMQQ MPXS2010VLQ120 DD N KLMHA1LMQP SPC5643LF2MLQ1 DE N KLMHA1NHR MPXS2010VLQ120 DD N KLMHA1LMQP MPXS2005VLQ80 DD N KLMHA1LMQM SPC5643LF2MLQ1 DE N KLMHA1NHR MPXS2005VLQ80 DD N KLMHA1LMQM MPXS2005VLQ80 DD N KLMHA1LMQM MPXS2010VLQ80 DD N KLMHA1LMQQ SPC5643LF2MLQ1 DE N KLMHA1NHR MPXS2010VLQ120 DD T KLMHA1P1GL Page 3 of 6

4 50 SPC5643LFF2MLQ1R DE X KLMHA1NFVK MPXS2005VLQ80 DD C KLMHA1NWTF SPC5643LFF2MLQ1 DE W KLMHA1Q Summary Final Verification steps: JVT test is contained in the Hot Test flow, the last Final Test insertion. NVM erase and security disable are being done at the end of the Hot Test flow, the last Final Test insertion. Flash contents (including main array and information row) are verified and in the correct state. Page 4 of 6

5 CURRENT FLOW with Room Test FLOW without Room Test Wafer Fab Wafer Fab Wafer Processing 100% Production Wafer Processing 100% Production Final Test Final Test Probe Process Probe Process Probe +25 C (Flash) DRB 250C Probe +25 C (Logic & Flash) 100% COLD Test -45C 100% HOT Test 145C 100% ROOM Test 25C Probe +25 C (Flash) DRB 250C Probe +25 C (Logic & Flash) 100% COLD Test -45C 100% HOT Test 145C Wafer Mapping Wafer Mapping QA Gates QA Gates Assembly Assembly Dry Bake 125C Dry Bake 125C Pack & Ship Pack & Ship Page 5 of 6

6 5. Product Quality Customer Return Assessment It has been verified that all available customer returns (CQI) can be detected by the remaining test insertion(s). 6. Temperature Variation Analysis/Characterization It has been verified that the electrical data sheet specifications and test parameters are linear over temperature. Product characterization on material with variation typical of the wafer fabrication process window show that they are containable with the remaining test inserts. 7. Data Analysis and Verification Summary From the above data, it was verified that the the requirements and acceptance criteria based on Freescale specification 12MQS10030G was achieved. For the Final test flow, Room can be eliminated for Leopard (MPC5643L).. Page 6 of 6