M2 Instruction Set Architecture
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- Phillip Park
- 6 years ago
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1 M2 Instruction Set Architecture
2 Module Outline Addressing modes. Instruction classes. MIPS-I ISA. High level languages, Assembly languages and object code. Translating and starting a program. Subroutine and subroutine call. Use of stack for handling subroutine call and return.
3 Module Outline Addressing modes. Instruction classes. MIPS-I ISA. High level languages, Assembly languages and object code. Translating and starting a program. Subroutine and subroutine call. Use of stack for handling subroutine call and return.
4 MIPS-I Arithmetic Instructions Add, Subtract Mnemonics Example Meaning ADD, ADDU, ADDI, ADDIU, SUB, SUBU ADD R1, R2, R3 R1 R2 + R3 ADDU R1, R2, R3 R1 R2 + R3 ADDI R1, R2, 6 R Format op 6 bits rs rt 5 bits 5 bits OP rd, rs, rt rd 5 bits sh_amt 5 bits funct 6 bits op: Opcode (class of instruction). Eg. ALU funct: Which subunit of the ALU to activate? ADD op/funct = 0x0/0x20 sh_amt: Shift Amount. For Shift Instructions SLL, SRL.
5 MIPS-I Arithmetic Instructions Mnemonics Example Meaning Add, Subtract ADD, ADDU, ADDI, ADDIU, SUB, SUBU ADD R1, R2, R3 R1 R2 + R3 ADDI R1, R2, 6 R1 R2 + 6 Multiply, Divide MULT, DIV, MULTU, DIVU MULT R1, R2 LO lsw (R1 * R2) HI msw (R1 * R2)
6 MIPS-I Arithmetic Instructions Mnemonics Example Add, Subtract ADD, ADDU, ADDI, ADDIU, SUB, SUBU ADD R1, R2, R3 R1 R2 + R3 ADDI R1, R2, 6 R1 R2 + 6 Multiply, Divide MULT, DIV, MULTU, DIVU MULT R1, R2 Meaning LO lsw (R1 * R2) HI msw (R1 * R2) Product of two 32-bit numbers is a 64-bit quantity. HI and LO contain the MSW and LSW of the Product
7 MIPS-I Arithmetic Instructions Mnemonics Example Add, Subtract ADD, ADDU, ADDI, ADDIU, SUB, SUBU ADD R1, R2, R3 R1 R2 + R3 ADDI R1, R2, 6 R1 R2 + 6 Multiply, Divide MULT, DIV, MULTU, DIVU MULT R1, R2 Divide Operation Quotient in LO, Remainder in HI Meaning LO lsw (R1 * R2) HI msw (R1 * R2)
8 MIPS-I Arithmetic Instructions Mnemonics Example Meaning Add, Subtract ADD, ADDU, ADDI, ADDIU, SUB, SUBU ADD R1, R2, R3 R1 R2 + R3 ADDI R1, R2, 6 R1 R2 + 6 Multiply, Divide MULT, DIV, MULTU, DIVU MULT R1, R2 Logical AND, ANDI, OR, ORI, XOR, XORI, NOR OR R1, R2, 0xF R1 R2 SE(0xF) LO lsw (R1 * R2) HI msw (R1 * R2)
9 MIPS-I Control Transfer Instructions Mnemonics Conditional Branch BEQ, BNE Jump J, JR Jump and Link JAL, JALR System Call SYSCALL Example Meaning
10 MIPS-I Control Transfer Instructions Mnemonics Example Meaning Conditional Branch BEQ, BNE BEQ R2, R3, -16 If R2 == R3; Jump J, JR Jump and Link JAL, JALR System Call SYSCALL PC PC
11 MIPS-I Control Transfer Instructions Mnemonics Example Meaning Conditional Branch BEQ, BNE BEQ R2, R3, -16 If R2 == R3; Jump J, JR J target26 Jump and Link JAL, JALR System Call SYSCALL PC PC PC PC31-28 target26 00
12 MIPS-I Control Transfer Instructions Mnemonics Example Meaning Conditional Branch BEQ, BNE BEQ R2, R3, -16 If R2 == R3; Jump J, JR J target26 PC PC31-28 target26 00 Jump and Link JAL, JALR JALR R2 R31 PC + 4 PC R2 System Call SYSCALL PC PC
13 MIPS-I Control Transfer Instructions Mnemonics Example Meaning Conditional Branch BEQ, BNE BEQ R2, R3, -16 If R2 == R3; Jump J, JR J target26 PC PC31-28 target26 00 Jump and Link JAL, JALR JALR R2 R31 PC + 4 PC R2 System Call SYSCALL SYSCALL PC PC
14 MIPS-I Control Transfer Instructions Conditional Branch Mnemonics Example Meaning BEQ, BNE BGEZ, BLEZ BLTZ, BGTZ BEQ R2, R3, -16 If R2 == R3; PC PC
15 MIPS-I Control Transfer Instructions Conditional Branch Mnemonics Example Meaning BEQ, BNE BGEZ, BLEZ BLTZ, BGTZ BEQ R2, R3, -16 If R2 == R3; PC PC PC Relative Addressing
16 MIPS-I Control Transfer Instructions Mnemonics Example Meaning Conditional Branch BEQ, BNE BEQ R2, R3, -16 If R2 == R3; Jump J, JR J target26 PC PC J 0x475 PC PC31-28 target26 00
17
18 MIPS-I Control Transfer Instructions Mnemonics Example Meaning Conditional Branch BEQ, BNE BEQ R2, R3, -16 If R2 == R3; Jump J, JR J target26 PC PC J 0x475 J Format op Offset added to PC 6 bits 26 bits PC PC31-28 target26 00
19 MIPS-I Control Transfer Instructions Mnemonics Example Meaning Conditional Branch BEQ, BNE BEQ R2, R3, -16 If R2 == R3; Jump J, JR J target26 PC PC J 0x475 PC PC31-28 target26 00 PC before J 0101 PC after J
20 MIPS-I Control Transfer Instructions Mnemonics Example Meaning Conditional Branch BEQ, BNE BEQ R2, R3, -16 If R2 == R3; Jump J, JR J target26 PC PC J 0x475 PC PC31-28 target26 00 JR R2 PC R2
21 MIPS-I Control Transfer Instructions Mnemonics Example Meaning Conditional Branch BEQ, BNE BEQ R2, R3, -16 If R2 == R3; Jump J, JR J target26 PC PC31-28 target26 00 Jump and Link JAL, JALR JAL target26 JALR R2 R31 PC + 4 PC R2 System Call SYSCALL SYSCALL PC PC
22 MIPS-I Control Transfer Instructions Mnemonics Example Meaning Conditional Branch BEQ, BNE BEQ R2, R3, -16 If R2 == R3; Jump J, JR J target26 PC PC31-28 target26 00 Jump and Link JAL, JALR JAL target26 JALR R2 R31 PC + 4 PC R2 System Call SYSCALL SYSCALL PC PC
23 MIPS Instruction Formats R-type. op 6 bits rs rt 5 bits 5 bits OP rd, rs, rt I-type. op 6 bits rd 5 bits shamt 5 bits J-type rs rt 5 bits 5 bits immediate 16 bits op Offset added to PC 6 bits 26 bits OP LABEL 6 bits op: Opcode (class of instruction). Eg. ALU funct: Which subunit of the ALU to activate? OP rt, rs, IMM funct
24 How are the locations of operands and results specified in instructions?
25 MIPS-I Instruction Set Immediate, Register (for Arithmetic and Logic instructions) Absolute (for Jumps) Base-displacement (for Loads, Stores) PC relative (for conditional branches)
26 Addressing Mode Examples
27 ADD ADD R3, R3, R1, R1, R2 R2 R3 = R1 + R2 Register File R5 R4 R3 R2 R1 R
28 Register Addressing Mode Operand is in the specified general purpose register ADD ADD R3, R3, R1, R1, R2 R2 R3 = R1 + R2 Register File R5 R4 R3 R2 R1 R
29 ADD ADD R3, R3, R1, R1, #13 #13 R3 = R Register File R5 R4 R3 R2 R1 R
30 Immediate Addressing Mode Operand is a constant value specified inside the instruction. ADD ADD R3, R3, R1, R1, #13 #13 R3 = R Register File R5 R4 R3 R2 R1 R
31 ADD ADD R3, R3, R1, R1, (R2) (R2) R3 = R1 + M(0x104) Register File MEMORY R x108 0x104 0x100 R4 R3 R2 R1 R x
32 Register Indirect Addressing Mode Memory address of operand is in the specified general purpose register. ADD ADD R3, R3, R1, R1, (R2) (R2) R3 = R1 + M(0x104) Register File MEMORY R x108 0x104 0x100 R4 R3 R2 R1 R x
33 ADD ADD R3, R3, R1, R1, 4(R2) 4(R2) R3 = R1 + M(0x ) Register File MEMORY R x108 0x104 0x100 R4 R3 R2 R1 R x
34 Base Displacement Addressing Mode Memory address of operand is calculated as the sum of value in specified register and specified displacement ADD ADD R3, R3, R1, R1, 4(R2) 4(R2) R3 = R1 + M(0x ) Register File MEMORY R5 Can be used instead of Register indirect addressing mode x108 0x104 0x100 R4 R3 R2 R1 R x
35 R3 = R1 + M(0x104) ADD ADD R3, R3, R1, R1, (104) (104) Register File MEMORY R x108 0x104 0x100 R4 R3 R2 R1 R x
36 Absolute Addressing Mode Memory address of operand is specified directly in the instruction R3 = R1 + M(0x104) ADD ADD R3, R3, R1, R1, (104) (104) Register File MEMORY R x108 0x104 0x100 R4 R3 R2 R1 R x
37 R3 = R1 + M(R2+R4) ADD ADD R3, R3, R1, R1, (R2, (R2, R4) R4) Register File MEMORY R5 R2: Base of an array R4: Index x108 0x104 0x100 R4 R3 R2 R1 R0 0x x
38 Indexed Addressing Mode Memory address of operand is calculated as sum of contents of 2 registers R3 = R1 + M(R2+R4) ADD ADD R3, R3, R1, R1, (R2, (R2, R4) R4) Register File MEMORY R5 R2: Base of an array R4: Index x108 0x104 0x100 R4 R3 R2 R1 R0 0x x
39 R3 = R1 + M(M(R2)) ADD ADD R3, R3, MEMORY Register File x104 R5 0x108 0x104 0x100 R4 R3 R2 0x40 R1 R0 0x x40 124
40 Memory Indirect Addressing Mode A memory location is used as a pointer to the value in another location in memory R3 = R1 + M(M(R2)) ADD ADD R3, R3, MEMORY Register File x104 R5 0x108 0x104 0x100 R4 R3 R2 0x40 R1 R0 0x x40 124
41 R3 = R3 + M(R1) R1 = R1 + d ADD ADD R3, R3, (R1)+ (R1)+ Register File MEMORY R x108 0x104 0x100 R4 R3 R2 R1 R x104 0x100
42 Auto-Increment Addressing Mode Increment the value inside a register after the operation is completed. R3 = R3 + M(R1) R1 = R1 + d ADD ADD R3, R3, (R1)+ (R1)+ Register File MEMORY R5 Useful for stepping through arrays within a loop x108 0x104 0x100 R4 R3 R2 R1 R x104 0x100
43 ADD ADD R3, R3, -(R1) -(R1) - R1 = R1 d R3 = R3 + M(R1) Register File MEMORY R x108 0x104 0x100 R4 R3 R2 R1 R x104 0x100
44 Auto-Decrement Addressing Mode Decrement the value inside a register before the operation is completed. ADD ADD R3, R3, -(R1) -(R1) - R1 = R1 d R3 = R3 + M(R1) Register File MEMORY R5 PUSH/POP operations x108 0x104 0x100 R4 R3 R2 R1 R x104 0x100
45 ADD ADD R3, R3, 100(R1)[R3] 100(R1)[R3] R3 = R3 + M(100 + R1 + R3*d) MEMORY Register File x100 0x10C 0x108 0x104 0x100 R4 R3 R2 0x40 R1 R0 R x40
46 Scaled Addressing Mode Memory address of operand is calculated as sum of contents of 2 registers ADD ADD R3, R3, 100(R1)[R3] 100(R1)[R3] R3 = R3 + M(100 + R1 + R3*d) MEMORY Register File x100 0x10C 0x108 0x104 0x100 R4 R3 R2 0x40 R1 R0 R x40
47 PC = PC 16 JMP JMPloop loop 0x100 0x104 0x108 0x112 0x116 Loop: ADD XOR AND SUB JMP
48 PC Relative Addressing Mode The operand address is specified as a displacement from the PC value (i.e., from the address of the instruction itself) PC = PC 16 JMP JMPloop loop 0x100 0x104 0x108 0x112 0x116 Loop: ADD XOR AND SUB JMP
49 Add R1, R2, R3 Regs[R4] <- Regs[R3] + Regs[R2]
50 Add R1, R2, R3 Regs[R4] <- Regs[R3] + Regs[R2] Register
51 Add R1, R2, R3 Regs[R4] <- Regs[R3] + Regs[R2] Add R4, R3, #5 Regs[R4] <- Regs[R3] + 5 Register
52 Add R1, R2, R3 Regs[R4] <- Regs[R3] + Regs[R2] Register Add R4, R3, #5 Regs[R4] <- Regs[R3] + 5 Immediate
53 Add R1, R2, R3 Regs[R4] <- Regs[R3] + Regs[R2] Register Add R4, R3, #5 Regs[R4] <- Regs[R3] + 5 Immediate Add R4, R3, 100(R1) Regs[R4] <- Regs[R3] + Mem[100 + Regs[R1]]
54 Add R1, R2, R3 Regs[R4] <- Regs[R3] + Regs[R2] Register Add R4, R3, #5 Regs[R4] <- Regs[R3] + 5 Immediate Add R4, R3, 100(R1) Regs[R4] <- Regs[R3] + Mem[100 + Regs[R1]] Displacement
55 Add R1, R2, R3 Regs[R4] <- Regs[R3] + Regs[R2] Register Add R4, R3, #5 Regs[R4] <- Regs[R3] + 5 Immediate Add R4, R3, 100(R1) Regs[R4] <- Regs[R3] + Mem[100 + Regs[R1]] Displacement Add R4, R3, (R1) Regs[R4] <- Regs[R3] + Mem[Regs[R1]]
56 Add R1, R2, R3 Regs[R4] <- Regs[R3] + Regs[R2] Register Add R4, R3, #5 Regs[R4] <- Regs[R3] + 5 Immediate Add R4, R3, 100(R1) Regs[R4] <- Regs[R3] + Mem[100 + Regs[R1]] Displacement Add R4, R3, (R1) Regs[R4] <- Regs[R3] + Mem[Regs[R1]] Register Indirect
57 Add R1, R2, R3 Regs[R4] <- Regs[R3] + Regs[R2] Register Add R4, R3, #5 Regs[R4] <- Regs[R3] + 5 Immediate Add R4, R3, 100(R1) Regs[R4] <- Regs[R3] + Mem[100 + Regs[R1]] Displacement Add R4, R3, (R1) Regs[R4] <- Regs[R3] + Mem[Regs[R1]] Register Indirect Add R4, R3, (0x475) Regs[R4] <- Regs[R3] + Mem[0x475]
58 Add R1, R2, R3 Regs[R4] <- Regs[R3] + Regs[R2] Register Add R4, R3, #5 Regs[R4] <- Regs[R3] + 5 Immediate Add R4, R3, 100(R1) Regs[R4] <- Regs[R3] + Mem[100 + Regs[R1]] Displacement Add R4, R3, (R1) Regs[R4] <- Regs[R3] + Mem[Regs[R1]] Register Indirect Add R4, R3, (0x475) Regs[R4] <- Regs[R3] + Mem[0x475] Absolute
59 Add R1, R2, R3 Regs[R4] <- Regs[R3] + Regs[R2] Register Add R4, R3, #5 Regs[R4] <- Regs[R3] + 5 Immediate Add R4, R3, 100(R1) Regs[R4] <- Regs[R3] + Mem[100 + Regs[R1]] Displacement Add R4, R3, (R1) Regs[R4] <- Regs[R3] + Mem[Regs[R1]] Register Indirect Add R4, R3, (0x475) Regs[R4] <- Regs[R3] + Mem[0x475] Absolute Add R4, Regs[R4] <- Regs[R3] + Mem[Mem[R1]]
60 Add R1, R2, R3 Regs[R4] <- Regs[R3] + Regs[R2] Register Add R4, R3, #5 Regs[R4] <- Regs[R3] + 5 Immediate Add R4, R3, 100(R1) Regs[R4] <- Regs[R3] + Mem[100 + Regs[R1]] Displacement Add R4, R3, (R1) Regs[R4] <- Regs[R3] + Mem[Regs[R1]] Register Indirect Add R4, R3, (0x475) Regs[R4] <- Regs[R3] + Mem[0x475] Absolute Add R4, Regs[R4] <- Regs[R3] + Mem[Mem[R1]] Memory Indirect
61 Add R1, R2, R3 Regs[R4] <- Regs[R3] + Regs[R2] Register Add R4, R3, #5 Regs[R4] <- Regs[R3] + 5 Immediate Add R4, R3, 100(R1) Regs[R4] <- Regs[R3] + Mem[100 + Regs[R1]] Displacement Add R4, R3, (R1) Regs[R4] <- Regs[R3] + Mem[Regs[R1]] Register Indirect Add R4, R3, (0x475) Regs[R4] <- Regs[R3] + Mem[0x475] Absolute Add R4, Regs[R4] <- Regs[R3] + Mem[Mem[R1]] Memory Indirect Add R4, R3, 100(PC) Regs[R4] <- Regs[R3] + Mem[100 + PC]
62 Add R1, R2, R3 Regs[R4] <- Regs[R3] + Regs[R2] Register Add R4, R3, #5 Regs[R4] <- Regs[R3] + 5 Immediate Add R4, R3, 100(R1) Regs[R4] <- Regs[R3] + Mem[100 + Regs[R1]] Displacement Add R4, R3, (R1) Regs[R4] <- Regs[R3] + Mem[Regs[R1]] Register Indirect Add R4, R3, (0x475) Regs[R4] <- Regs[R3] + Mem[0x475] Absolute Add R4, Regs[R4] <- Regs[R3] + Mem[Mem[R1]] Memory Indirect Add R4, R3, 100(PC) Regs[R4] <- Regs[R3] + Mem[100 + PC] PC relative
63 Add R1, R2, R3 Regs[R4] <- Regs[R3] + Regs[R2] Register Add R4, R3, #5 Regs[R4] <- Regs[R3] + 5 Immediate Add R4, R3, 100(R1) Regs[R4] <- Regs[R3] + Mem[100 + Regs[R1]] Displacement Add R4, R3, (R1) Regs[R4] <- Regs[R3] + Mem[Regs[R1]] Register Indirect Add R4, R3, (0x475) Regs[R4] <- Regs[R3] + Mem[0x475] Absolute Add R4, Regs[R4] <- Regs[R3] + Mem[Mem[R1]] Memory Indirect Add R4, R3, 100(PC) Regs[R4] <- Regs[R3] + Mem[100 + PC] PC relative Add R4, R3, 100(R1)[R5] Regs[R4] <- Regs[R3] + Mem[100 + Regs[R1] + Regs[R5] * 4]
64 Add R1, R2, R3 Regs[R4] <- Regs[R3] + Regs[R2] Register Add R4, R3, #5 Regs[R4] <- Regs[R3] + 5 Immediate Add R4, R3, 100(R1) Regs[R4] <- Regs[R3] + Mem[100 + Regs[R1]] Displacement Add R4, R3, (R1) Regs[R4] <- Regs[R3] + Mem[Regs[R1]] Register Indirect Add R4, R3, (0x475) Regs[R4] <- Regs[R3] + Mem[0x475] Absolute Add R4, Regs[R4] <- Regs[R3] + Mem[Mem[R1]] Memory Indirect Add R4, R3, 100(PC) Regs[R4] <- Regs[R3] + Mem[100 + PC] PC relative Add R4, R3, 100(R1)[R5] Regs[R4] <- Regs[R3] + Mem[100 + Regs[R1] + Regs[R5] * 4] Scaled
65 Add R1, R2, R3 Regs[R4] <- Regs[R3] + Regs[R2] Register Add R4, R3, #5 Regs[R4] <- Regs[R3] + 5 Immediate Add R4, R3, 100(R1) Regs[R4] <- Regs[R3] + Mem[100 + Regs[R1]] Displacement Add R4, R3, (R1) Regs[R4] <- Regs[R3] + Mem[Regs[R1]] Register Indirect Add R4, R3, (0x475) Regs[R4] <- Regs[R3] + Mem[0x475] Absolute Add R4, Regs[R4] <- Regs[R3] + Mem[Mem[R1]] Memory Indirect Add R4, R3, 100(PC) Regs[R4] <- Regs[R3] + Mem[100 + PC] PC relative Add R4, R3, 100(R1)[R5] Regs[R4] <- Regs[R3] + Mem[100 + Regs[R1] + Regs[R5] * 4] Scaled Add R4, (R3)+ Regs[R4] <- Regs[R4] + Mem[R3] Regs[R3] <- Regs[R3] + d
66 Add R1, R2, R3 Regs[R4] <- Regs[R3] + Regs[R2] Register Add R4, R3, #5 Regs[R4] <- Regs[R3] + 5 Immediate Add R4, R3, 100(R1) Regs[R4] <- Regs[R3] + Mem[100 + Regs[R1]] Displacement Add R4, R3, (R1) Regs[R4] <- Regs[R3] + Mem[Regs[R1]] Register Indirect Add R4, R3, (0x475) Regs[R4] <- Regs[R3] + Mem[0x475] Absolute Add R4, Regs[R4] <- Regs[R3] + Mem[Mem[R1]] Memory Indirect Add R4, R3, 100(PC) Regs[R4] <- Regs[R3] + Mem[100 + PC] PC relative Add R4, R3, 100(R1)[R5] Regs[R4] <- Regs[R3] + Mem[100 + Regs[R1] + Regs[R5] * 4] Scaled Add R4, (R3)+ Regs[R4] <- Regs[R4] + Mem[R3] Regs[R3] <- Regs[R3] + d Auto Increment
67 Add R1, R2, R3 Regs[R4] <- Regs[R3] + Regs[R2] Register Add R4, R3, #5 Regs[R4] <- Regs[R3] + 5 Immediate Add R4, R3, 100(R1) Regs[R4] <- Regs[R3] + Mem[100 + Regs[R1]] Displacement Add R4, R3, (R1) Regs[R4] <- Regs[R3] + Mem[Regs[R1]] Register Indirect Add R4, R3, (0x475) Regs[R4] <- Regs[R3] + Mem[0x475] Absolute Add R4, Regs[R4] <- Regs[R3] + Mem[Mem[R1]] Memory Indirect Add R4, R3, 100(PC) Regs[R4] <- Regs[R3] + Mem[100 + PC] PC relative Add R4, R3, 100(R1)[R5] Regs[R4] <- Regs[R3] + Mem[100 + Regs[R1] + Regs[R5] * 4] Scaled Add R4, (R3)+ Regs[R4] <- Regs[R4] + Mem[R3] Regs[R3] <- Regs[R3] + d Auto Increment Add R4, -(R3) Regs[R3] <- Regs[R3] - d Regs[R4] <- Regs[R4] + Mem[R3]
68 Add R1, R2, R3 Regs[R4] <- Regs[R3] + Regs[R2] Register Add R4, R3, #5 Regs[R4] <- Regs[R3] + 5 Immediate Add R4, R3, 100(R1) Regs[R4] <- Regs[R3] + Mem[100 + Regs[R1]] Displacement Add R4, R3, (R1) Regs[R4] <- Regs[R3] + Mem[Regs[R1]] Register Indirect Add R4, R3, (0x475) Regs[R4] <- Regs[R3] + Mem[0x475] Absolute Add R4, Regs[R4] <- Regs[R3] + Mem[Mem[R1]] Memory Indirect Add R4, R3, 100(PC) Regs[R4] <- Regs[R3] + Mem[100 + PC] PC relative Add R4, R3, 100(R1)[R5] Regs[R4] <- Regs[R3] + Mem[100 + Regs[R1] + Regs[R5] * 4] Scaled Add R4, (R3)+ Regs[R4] <- Regs[R4] + Mem[R3] Regs[R3] <- Regs[R3] + d Auto Increment Add R4, -(R3) Regs[R3] <- Regs[R3] - d Regs[R4] <- Regs[R4] + Mem[R3] Auto Decrement
69 Which ones should a new architecture support? What should be size of the displacement? What should be size of the immediate field?
70 Which ones should a new architecture support? What should be size of the displacement? What should be size of the immediate field? Benchmarks: GCC, Particle simulations (Physics, Chemistry), Large databases, Video encoding/decoding Popular Choices: Displacement, Immediate, Register Indirect 12 16b
71 Module Outline Instruction classes. MIPS-I ISA. Addressing modes High level languages, Assembly languages and object code. Subroutine and subroutine call. Translating and starting a program.
72 Extra Slides
73 MIPS-I Data Transfer Instructions Load Mnemonics Example Meaning LB, LBU, LH, LHU, LW, LUI LB R2, 4(R3) LH R2, 4(R3) LW R2, 4(R3) R215-0 Mem(R3 + 4)15-0 R Sign Extension LBU R2, 4(R3) LUI R2, 4(R3) R2 Memory 0x2D8A107F 0x F x104 R3 0x100
74 MIPS-I Data Transfer Instructions Mnemonics Example Meaning Load LB, LBU, LH, LHU, LW, LUI LW R2, 4(R3) R2 Mem(R3 + 4) Store SB, SH, SW SB R2, -8(R4) Mem(R4-8) R2 Move MFHI, MFLO, MTHI, MTLO MFHI R1 R2 HI L: Load S: Store M: Move from/to HI/LO B: Byte (8b), H: Half Word (16b), W: Word (32b) U: Upper I: Immediate
75 MIPS-I Arithmetic Instructions Mnemonics Example Add, Subtract ADD, ADDU, ADDI, ADDIU, SUB, SUBU ADD R1, R2, R3 R1 R2 + R3 ADDI R1, R2, 6 R1 R2 + 6 Multiply, Divide MULT, DIV, MULTU, DIVU MULT R1, R2 Divide Operation Quotient in LO, Remainder in HI Meaning LO lsw (R1 * R2) HI msw (R1 * R2)
76 x86 (IA-32) Instruction Encoding Instruction Prefix Up to four prefixes (1 byte each) Opcode 1, 2 or 3B ModR/M Scale,Index Base 1B (if needed) 1B (if needed) Displace ment Immediate 0,1,2, or 4B 0,1,2, or 4B (if needed) (if needed) x86 and x86-64 instruction format Possible instructions 1 to 18 bytes long REP MOVSB
77 ISA Examples
78 Arithmetic Example C code: f = (g + h) - (i + j); {f,g,h,i,j} in {$s0,$s1,$s2,$s3,$s4} Compiled MIPS code: add $t0, $s1, $s2 add $t1, $s3, $s4 sub $s0, $t0, $t1
79 R-format Example op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits add $t0, $s1, $s2 special $s1 $s2 $t0 0 add =
80 I-format Example op rs rt constant or address 6 bits 5 bits 5 bits 16 bits addi $t0, $s1, 10 addi $s1 $t = A16
Pipeline Hazards. See P&H Chapter 4.7. Hakim Weatherspoon CS 3410, Spring 2013 Computer Science Cornell University
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