Lecture 31 Caches II TIO Dan s great cache mnemonic. Issues with Direct-Mapped

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1 CS61C L31 Caches II (1) inst.eecs.berkeley.edu/~cs61c UC Berkeley CS61C : Machine Structures Lecture 31 Caches II Lecturer SOE Dan Garcia GPUs >> CPUs? Many are using graphics processing units on graphics cards for high-performance computing (HPC). Some early numbers show them to have 2x the performance of CPUs! Garcia, Fall 26 UCB Direct-Mapped Cache Terminology All fields are read as unsigned integers. Index: specifies the cache index (which row of the cache we should look in) Offset: once we ve found correct block, specifies which byte within the block we want -- I.e., which column Tag: the remaining bits after offset and index are determined; these are used to distinguish between all the memory addresses that map to the same location CS61C L31 Caches II (2) Garcia, Fall 26 UCB Issues with Direct-Mapped Since multiple memory addresses map to same cache index, how do we tell which one is in there? What if we have a block size > 1 byte? Answer: divide memory address into three fields HEIGHT WIDTH ttttttttttttttttt iiiiiiiiii oooo tag index byte to check to offset if have select within correct block block block TIO Dan s great cache mnemonic AREA (cache size, B) 2 (H+W) = 2 H * 2 W = HEIGHT (# of blocks) * WIDTH (size of one block, B/block) HEIGHT (# of blocks) WIDTH (size of one block, B/block) AREA (cache size, B) CS61C L31 Caches II (3) Garcia, Fall 26 UCB CS61C L31 Caches II (4) Garcia, Fall 26 UCB Caching Terminology When we try to read memory, 3 things can happen: 1. cache hit: cache block is valid and contains proper address, so read desired word 2. cache miss: nothing in cache in appropriate block, so fetch from memory 3. cache miss, block replacement: wrong data is in cache at appropriate block, so discard it and fetch desired data from memory (cache always copy) CS61C L31 Caches II (5) Garcia, Fall 26 UCB Accessing data in a direct mapped cache Ex.: 16KB of data, Memory direct-mapped, 4 word blocks Read 4 addresses 1. x14 2. x1c 3. x34 4. x814 Memory values on right: CS61C L31 Caches II (6) Address (hex)value of Word C a b c d C C e f g h i j k l Garcia, Fall 26 UCB

2 CS61C L31 Caches II (7) Accessing data in a direct mapped cache 4 Addresses: x14, x1c, x34, x814 4 Addresses divided (for convenience) into Tag, Index, Byte Offset fields KB Direct Mapped Cache, 16B blocks bit: determines whether anything is stored in that row (when computer initially turned on, all entries invalid) Index Tag x-3 x4-7 x8-b xc-f Garcia, Fall 26 UCB CS61C L31 Caches II (8) Garcia, Fall 26 UCB 1. Read x Index Tag x-3 x4-7 x8-b xc-f So we read block 1 (1) 1 1 Index Tag x-3 x4-7 x8-b xc-f CS61C L31 Caches II (9) Garcia, Fall 26 UCB CS61C L31 Caches II (1) Garcia, Fall 26 UCB No valid data 1 1 Index Tag x-3 x4-7 x8-b xc-f So load that data into cache, setting tag, valid 1 1 Index Tag x-3 x4-7 x8-b xc-f 1 1 a b c d CS61C L31 Caches II (11) Garcia, Fall 26 UCB CS61C L31 Caches II (12) Garcia, Fall 26 UCB

3 CS61C L31 Caches II (13) Read from cache at offset, return word b 1 1 Index Tag x-3 x4-7 x8-b xc-f 1 1 a b c d Read x1c = Index Tag x-3 x4-7 x8-b xc-f 1 1 a b c d Garcia, Fall 26 UCB CS61C L31 Caches II (14) Garcia, Fall 26 UCB Index is 1 11 Index Tag x-3 x4-7 x8-b xc-f 1 1 a b c d Index valid, Tag Matches 1 11 Index Tag x-3 x4-7 x8-b xc-f 1 1 a b c d CS61C L31 Caches II (15) Garcia, Fall 26 UCB CS61C L31 Caches II (16) Garcia, Fall 26 UCB Index, Tag Matches, return d 1 11 Index Tag x-3 x4-7 x8-b xc-f 1 1 a b c d Read x34 = Index Tag x-3 x4-7 x8-b xc-f 1 1 a b c d CS61C L31 Caches II (17) Garcia, Fall 26 UCB CS61C L31 Caches II (18) Garcia, Fall 26 UCB

4 CS61C L31 Caches II (19) So read block Index Tag x-3 x4-7 x8-b xc-f 1 1 a b c d No valid data 11 1 Index Tag x-3 x4-7 x8-b xc-f 1 1 a b c d Garcia, Fall 26 UCB CS61C L31 Caches II (2) Garcia, Fall 26 UCB Load that cache block, return word f 11 1 Index Tag x-3 x4-7 x8-b xc-f 1 1 a b c d e f g h Read x814 = Index Tag x-3 x4-7 x8-b xc-f 1 1 a b c d e f g h CS61C L31 Caches II (21) Garcia, Fall 26 UCB CS61C L31 Caches II (22) Garcia, Fall 26 UCB So read Cache Block 1, Data is Index Tag x-3 x4-7 x8-b xc-f 1 1 a b c d e f g h Cache Block 1 Tag does not match (!= 2) Index Tag x-3 x4-7 x8-b xc-f 1 1 a b c d e f g h CS61C L31 Caches II (23) Garcia, Fall 26 UCB CS61C L31 Caches II (24) Garcia, Fall 26 UCB

5 CS61C L31 Caches II (25) Miss, so replace block 1 with new data & tag Index Tag x-3 x4-7 x8-b xc-f e f g h And return word j Index Tag x-3 x4-7 x8-b xc-f e f g h Garcia, Fall 26 UCB CS61C L31 Caches II (26) Garcia, Fall 26 UCB Do an example yourself. What happens? Chose from: Cache: Hit, Miss, Miss w. replace Values returned: a,b, c, d, e,, k, l Read address x3? 11 Read address x1c? 1 11 Cache Index Tag x-3 x4-7 x8-b xc-f e f g h CS61C L31 Caches II (27) Garcia, Fall 26 UCB Answers x3 a hit Memory Index = 3, Tag matches, Offset =, value = e Address Value of Word 1 a x1c a miss 14 b 18 c Index = 1, Tag mismatch, 1c d so replace from memory, Offset = xc, value = d Since reads, values must = memory values whether or not cached: x3 = e x1c = d CS61C L31 Caches II (28) c c e f g h i j k l Garcia, Fall 26 UCB Peer Instructions 1. All caches take advantage of spatial locality. 2. All caches take advantage of temporal locality. 3. On a read, the return value will depend on what is in the cache. CS61C L31 Caches II (3) ABC 1: FFF 2: FFT 3: FTF 4: FTT 5: TFF 6: TFT 7: TTF 8: TTT Garcia, Fall 26 UCB And in Conclusion Mechanism for transparent movement of data among levels of a storage hierarchy set of address/value bindings address index to set of candidates compare desired address with tag service hit or miss load new block and binding on miss address: tag index offset 1 11 Tag x-3 x4-7 x8-b xc-f 1 a b c d CS61C L31 Caches II (32) Garcia, Fall 26 UCB