CSCI 510: Computer Architecture Written Assignment 2 Solutions
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1 CSCI 510: Computer Architecture Written Assignment 2 Solutions The following code does compution over two vectors. Consider different execution scenarios and provide the average number of cycles per iterion for each of them. DADDIU R4,R1,#800 ; R1 = upper bound for X foo: L.D F2,0(R1) ; (F2) = X(i) MUL.D F2,F2,F0 ; (F2) = a*x(i) L.D F6,0(R2) ; (F6) = Y(i) DIV.D F6,F6,F8 ; (F6) = Y(i)/b SUB.D F6,F2,F6 ; (F6) = a*x(i) - Y(i)/b S.D F6,0(R1) ; X(i) = a*x(i) - Y(i)/b DADDIU R1,R1,#8 ; increment X index DADDIU R2,R2,#8 ; increment Y index DSLTU R3,R1,R4 ; test: continue loop? BNEZ R3,foo ; loop if needed Operions Number of Clock Cycles for the Execution Stage Floing Point Multiplicion 5 Floing Point Division 15 Floing Point Subtraction 2 Integer Calculion 1 Memory Access 1 1) (10 pts) Assume a single-issue pipeline not using Tomasulo s algorithm. Show how an iterion of the loop would execute without being scheduled by compiler. Clock Cycle 1 L.D F2, 0(R1) 2 MUL.D F2, F2, F0 3 L.D F6, 0(R2) 4 DIV.D F6, F6, F8 Stall for 14 cycles 19 SUB.D F6, F2, F6 Stall for 1 cycle 21 S.D F6, 0(R1)
2 22 DADDIU R1, R1, #8 23 DADDIU R2, R2, #8 24 DSLTU R3, R1, R4 25 BNEZ R3, foo 2) (20 pts) Assume a single-issue pipeline not using Tomasulo s algorithm. Unroll the loop as many times as necessary and schedule it without any stalls, collapsing the loop overhead instructions. Show the execution of the scheduled unrolled code. Clock Cycle 1 L.D F6, 0(R2) 2 L.D F7, 8(R2) 3 L.D F9, 16(R2) 4 L.D F10, 24(R2) 5 DIV.D F6, F6, F8 6 DIV.D F7, F7, F8 7 DIV.D F9, F9, F8 8 DIV.D F10, F10, F8 9 L.D F2, 0(R1) 10 L.D F3, 8(R1) 11 L.D F4, 16(R1) 12 L.D F5, 24(R1) 13 MUL.D F2, F2, F0 14 MUL.D F3, F3, F0 15 MUL.D F4, F4, F0 16 MUL.D F5, F5, F0 17 DADDIU R1, R1, #32 18 DADDIU R2, R2, #32 19 DSLTU R3, R1, R4 20 SUB.D F6, F2, F6 21 SUB.D F7, F3, F7 22 SUB.D F9, F4, F9 23 SUB.D F10, F5, F10 24 S.D F6, -32(R1) 25 S.D F7, -24(R1) 26 S.D F9, -16(R1) 27 S.D F10, -8(R1) 28 BNEZ R3, foo 3) (20 pts) Assume a VLIW processor with instructions th contain three operions (1 floing point, 1 memory access and 1 integer or branch). Unroll the loop as many times as necessary and schedule it without any stalls, collapsing the loop overhead instructions. Wh percent of the operion slots are used in each schedule? How much larger is the size of the code compared to the original? Wh is the total register demand? Memory Reference Floing Point Op. Integer/Branch 1 L.D F6, 0(R2)
3 2 L.D F7, 8(R2) DIV.D F6, F6, F8 3 L.D F9, 16(R2) DIV.D F7, F7, F8 4 L.D F10, 24(R2) DIV.D F9, F9, F8 5 L.D F11, 32(R2) DIV.D F10, F10, F8 6 L.D F12, 40(R2) DIV.D F11, F11, F8 7 L.D F13, 48(R2) DIV.D F12, F12, F8 8 L.D F14, 56(R2) DIV.D F13, F13, F8 9 L.D F2, 0(R1) DIV.D F14, F14, F8 10 L.D F3, 8(R1) MUL.D F2, F2, F0 11 L.D F4, 16(R1) MUL.D F3, F3, F0 12 L.D F5, 24(R1) MUL.D F4, F4, F0 13 L.D F15, 32(R1) MUL.D F5, F5, F0 14 L.D F16, 40(R1) MUL.D F15, F15, F0 15 L.D F17, 48(R1) MUL.D F16, F16, F0 16 L.D F18, 56(R1) MUL.D F17, F17, F0 17 MUL.D F18, F18, F0 18 SUB.D F6, F2, F6 19 SUB.D F7, F3, F7 20 S.D F6, 0(R1) SUB.D F9, F4, F9 21 S.D F7, 8(R1) SUB.D F10, F5, F10 22 S.D F9, 16(R1) SUB.D F11, F15, F11 23 S.D F10, 24(R1) SUB.D F12, F16, F12 24 S.D F11, 32(R1) SUB.D F13, F17, F13 DADDIU R1, R1, #64 25 S.D F12, -24(R1) SUB.D F14, F18, F14 DADDIU R2, R2, #64 26 S.D F13, -16(R1) DSLTU R3, R1, R4 27 S.D F14, -8(R1) NEZ R3, foo There are 26 3 = 78 slots. 25 are not used. (1 25 / 78) 100% 67.9% of the operions slots are used. Assume each instruction takes 32 bits. The original code has 10 instructions, and thus uses 320 bytes. The VLIW code has 78 instructions (each slot counted as one instructions), and thus uses = 2496 bytes and is 78/10 1 = 6.8 times larger. The VLIW code needs 17 floing point registers (14 more than the original code) and 4 integer registers. 4) (20 pts) Assume a single-issue pipeline using Tomasulo s algorithm without speculion. Show the execution of three iterions following the example given below. Assume 1 cycle stall for branch.
4 Iterion Issue Executes /Memory Write CDB Comment 1 L.D F2, 0(R1) MUL.D F2, F2, F Wait for L.D 1 L.D F6, 0(R2) DIV.D F6, F6, F SUB.D F6, F2, F Wait for DIV.D 1 S.D F6, 0(R1) 6 25 Wait for SUB.D 1 DADDIU R1, R1, # Wait for CDB 1 DADDIU R2, R2, # Wait for CDB 1 DSLTU R3, R1, R Wait for CDB 1 BNEZ R3, foo Wait for DSLTU 2 L.D F2, 0(R1) Stall for BNEZ 2 MUL.D F2, F2, F Wait for L.D 2 L.D F6, 0(R2) Wait for CDB Stall for BNEZ Wait for CDB 2 DIV.D F6, F6, F Wait for RS 2 SUB.D F6, F2, F Wait for DIV.D 2 S.D F6, 0(R1) Wait for SUB.D 2 DADDIU R1, R1, # DADDIU R2, R2, # DSLTU R3, R1, R BNEZ R3, foo Wait for DSLTU 3 L.D F2, 0(R1) Stall for BNEZ 3 MUL.D F2, F2, F Wait for L.D 3 L.D F6, 0(R2) Stall for BNEZ Wait for CDB 3 DIV.D F6, F6, F Wait for RS 3 SUB.D F6, F2, F Wait for DIV.D 3 S.D F6, 0(R1) Wait for SUB.D 3 DADDIU R1, R1, # DADDIU R2, R2, # DSLTU R3, R1, R BNEZ R3, foo Wait for DSLTU
5 5) (20 pts) Assume a single-issue pipeline using Tomasulo s algorithm with speculion. Show the execution of three iterions. Assume branches are predicted to be taken. Itrn Issue Executes /Memory Write CDB Commit Comment 1 L.D F2, 0(R1) MUL.D F2, F2, F Wait for L.D 1 L.D F6, 0(R2) DIV.D F6, F6, F SUB.D F6, F2, F Wait for DIV.D 1 S.D F6, 0(R1) Wait for SUB.D 1 DADDIU R1, R1, # Wait for CDB 1 DADDIU R2, R2, # DSLTU R3, R1, R Wait for DADDIU 1 BNEZ R3, foo Wait for DSLTU 2 L.D F2, 0(R1) MUL.D F2, F2, F Wait for L.D 2 L.D F6, 0(R2) DIV.D F6, F6, F Wait for RS 2 SUB.D F6, F2, F Wait for DIV.D 2 S.D F6, 0(R1) Wait for SUB.D 2 DADDIU R1, R1, # DADDIU R2, R2, # DSLTU R3, R1, R BNEZ R3, foo Wait for DSLTU 3 L.D F2, 0(R1) MUL.D F2, F2, F Wait for L.D 3 L.D F6, 0(R2) DIV.D F6, F6, F Wait for RS 3 SUB.D F6, F2, F Wait for DIV.D 3 S.D F6, 0(R1) Wait for SUB.D 3 DADDIU R1, R1, # DADDIU R2, R2, # DSLTU R3, R1, R BNEZ R3, foo Wait for DSLTU 6) (20 pts) Assume a dual-issue pipeline using Tomasulo s algorithm with speculion. Show the execution of three iterions. Assume branches are predicted to be taken. For 4) 5) 6), assume 5 reservion stions for integer operions, 3 reservion stions for load, 3 reservion stions for store, 2 reservion stions for floing point addition/subtraction, 2
6 reservion stions for floing point multiplicion/division. Also assume two function units of each type. Itrn Issue Executes /Memory Write CDB Commit Comment 1 L.D F2, 0(R1) MUL.D F2, F2, F L.D F6, 0(R2) DIV.D F6, F6, F SUB.D F6, F2, F S.D F6, 0(R1) DADDIU R1, R1, # DADDIU R2, R2, # DSLTU R3, R1, R BNEZ R3, foo L.D F2, 0(R1) MUL.D F2, F2, F L.D F6, 0(R2) DIV.D F6, F6, F Wait for RS 2 SUB.D F6, F2, F Wait for DIV.D 2 S.D F6, 0(R1) DADDIU R1, R1, # DADDIU R2, R2, # DSLTU R3, R1, R BNEZ R3, foo L.D F2, 0(R1) MUL.D F2, F2, F L.D F6, 0(R2) DIV.D F6, F6, F Wait for RS 3 SUB.D F6, F2, F Wait for DIV.D 3 S.D F6, 0(R1) DADDIU R1, R1, # DADDIU R2, R2, # DSLTU R3, R1, R BNEZ R3, foo
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