Future Trends in Microelectronic Device Packaging. Ziglioli Federico

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Sharon Donna Byrd
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1 Future Trends in Microelectronic Device Packaging Ziglioli Federico

2 What is Packaging for a Silicon Chip? 2 A CARRIER A thermal dissipator An electrical Connection

3 Packaging by Assy Techology 3 Technology platforms: Organic Substrate based packages (BGA/LGA) Metallic Leadframe based packages Wafer Level Packaging

4 Packaging by Applications 4 Sense MEMS and microphones (LGAs), Optical modules and Imagers towards BSI Power & BCD High dissipation, miniaturized packages (PSSO, QFNs) Digital with advanced CMOS Integration and miniaturization based on BGAs, QFPs. Towards Flip Chip &WLP

5 Organic Substrate - (BGA) Package 5 Layout flexibility IO density Suitable for System-In-Package integration Electrical performance Compatible with wire bonding and Flip-Chip technology

6 Wire Bonding Interconnection trends Ball Grid Array - New Packages Development 6 Flip Chip 3D adv Pack DCG-APG FCBGA FCBGA/ FCTEBGA CuP Emerging technologies 2,5D 2,1 D with Stacked memory PBGA BGA/PBGA CuWire BGA AgWire PoP CuP 3D,TSV, interposer BGA Std Basic platform Body >14² Body <14² BGA IBP-APG-MMS BGA Stacked BGA CuWire BGA AgWire FC CuP, Hybrid

7 Stacked BGAs: basic structures 7

8 Stacked BGA Evolution 8 10 stack 1.6mm 8 stack 1.4mm 4 stack 1.4mm 3 stack 1.0mm

9 Package on Package (PoP) : traditional structures 9 Bottom Package: Flip chip die Bottom Package: Wire bonded die Standard size: 12x12mm

10 Advanced LGA SIP 10 Stacked & side-by-side configuration Diode SMDs

11 Embedded Die 11 Integration, miniaturization, shielding, short interconnections Embedded die

12 Embedded Capacitors 12 Embedded SMDs

13 From BGA WB to FC or FCCP BGA 13 Conventional Wire Bonded BGA Device Substrate Flip Chip with solder ball bumps Si Al Flip Chip with Copper Pillar bumps

14 What s 3D IC? 14 3D already exist at die or package level: wire bonding stacked dies. POP STACK POP 3D IC is related to interconnecting dies with high density and performance connections using TSV (Through Silicon Via) & micro bumps. µbumps Thin die Active face Logic die Wide-IO DRAM die TSV Bumps Substrate

3D IC Main Technology Enablers 15 Stacking Process Accuracy Underfill Type (Capillary, NCP ) Process Top die Bottom die Substrate Micro bumping Type (Cu pillar, CuCu ) Pitch Electrical

15 3D IC Main Technology Enablers 15 Stacking Process Accuracy Underfill Type (Capillary, NCP ) Process Top die Bottom die Substrate Micro bumping Type (Cu pillar, CuCu ) Pitch Electrical performances Through silicon via (TSV) Type (via middle, via last ) Aspect ratio Electrical performances Thin wafer handling & processing Temporary carrier Compatibility with other process

16 die die wires Lead Frame Packages 16 leads full plastic exposed pad 1 layer metal frame with bent leads Reliability Thermal performance Cost but limited layout flexibility (only radial signals distribution)

17 Leads Shape Evolution 17 straight ( 70) J bent ( 80) gull wing ( 90) no leads! ( 00) DIP Power pack. PLCC, SOJ SO, TSOP, TSSOP, TQFP QFN, (BGA) pass through surface mount Methods to attach IC devices to PC board

18 Packaging Thickness Trend 18 Values in mm LQFP TQFP VQFPN U/W/VQFN-mr Resin /0.70/0.80 Die /0.140 Lead frame ~0.125 Standoff max max Total 1.60 max 1.20 max 1.00 max 0.65/0.8/1.0 max

19 QFNs Tapeless 19 Tapeless QFN QFN-mr (Quad Flatpack No lead Multi Row) QFN-sr (Quad Flatpack No lead Single Row)

20 QFN-mr: driving forces 20 L/TQFP exposed pad big dimensions thermal dissipation QFN-mr single row QFN pin count limited no leads BGA high cost & low power dissipation high pin count

21 QFN/QFN-mr: Package Characteristics 21 BGA cost & power dissipation e-tqfp dimensions & lead count QFN lead count QFN-mr package size (same I/O number) high pin count capability warpage excursion high frequency capability thermal dissipation MSL & SJR assembly (robust process) testing & finishing (robust process) TECHNOLOGY Multi row I/O Small footprint Free-routing cap. Single row I/O Large footprint Mature pck Single row I/O Small footprint Multi row I/O Smallest footprint Flexible I/O design worst best

22 Wafer Level Packaging 22 Fan In-WLP Fan Out-WLP (ewlb) Solder ball UBM (Under Bump Metallurgy) RDL (Al,Cu) Si Chip Solder ball Cu-RDL Si Chip EMC

23 Thank You! Packaging by ST

Semiconductor Manufacturing Technology. Semiconductor Manufacturing Technology

Semiconductor Manufacturing Technology Michael Quirk & Julian Serda October 2001 by Prentice Hall Chapter 20 Assembly and Packaging Four Important Functions of IC Packaging 1. Protection from the environment