Coreless Packaging Technology for High-performance Application

Size: px

Start display at page:

Download "Coreless Packaging Technology for High-performance Application"

Emory Andrews
5 years ago
Views:

1 62 nd ECTC San Diego, CA: May 29 June 1, 2012 Coreless Packaging Technology for High-performance Application Corp Advanced LSI Assembly Product Department Analog LSI Bussiness Division Semiconductor Business -1-

2 Agenda s Coreless Package Status What is Coreless Package? Advantages in Electrical Design Problem and Solution for Assembly Issue Next Challenges -2-

3 Agenda s Coreless Package Status What is Coreless Package? Advantages in Electrical Design Problem and Solution for Assembly Issue Next Challenges -3-

4 s Coreless Package Status Started Mass-Production for CPU application (CELL) with Coreless Substrate from April/2010. Accumulative shipments of Coreless Package ; Over 10 million Assembly Yield ; >99.9% -4-

5 Agenda s Coreless Package Status What is Coreless Package? Advantages in Electrical Design Problem and Solution for Assembly Issue Next Challenges -5-

6 What is Coreless Package? Coreless package Package with high density wiring by using only build-up process Coreless Package Coreless Substrate Lid Conventional Chip Build-up Substrate Core Build-up Layer Micro-via -6-

7 Where Coreless used for? High-Speed Signal Datarate Requirement High-Quality Power Delivery Requirement Ceramic Sub. FC 20~25Gbps/line Organic Sub. FC (Cored technology) Organic Coreless BGA s Possible Target Organic Sub. WB Pacakge Cost Package Substrate Pyramid Coreless can replace cored substrates for SI/PI improvement!! several ceramic substrates for Cost down!! -7-

8 Summary of Advantage and Disadvantage Good electrical property, low cost and high wiring-ability by eliminating of core process Enhanced assembly technique is needed because of low rigidity Advantage Cost reduction by eliminating of core process The limit of C4 layout is extremely little because of the improvement of wiring-ability Good high-speed transmission characteristic Disadvantage Bad chip joint yield in a current assembly process because warpage control is difficult Laminate chipping is occurred easily New manufacturing infrastructure for coreless packaging is necessary Power characteristic of both AC and DC are improved -8-

9 Agenda s Coreless Package Status What is Coreless Package? Advantages in Electrical Design Problem and Solution for Assembly Issue Next Challenges -9-

10 Advantages in Electrical Design Wiring Capability - Non-PTH structure allows direct signaling, and full-layer signaling. High PI Performance (PTH: Plated Through Hole) - Non-PTH PDN remarkably reduces AC impedance. High SI Performance - Coreless signal wiring avoids big return loss at PTHs. -10-

Package ~300um - Direct signaling is available.

11 Wiring Capability Build-up Package ~150um - You must make fan-out region to fit the C4/line pitch into the big PTH pitch Coreless Package ~300um - Direct signaling is available. - All layers can be used as signal layer. Designer can use the wiring area with maximum efficiency. -11-

12 Why? High PI Performance Because of the lowest self and highest mutual inductances of package PDN. L total =L vdd +L vss -2M VSS Chip VDD Min. chip-to-caps distance (lower L) Build-up = ~ 1 mmt Coreless = ~300 umt I vdd M I vss Parallel High Density Via (lower L) Build-up = 300 ph/1pth Coreless = 150 ph/1via 40 ph/4via PT H V V V V Decoupling Capacitors Min. VDD-VSS via distance (higher M) Build-up = 300um Coreless = 150um -12-

13 Package VDD Impedance [ohm] High PI Performance AC Impedance Improvement (Substrate + decap ) - Coreless package has 25% advantage compared to cored package. - AC noise becomes lower, then results in system voltage & power reduction. VDD C4 side BGA side Cored pkg Coreless pkg Package Bottom Decap 25% Cut VSS 10MHz 100MHz 1GHz Frequency -13-

14 High SI Performance Where Coreless can contributes? - In FC-BGA, the big two of Z0 mismatch points at signal transmission are PTH & ball. - We cannot remove both of them, but we can remove one of them: PTH. TX PTH Z0 mismatch!! Ball -14-

Insertion Loss, db Return Loss, db High SI Performance Coreless substrate is

Coreless -15dB 35-umt Via Via dia: 70/60 um Via pitch: 185 um Via land dia: 120 um

Via only 800-umt Core PTH dia: 300 um PTH pitch: 600 um PTH land dia: 500um

15 Insertion Loss, db Return Loss, db High SI Performance Coreless substrate is potentially the widest bandwidth substrate structure. Coreless -15dB 35-umt Via Via dia: 70/60 um Via pitch: 185 um Via land dia: 120 um Standard Thincore Standard Thincore Coreless Return Loss of Diff. Via only 800-umt Core PTH dia: 300 um PTH pitch: 600 um PTH land dia: 500um 400-umt Core PTH dia: 120 um PTH pitch: 300 um PTH land dia: 250um -3dB 凡例 Standard Thincore Coreless Insertion Loss of Diff. Via only -15-

16 Agenda s Coreless Package Status What is Coreless Package? Advantages in Electrical Design Problem and Solution for Assembly Issue Next Challenges -16-

17 1. Warpage Problem for Assembly Build-up Substrate (0.4mmt Core) Warpage value ; 104μm Coreless Substrate Warpage value ; 354μm -17-

18 Problem for Assembly 2. Warpage behavior at high temperature (1) Chip attach area warpage -18-

19 Solution To solve disadvantages of coreless, enhanced assembly process is applied Warpage ; Clumping jig is applied for chip attach process Key point Jig material (Stiffness property, CTE, Flatness) Clumping force Clumping position Laminate chipping ; Optimization of machine condition Package co-planarity ; Enhanced lid attach process -19-

20 Solution -20-

21 n (pcs) Package Co-planarity Specification Coreless Build-up (400μm Core) Ball coplanarity (um) 42.5 x 42.5mm Package -21-

22 Agenda s Coreless Package Status What is Coreless Package? Advantages in Electrical Design Problem and Solution for Assembly Issue Next Challenges -22-

23 Thank you -23-

Core Power Delivery Network Analysis of Core and Coreless Substrates in a Multilayer Organic Buildup Package

Core Power Delivery Network Analysis of Core and Coreless Substrates in a Multilayer Organic Buildup Package Ozgur Misman, Mike DeVita, Nozad Karim, Amkor Technology, AZ, USA 1900 S. Price Rd, Chandler,